ia64/linux-2.6.18-xen.hg

view arch/i386/kernel/io_apic-xen.c @ 659:ad374a7a9f3e

Revert 654:8925ce7552528 (linux/pci-msi: translate Xen-provided PIRQs)

Breaks the -xenU configuration ("MAX_IO_APICS undefined")

Also implicated in kernel crash during save/restore in our automated
tests.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Sep 05 12:39:29 2008 +0100 (2008-09-05)
parents 8925ce755252
children 7886619f623e
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
35 #include <asm/io.h>
36 #include <asm/smp.h>
37 #include <asm/desc.h>
38 #include <asm/timer.h>
39 #include <asm/i8259.h>
40 #include <asm/nmi.h>
42 #include <mach_apic.h>
44 #include "io_ports.h"
46 #ifdef CONFIG_XEN
48 #include <xen/interface/xen.h>
49 #include <xen/interface/physdev.h>
51 /* Fake i8259 */
52 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
53 #define disable_8259A_irq(_irq) ((void)0)
54 #define i8259A_irq_pending(_irq) (0)
56 unsigned long io_apic_irqs;
58 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
59 {
60 struct physdev_apic apic_op;
61 int ret;
63 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
64 apic_op.reg = reg;
65 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
66 if (ret)
67 return ret;
68 return apic_op.value;
69 }
71 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
72 {
73 struct physdev_apic apic_op;
75 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
76 apic_op.reg = reg;
77 apic_op.value = value;
78 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
79 }
81 #define io_apic_read(a,r) xen_io_apic_read(a,r)
82 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
84 #endif /* CONFIG_XEN */
86 int (*ioapic_renumber_irq)(int ioapic, int irq);
87 atomic_t irq_mis_count;
89 /* Where if anywhere is the i8259 connect in external int mode */
90 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92 static DEFINE_SPINLOCK(ioapic_lock);
93 static DEFINE_SPINLOCK(vector_lock);
95 int timer_over_8254 __initdata = 1;
97 /*
98 * Is the SiS APIC rmw bug present ?
99 * -1 = don't know, 0 = no, 1 = yes
100 */
101 int sis_apic_bug = -1;
103 /*
104 * # of IRQ routing registers
105 */
106 int nr_ioapic_registers[MAX_IO_APICS];
108 int disable_timer_pin_1 __initdata;
110 /*
111 * Rough estimation of how many shared IRQs there are, can
112 * be changed anytime.
113 */
114 #define MAX_PLUS_SHARED_IRQS NR_IRQS
115 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
117 /*
118 * This is performance-critical, we want to do it O(1)
119 *
120 * the indexing order of this array favors 1:1 mappings
121 * between pins and IRQs.
122 */
124 static struct irq_pin_list {
125 int apic, pin, next;
126 } irq_2_pin[PIN_MAP_SIZE];
128 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
129 #ifdef CONFIG_PCI_MSI
130 #define vector_to_irq(vector) \
131 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
132 #else
133 #define vector_to_irq(vector) (vector)
134 #endif
136 /*
137 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
138 * shared ISA-space IRQs, so we have to support them. We are super
139 * fast in the common case, and fast for shared ISA-space IRQs.
140 */
141 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
142 {
143 static int first_free_entry = NR_IRQS;
144 struct irq_pin_list *entry = irq_2_pin + irq;
146 while (entry->next)
147 entry = irq_2_pin + entry->next;
149 if (entry->pin != -1) {
150 entry->next = first_free_entry;
151 entry = irq_2_pin + entry->next;
152 if (++first_free_entry >= PIN_MAP_SIZE)
153 panic("io_apic.c: whoops");
154 }
155 entry->apic = apic;
156 entry->pin = pin;
157 }
159 #ifdef CONFIG_XEN
160 #define clear_IO_APIC() ((void)0)
161 #else
162 /*
163 * Reroute an IRQ to a different pin.
164 */
165 static void __init replace_pin_at_irq(unsigned int irq,
166 int oldapic, int oldpin,
167 int newapic, int newpin)
168 {
169 struct irq_pin_list *entry = irq_2_pin + irq;
171 while (1) {
172 if (entry->apic == oldapic && entry->pin == oldpin) {
173 entry->apic = newapic;
174 entry->pin = newpin;
175 }
176 if (!entry->next)
177 break;
178 entry = irq_2_pin + entry->next;
179 }
180 }
182 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
183 {
184 struct irq_pin_list *entry = irq_2_pin + irq;
185 unsigned int pin, reg;
187 for (;;) {
188 pin = entry->pin;
189 if (pin == -1)
190 break;
191 reg = io_apic_read(entry->apic, 0x10 + pin*2);
192 reg &= ~disable;
193 reg |= enable;
194 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
195 if (!entry->next)
196 break;
197 entry = irq_2_pin + entry->next;
198 }
199 }
201 /* mask = 1 */
202 static void __mask_IO_APIC_irq (unsigned int irq)
203 {
204 __modify_IO_APIC_irq(irq, 0x00010000, 0);
205 }
207 /* mask = 0 */
208 static void __unmask_IO_APIC_irq (unsigned int irq)
209 {
210 __modify_IO_APIC_irq(irq, 0, 0x00010000);
211 }
213 /* mask = 1, trigger = 0 */
214 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
215 {
216 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
217 }
219 /* mask = 0, trigger = 1 */
220 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
221 {
222 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
223 }
225 static void mask_IO_APIC_irq (unsigned int irq)
226 {
227 unsigned long flags;
229 spin_lock_irqsave(&ioapic_lock, flags);
230 __mask_IO_APIC_irq(irq);
231 spin_unlock_irqrestore(&ioapic_lock, flags);
232 }
234 static void unmask_IO_APIC_irq (unsigned int irq)
235 {
236 unsigned long flags;
238 spin_lock_irqsave(&ioapic_lock, flags);
239 __unmask_IO_APIC_irq(irq);
240 spin_unlock_irqrestore(&ioapic_lock, flags);
241 }
243 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
244 {
245 struct IO_APIC_route_entry entry;
246 unsigned long flags;
248 /* Check delivery_mode to be sure we're not clearing an SMI pin */
249 spin_lock_irqsave(&ioapic_lock, flags);
250 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
251 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
252 spin_unlock_irqrestore(&ioapic_lock, flags);
253 if (entry.delivery_mode == dest_SMI)
254 return;
256 /*
257 * Disable it in the IO-APIC irq-routing table:
258 */
259 memset(&entry, 0, sizeof(entry));
260 entry.mask = 1;
261 spin_lock_irqsave(&ioapic_lock, flags);
262 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
263 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
264 spin_unlock_irqrestore(&ioapic_lock, flags);
265 }
267 static void clear_IO_APIC (void)
268 {
269 int apic, pin;
271 for (apic = 0; apic < nr_ioapics; apic++)
272 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
273 clear_IO_APIC_pin(apic, pin);
274 }
276 #ifdef CONFIG_SMP
277 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
278 {
279 unsigned long flags;
280 int pin;
281 struct irq_pin_list *entry = irq_2_pin + irq;
282 unsigned int apicid_value;
283 cpumask_t tmp;
285 cpus_and(tmp, cpumask, cpu_online_map);
286 if (cpus_empty(tmp))
287 tmp = TARGET_CPUS;
289 cpus_and(cpumask, tmp, CPU_MASK_ALL);
291 apicid_value = cpu_mask_to_apicid(cpumask);
292 /* Prepare to do the io_apic_write */
293 apicid_value = apicid_value << 24;
294 spin_lock_irqsave(&ioapic_lock, flags);
295 for (;;) {
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
300 if (!entry->next)
301 break;
302 entry = irq_2_pin + entry->next;
303 }
304 set_irq_info(irq, cpumask);
305 spin_unlock_irqrestore(&ioapic_lock, flags);
306 }
308 #if defined(CONFIG_IRQBALANCE)
309 # include <asm/processor.h> /* kernel_thread() */
310 # include <linux/kernel_stat.h> /* kstat */
311 # include <linux/slab.h> /* kmalloc() */
312 # include <linux/timer.h> /* time_after() */
314 #ifdef CONFIG_BALANCED_IRQ_DEBUG
315 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
316 # define Dprintk(x...) do { TDprintk(x); } while (0)
317 # else
318 # define TDprintk(x...)
319 # define Dprintk(x...)
320 # endif
322 #define IRQBALANCE_CHECK_ARCH -999
323 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
324 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
325 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
326 #define BALANCED_IRQ_LESS_DELTA (HZ)
328 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
329 static int physical_balance __read_mostly;
330 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
332 static struct irq_cpu_info {
333 unsigned long * last_irq;
334 unsigned long * irq_delta;
335 unsigned long irq;
336 } irq_cpu_data[NR_CPUS];
338 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
339 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
340 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
342 #define IDLE_ENOUGH(cpu,now) \
343 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
345 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
347 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
349 static cpumask_t balance_irq_affinity[NR_IRQS] = {
350 [0 ... NR_IRQS-1] = CPU_MASK_ALL
351 };
353 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
354 {
355 balance_irq_affinity[irq] = mask;
356 }
358 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
359 unsigned long now, int direction)
360 {
361 int search_idle = 1;
362 int cpu = curr_cpu;
364 goto inside;
366 do {
367 if (unlikely(cpu == curr_cpu))
368 search_idle = 0;
369 inside:
370 if (direction == 1) {
371 cpu++;
372 if (cpu >= NR_CPUS)
373 cpu = 0;
374 } else {
375 cpu--;
376 if (cpu == -1)
377 cpu = NR_CPUS-1;
378 }
379 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
380 (search_idle && !IDLE_ENOUGH(cpu,now)));
382 return cpu;
383 }
385 static inline void balance_irq(int cpu, int irq)
386 {
387 unsigned long now = jiffies;
388 cpumask_t allowed_mask;
389 unsigned int new_cpu;
391 if (irqbalance_disabled)
392 return;
394 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
395 new_cpu = move(cpu, allowed_mask, now, 1);
396 if (cpu != new_cpu) {
397 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
398 }
399 }
401 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
402 {
403 int i, j;
404 Dprintk("Rotating IRQs among CPUs.\n");
405 for_each_online_cpu(i) {
406 for (j = 0; j < NR_IRQS; j++) {
407 if (!irq_desc[j].action)
408 continue;
409 /* Is it a significant load ? */
410 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
411 useful_load_threshold)
412 continue;
413 balance_irq(i, j);
414 }
415 }
416 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
417 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
418 return;
419 }
421 static void do_irq_balance(void)
422 {
423 int i, j;
424 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
425 unsigned long move_this_load = 0;
426 int max_loaded = 0, min_loaded = 0;
427 int load;
428 unsigned long useful_load_threshold = balanced_irq_interval + 10;
429 int selected_irq;
430 int tmp_loaded, first_attempt = 1;
431 unsigned long tmp_cpu_irq;
432 unsigned long imbalance = 0;
433 cpumask_t allowed_mask, target_cpu_mask, tmp;
435 for_each_possible_cpu(i) {
436 int package_index;
437 CPU_IRQ(i) = 0;
438 if (!cpu_online(i))
439 continue;
440 package_index = CPU_TO_PACKAGEINDEX(i);
441 for (j = 0; j < NR_IRQS; j++) {
442 unsigned long value_now, delta;
443 /* Is this an active IRQ? */
444 if (!irq_desc[j].action)
445 continue;
446 if ( package_index == i )
447 IRQ_DELTA(package_index,j) = 0;
448 /* Determine the total count per processor per IRQ */
449 value_now = (unsigned long) kstat_cpu(i).irqs[j];
451 /* Determine the activity per processor per IRQ */
452 delta = value_now - LAST_CPU_IRQ(i,j);
454 /* Update last_cpu_irq[][] for the next time */
455 LAST_CPU_IRQ(i,j) = value_now;
457 /* Ignore IRQs whose rate is less than the clock */
458 if (delta < useful_load_threshold)
459 continue;
460 /* update the load for the processor or package total */
461 IRQ_DELTA(package_index,j) += delta;
463 /* Keep track of the higher numbered sibling as well */
464 if (i != package_index)
465 CPU_IRQ(i) += delta;
466 /*
467 * We have sibling A and sibling B in the package
468 *
469 * cpu_irq[A] = load for cpu A + load for cpu B
470 * cpu_irq[B] = load for cpu B
471 */
472 CPU_IRQ(package_index) += delta;
473 }
474 }
475 /* Find the least loaded processor package */
476 for_each_online_cpu(i) {
477 if (i != CPU_TO_PACKAGEINDEX(i))
478 continue;
479 if (min_cpu_irq > CPU_IRQ(i)) {
480 min_cpu_irq = CPU_IRQ(i);
481 min_loaded = i;
482 }
483 }
484 max_cpu_irq = ULONG_MAX;
486 tryanothercpu:
487 /* Look for heaviest loaded processor.
488 * We may come back to get the next heaviest loaded processor.
489 * Skip processors with trivial loads.
490 */
491 tmp_cpu_irq = 0;
492 tmp_loaded = -1;
493 for_each_online_cpu(i) {
494 if (i != CPU_TO_PACKAGEINDEX(i))
495 continue;
496 if (max_cpu_irq <= CPU_IRQ(i))
497 continue;
498 if (tmp_cpu_irq < CPU_IRQ(i)) {
499 tmp_cpu_irq = CPU_IRQ(i);
500 tmp_loaded = i;
501 }
502 }
504 if (tmp_loaded == -1) {
505 /* In the case of small number of heavy interrupt sources,
506 * loading some of the cpus too much. We use Ingo's original
507 * approach to rotate them around.
508 */
509 if (!first_attempt && imbalance >= useful_load_threshold) {
510 rotate_irqs_among_cpus(useful_load_threshold);
511 return;
512 }
513 goto not_worth_the_effort;
514 }
516 first_attempt = 0; /* heaviest search */
517 max_cpu_irq = tmp_cpu_irq; /* load */
518 max_loaded = tmp_loaded; /* processor */
519 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
521 Dprintk("max_loaded cpu = %d\n", max_loaded);
522 Dprintk("min_loaded cpu = %d\n", min_loaded);
523 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
524 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
525 Dprintk("load imbalance = %lu\n", imbalance);
527 /* if imbalance is less than approx 10% of max load, then
528 * observe diminishing returns action. - quit
529 */
530 if (imbalance < (max_cpu_irq >> 3)) {
531 Dprintk("Imbalance too trivial\n");
532 goto not_worth_the_effort;
533 }
535 tryanotherirq:
536 /* if we select an IRQ to move that can't go where we want, then
537 * see if there is another one to try.
538 */
539 move_this_load = 0;
540 selected_irq = -1;
541 for (j = 0; j < NR_IRQS; j++) {
542 /* Is this an active IRQ? */
543 if (!irq_desc[j].action)
544 continue;
545 if (imbalance <= IRQ_DELTA(max_loaded,j))
546 continue;
547 /* Try to find the IRQ that is closest to the imbalance
548 * without going over.
549 */
550 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
551 move_this_load = IRQ_DELTA(max_loaded,j);
552 selected_irq = j;
553 }
554 }
555 if (selected_irq == -1) {
556 goto tryanothercpu;
557 }
559 imbalance = move_this_load;
561 /* For physical_balance case, we accumlated both load
562 * values in the one of the siblings cpu_irq[],
563 * to use the same code for physical and logical processors
564 * as much as possible.
565 *
566 * NOTE: the cpu_irq[] array holds the sum of the load for
567 * sibling A and sibling B in the slot for the lowest numbered
568 * sibling (A), _AND_ the load for sibling B in the slot for
569 * the higher numbered sibling.
570 *
571 * We seek the least loaded sibling by making the comparison
572 * (A+B)/2 vs B
573 */
574 load = CPU_IRQ(min_loaded) >> 1;
575 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
576 if (load > CPU_IRQ(j)) {
577 /* This won't change cpu_sibling_map[min_loaded] */
578 load = CPU_IRQ(j);
579 min_loaded = j;
580 }
581 }
583 cpus_and(allowed_mask,
584 cpu_online_map,
585 balance_irq_affinity[selected_irq]);
586 target_cpu_mask = cpumask_of_cpu(min_loaded);
587 cpus_and(tmp, target_cpu_mask, allowed_mask);
589 if (!cpus_empty(tmp)) {
591 Dprintk("irq = %d moved to cpu = %d\n",
592 selected_irq, min_loaded);
593 /* mark for change destination */
594 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
596 /* Since we made a change, come back sooner to
597 * check for more variation.
598 */
599 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
600 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
601 return;
602 }
603 goto tryanotherirq;
605 not_worth_the_effort:
606 /*
607 * if we did not find an IRQ to move, then adjust the time interval
608 * upward
609 */
610 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
611 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
612 Dprintk("IRQ worth rotating not found\n");
613 return;
614 }
616 static int balanced_irq(void *unused)
617 {
618 int i;
619 unsigned long prev_balance_time = jiffies;
620 long time_remaining = balanced_irq_interval;
622 daemonize("kirqd");
624 /* push everything to CPU 0 to give us a starting point. */
625 for (i = 0 ; i < NR_IRQS ; i++) {
626 irq_desc[i].pending_mask = cpumask_of_cpu(0);
627 set_pending_irq(i, cpumask_of_cpu(0));
628 }
630 for ( ; ; ) {
631 time_remaining = schedule_timeout_interruptible(time_remaining);
632 try_to_freeze();
633 if (time_after(jiffies,
634 prev_balance_time+balanced_irq_interval)) {
635 preempt_disable();
636 do_irq_balance();
637 prev_balance_time = jiffies;
638 time_remaining = balanced_irq_interval;
639 preempt_enable();
640 }
641 }
642 return 0;
643 }
645 static int __init balanced_irq_init(void)
646 {
647 int i;
648 struct cpuinfo_x86 *c;
649 cpumask_t tmp;
651 cpus_shift_right(tmp, cpu_online_map, 2);
652 c = &boot_cpu_data;
653 /* When not overwritten by the command line ask subarchitecture. */
654 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
655 irqbalance_disabled = NO_BALANCE_IRQ;
656 if (irqbalance_disabled)
657 return 0;
659 /* disable irqbalance completely if there is only one processor online */
660 if (num_online_cpus() < 2) {
661 irqbalance_disabled = 1;
662 return 0;
663 }
664 /*
665 * Enable physical balance only if more than 1 physical processor
666 * is present
667 */
668 if (smp_num_siblings > 1 && !cpus_empty(tmp))
669 physical_balance = 1;
671 for_each_online_cpu(i) {
672 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
673 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
674 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
675 printk(KERN_ERR "balanced_irq_init: out of memory");
676 goto failed;
677 }
678 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
679 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
680 }
682 printk(KERN_INFO "Starting balanced_irq\n");
683 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
684 return 0;
685 else
686 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
687 failed:
688 for_each_possible_cpu(i) {
689 kfree(irq_cpu_data[i].irq_delta);
690 irq_cpu_data[i].irq_delta = NULL;
691 kfree(irq_cpu_data[i].last_irq);
692 irq_cpu_data[i].last_irq = NULL;
693 }
694 return 0;
695 }
697 int __init irqbalance_disable(char *str)
698 {
699 irqbalance_disabled = 1;
700 return 1;
701 }
703 __setup("noirqbalance", irqbalance_disable);
705 late_initcall(balanced_irq_init);
706 #endif /* CONFIG_IRQBALANCE */
707 #endif /* CONFIG_SMP */
708 #endif
710 #ifndef CONFIG_SMP
711 void fastcall send_IPI_self(int vector)
712 {
713 #ifndef CONFIG_XEN
714 unsigned int cfg;
716 /*
717 * Wait for idle.
718 */
719 apic_wait_icr_idle();
720 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
721 /*
722 * Send the IPI. The write to APIC_ICR fires this off.
723 */
724 apic_write_around(APIC_ICR, cfg);
725 #endif
726 }
727 #endif /* !CONFIG_SMP */
730 /*
731 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
732 * specific CPU-side IRQs.
733 */
735 #define MAX_PIRQS 8
736 static int pirq_entries [MAX_PIRQS];
737 static int pirqs_enabled;
738 int skip_ioapic_setup;
740 static int __init ioapic_setup(char *str)
741 {
742 skip_ioapic_setup = 1;
743 return 1;
744 }
746 __setup("noapic", ioapic_setup);
748 static int __init ioapic_pirq_setup(char *str)
749 {
750 int i, max;
751 int ints[MAX_PIRQS+1];
753 get_options(str, ARRAY_SIZE(ints), ints);
755 for (i = 0; i < MAX_PIRQS; i++)
756 pirq_entries[i] = -1;
758 pirqs_enabled = 1;
759 apic_printk(APIC_VERBOSE, KERN_INFO
760 "PIRQ redirection, working around broken MP-BIOS.\n");
761 max = MAX_PIRQS;
762 if (ints[0] < MAX_PIRQS)
763 max = ints[0];
765 for (i = 0; i < max; i++) {
766 apic_printk(APIC_VERBOSE, KERN_DEBUG
767 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
768 /*
769 * PIRQs are mapped upside down, usually.
770 */
771 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
772 }
773 return 1;
774 }
776 __setup("pirq=", ioapic_pirq_setup);
778 /*
779 * Find the IRQ entry number of a certain pin.
780 */
781 static int find_irq_entry(int apic, int pin, int type)
782 {
783 int i;
785 for (i = 0; i < mp_irq_entries; i++)
786 if (mp_irqs[i].mpc_irqtype == type &&
787 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
788 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
789 mp_irqs[i].mpc_dstirq == pin)
790 return i;
792 return -1;
793 }
795 /*
796 * Find the pin to which IRQ[irq] (ISA) is connected
797 */
798 static int __init find_isa_irq_pin(int irq, int type)
799 {
800 int i;
802 for (i = 0; i < mp_irq_entries; i++) {
803 int lbus = mp_irqs[i].mpc_srcbus;
805 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
806 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
807 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
808 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
809 ) &&
810 (mp_irqs[i].mpc_irqtype == type) &&
811 (mp_irqs[i].mpc_srcbusirq == irq))
813 return mp_irqs[i].mpc_dstirq;
814 }
815 return -1;
816 }
818 static int __init find_isa_irq_apic(int irq, int type)
819 {
820 int i;
822 for (i = 0; i < mp_irq_entries; i++) {
823 int lbus = mp_irqs[i].mpc_srcbus;
825 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
826 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
827 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
828 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
829 ) &&
830 (mp_irqs[i].mpc_irqtype == type) &&
831 (mp_irqs[i].mpc_srcbusirq == irq))
832 break;
833 }
834 if (i < mp_irq_entries) {
835 int apic;
836 for(apic = 0; apic < nr_ioapics; apic++) {
837 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
838 return apic;
839 }
840 }
842 return -1;
843 }
845 /*
846 * Find a specific PCI IRQ entry.
847 * Not an __init, possibly needed by modules
848 */
849 static int pin_2_irq(int idx, int apic, int pin);
851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
852 {
853 int apic, i, best_guess = -1;
855 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
856 "slot:%d, pin:%d.\n", bus, slot, pin);
857 if (mp_bus_id_to_pci_bus[bus] == -1) {
858 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
859 return -1;
860 }
861 for (i = 0; i < mp_irq_entries; i++) {
862 int lbus = mp_irqs[i].mpc_srcbus;
864 for (apic = 0; apic < nr_ioapics; apic++)
865 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
866 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
867 break;
869 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
870 !mp_irqs[i].mpc_irqtype &&
871 (bus == lbus) &&
872 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
873 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
875 if (!(apic || IO_APIC_IRQ(irq)))
876 continue;
878 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
879 return irq;
880 /*
881 * Use the first all-but-pin matching entry as a
882 * best-guess fuzzy result for broken mptables.
883 */
884 if (best_guess < 0)
885 best_guess = irq;
886 }
887 }
888 return best_guess;
889 }
890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
892 /*
893 * This function currently is only a helper for the i386 smp boot process where
894 * we need to reprogram the ioredtbls to cater for the cpus which have come online
895 * so mask in all cases should simply be TARGET_CPUS
896 */
897 #ifdef CONFIG_SMP
898 #ifndef CONFIG_XEN
899 void __init setup_ioapic_dest(void)
900 {
901 int pin, ioapic, irq, irq_entry;
903 if (skip_ioapic_setup == 1)
904 return;
906 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
907 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
908 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
909 if (irq_entry == -1)
910 continue;
911 irq = pin_2_irq(irq_entry, ioapic, pin);
912 set_ioapic_affinity_irq(irq, TARGET_CPUS);
913 }
915 }
916 }
917 #endif /* !CONFIG_XEN */
918 #endif
920 /*
921 * EISA Edge/Level control register, ELCR
922 */
923 static int EISA_ELCR(unsigned int irq)
924 {
925 if (irq < 16) {
926 unsigned int port = 0x4d0 + (irq >> 3);
927 return (inb(port) >> (irq & 7)) & 1;
928 }
929 apic_printk(APIC_VERBOSE, KERN_INFO
930 "Broken MPtable reports ISA irq %d\n", irq);
931 return 0;
932 }
934 /* EISA interrupts are always polarity zero and can be edge or level
935 * trigger depending on the ELCR value. If an interrupt is listed as
936 * EISA conforming in the MP table, that means its trigger type must
937 * be read in from the ELCR */
939 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
940 #define default_EISA_polarity(idx) (0)
942 /* ISA interrupts are always polarity zero edge triggered,
943 * when listed as conforming in the MP table. */
945 #define default_ISA_trigger(idx) (0)
946 #define default_ISA_polarity(idx) (0)
948 /* PCI interrupts are always polarity one level triggered,
949 * when listed as conforming in the MP table. */
951 #define default_PCI_trigger(idx) (1)
952 #define default_PCI_polarity(idx) (1)
954 /* MCA interrupts are always polarity zero level triggered,
955 * when listed as conforming in the MP table. */
957 #define default_MCA_trigger(idx) (1)
958 #define default_MCA_polarity(idx) (0)
960 /* NEC98 interrupts are always polarity zero edge triggered,
961 * when listed as conforming in the MP table. */
963 #define default_NEC98_trigger(idx) (0)
964 #define default_NEC98_polarity(idx) (0)
966 static int __init MPBIOS_polarity(int idx)
967 {
968 int bus = mp_irqs[idx].mpc_srcbus;
969 int polarity;
971 /*
972 * Determine IRQ line polarity (high active or low active):
973 */
974 switch (mp_irqs[idx].mpc_irqflag & 3)
975 {
976 case 0: /* conforms, ie. bus-type dependent polarity */
977 {
978 switch (mp_bus_id_to_type[bus])
979 {
980 case MP_BUS_ISA: /* ISA pin */
981 {
982 polarity = default_ISA_polarity(idx);
983 break;
984 }
985 case MP_BUS_EISA: /* EISA pin */
986 {
987 polarity = default_EISA_polarity(idx);
988 break;
989 }
990 case MP_BUS_PCI: /* PCI pin */
991 {
992 polarity = default_PCI_polarity(idx);
993 break;
994 }
995 case MP_BUS_MCA: /* MCA pin */
996 {
997 polarity = default_MCA_polarity(idx);
998 break;
999 }
1000 case MP_BUS_NEC98: /* NEC 98 pin */
1002 polarity = default_NEC98_polarity(idx);
1003 break;
1005 default:
1007 printk(KERN_WARNING "broken BIOS!!\n");
1008 polarity = 1;
1009 break;
1012 break;
1014 case 1: /* high active */
1016 polarity = 0;
1017 break;
1019 case 2: /* reserved */
1021 printk(KERN_WARNING "broken BIOS!!\n");
1022 polarity = 1;
1023 break;
1025 case 3: /* low active */
1027 polarity = 1;
1028 break;
1030 default: /* invalid */
1032 printk(KERN_WARNING "broken BIOS!!\n");
1033 polarity = 1;
1034 break;
1037 return polarity;
1040 static int MPBIOS_trigger(int idx)
1042 int bus = mp_irqs[idx].mpc_srcbus;
1043 int trigger;
1045 /*
1046 * Determine IRQ trigger mode (edge or level sensitive):
1047 */
1048 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1050 case 0: /* conforms, ie. bus-type dependent */
1052 switch (mp_bus_id_to_type[bus])
1054 case MP_BUS_ISA: /* ISA pin */
1056 trigger = default_ISA_trigger(idx);
1057 break;
1059 case MP_BUS_EISA: /* EISA pin */
1061 trigger = default_EISA_trigger(idx);
1062 break;
1064 case MP_BUS_PCI: /* PCI pin */
1066 trigger = default_PCI_trigger(idx);
1067 break;
1069 case MP_BUS_MCA: /* MCA pin */
1071 trigger = default_MCA_trigger(idx);
1072 break;
1074 case MP_BUS_NEC98: /* NEC 98 pin */
1076 trigger = default_NEC98_trigger(idx);
1077 break;
1079 default:
1081 printk(KERN_WARNING "broken BIOS!!\n");
1082 trigger = 1;
1083 break;
1086 break;
1088 case 1: /* edge */
1090 trigger = 0;
1091 break;
1093 case 2: /* reserved */
1095 printk(KERN_WARNING "broken BIOS!!\n");
1096 trigger = 1;
1097 break;
1099 case 3: /* level */
1101 trigger = 1;
1102 break;
1104 default: /* invalid */
1106 printk(KERN_WARNING "broken BIOS!!\n");
1107 trigger = 0;
1108 break;
1111 return trigger;
1114 static inline int irq_polarity(int idx)
1116 return MPBIOS_polarity(idx);
1119 static inline int irq_trigger(int idx)
1121 return MPBIOS_trigger(idx);
1124 static int pin_2_irq(int idx, int apic, int pin)
1126 int irq, i;
1127 int bus = mp_irqs[idx].mpc_srcbus;
1129 /*
1130 * Debugging check, we are in big trouble if this message pops up!
1131 */
1132 if (mp_irqs[idx].mpc_dstirq != pin)
1133 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1135 switch (mp_bus_id_to_type[bus])
1137 case MP_BUS_ISA: /* ISA pin */
1138 case MP_BUS_EISA:
1139 case MP_BUS_MCA:
1140 case MP_BUS_NEC98:
1142 irq = mp_irqs[idx].mpc_srcbusirq;
1143 break;
1145 case MP_BUS_PCI: /* PCI pin */
1147 /*
1148 * PCI IRQs are mapped in order
1149 */
1150 i = irq = 0;
1151 while (i < apic)
1152 irq += nr_ioapic_registers[i++];
1153 irq += pin;
1155 /*
1156 * For MPS mode, so far only needed by ES7000 platform
1157 */
1158 if (ioapic_renumber_irq)
1159 irq = ioapic_renumber_irq(apic, irq);
1161 break;
1163 default:
1165 printk(KERN_ERR "unknown bus type %d.\n",bus);
1166 irq = 0;
1167 break;
1171 /*
1172 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1173 */
1174 if ((pin >= 16) && (pin <= 23)) {
1175 if (pirq_entries[pin-16] != -1) {
1176 if (!pirq_entries[pin-16]) {
1177 apic_printk(APIC_VERBOSE, KERN_DEBUG
1178 "disabling PIRQ%d\n", pin-16);
1179 } else {
1180 irq = pirq_entries[pin-16];
1181 apic_printk(APIC_VERBOSE, KERN_DEBUG
1182 "using PIRQ%d -> IRQ %d\n",
1183 pin-16, irq);
1187 return irq;
1190 static inline int IO_APIC_irq_trigger(int irq)
1192 int apic, idx, pin;
1194 for (apic = 0; apic < nr_ioapics; apic++) {
1195 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1196 idx = find_irq_entry(apic,pin,mp_INT);
1197 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1198 return irq_trigger(idx);
1201 /*
1202 * nonexistent IRQs are edge default
1203 */
1204 return 0;
1207 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1208 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1210 int assign_irq_vector(int irq)
1212 unsigned long flags;
1213 int vector;
1214 struct physdev_irq irq_op;
1216 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1218 spin_lock_irqsave(&vector_lock, flags);
1220 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1221 spin_unlock_irqrestore(&vector_lock, flags);
1222 return IO_APIC_VECTOR(irq);
1225 irq_op.irq = irq;
1226 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
1227 spin_unlock_irqrestore(&vector_lock, flags);
1228 return -ENOSPC;
1231 vector = irq_op.vector;
1232 vector_irq[vector] = irq;
1233 if (irq != AUTO_ASSIGN)
1234 IO_APIC_VECTOR(irq) = vector;
1236 spin_unlock_irqrestore(&vector_lock, flags);
1238 return vector;
1241 #ifndef CONFIG_XEN
1242 static struct hw_interrupt_type ioapic_level_type;
1243 static struct hw_interrupt_type ioapic_edge_type;
1245 #define IOAPIC_AUTO -1
1246 #define IOAPIC_EDGE 0
1247 #define IOAPIC_LEVEL 1
1249 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1251 unsigned idx;
1253 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1255 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1256 trigger == IOAPIC_LEVEL)
1257 irq_desc[idx].chip = &ioapic_level_type;
1258 else
1259 irq_desc[idx].chip = &ioapic_edge_type;
1260 set_intr_gate(vector, interrupt[idx]);
1262 #else
1263 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1264 #endif
1266 static void __init setup_IO_APIC_irqs(void)
1268 struct IO_APIC_route_entry entry;
1269 int apic, pin, idx, irq, first_notcon = 1, vector;
1270 unsigned long flags;
1272 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1274 for (apic = 0; apic < nr_ioapics; apic++) {
1275 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1277 /*
1278 * add it to the IO-APIC irq-routing table:
1279 */
1280 memset(&entry,0,sizeof(entry));
1282 entry.delivery_mode = INT_DELIVERY_MODE;
1283 entry.dest_mode = INT_DEST_MODE;
1284 entry.mask = 0; /* enable IRQ */
1285 entry.dest.logical.logical_dest =
1286 cpu_mask_to_apicid(TARGET_CPUS);
1288 idx = find_irq_entry(apic,pin,mp_INT);
1289 if (idx == -1) {
1290 if (first_notcon) {
1291 apic_printk(APIC_VERBOSE, KERN_DEBUG
1292 " IO-APIC (apicid-pin) %d-%d",
1293 mp_ioapics[apic].mpc_apicid,
1294 pin);
1295 first_notcon = 0;
1296 } else
1297 apic_printk(APIC_VERBOSE, ", %d-%d",
1298 mp_ioapics[apic].mpc_apicid, pin);
1299 continue;
1302 entry.trigger = irq_trigger(idx);
1303 entry.polarity = irq_polarity(idx);
1305 if (irq_trigger(idx)) {
1306 entry.trigger = 1;
1307 entry.mask = 1;
1310 irq = pin_2_irq(idx, apic, pin);
1311 /*
1312 * skip adding the timer int on secondary nodes, which causes
1313 * a small but painful rift in the time-space continuum
1314 */
1315 if (multi_timer_check(apic, irq))
1316 continue;
1317 else
1318 add_pin_to_irq(irq, apic, pin);
1320 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1321 continue;
1323 if (IO_APIC_IRQ(irq)) {
1324 vector = assign_irq_vector(irq);
1325 entry.vector = vector;
1326 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1328 if (!apic && (irq < 16))
1329 disable_8259A_irq(irq);
1331 spin_lock_irqsave(&ioapic_lock, flags);
1332 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1333 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1334 set_native_irq_info(irq, TARGET_CPUS);
1335 spin_unlock_irqrestore(&ioapic_lock, flags);
1339 if (!first_notcon)
1340 apic_printk(APIC_VERBOSE, " not connected.\n");
1343 /*
1344 * Set up the 8259A-master output pin:
1345 */
1346 #ifndef CONFIG_XEN
1347 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1349 struct IO_APIC_route_entry entry;
1350 unsigned long flags;
1352 memset(&entry,0,sizeof(entry));
1354 disable_8259A_irq(0);
1356 /* mask LVT0 */
1357 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1359 /*
1360 * We use logical delivery to get the timer IRQ
1361 * to the first CPU.
1362 */
1363 entry.dest_mode = INT_DEST_MODE;
1364 entry.mask = 0; /* unmask IRQ now */
1365 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1366 entry.delivery_mode = INT_DELIVERY_MODE;
1367 entry.polarity = 0;
1368 entry.trigger = 0;
1369 entry.vector = vector;
1371 /*
1372 * The timer IRQ doesn't have to know that behind the
1373 * scene we have a 8259A-master in AEOI mode ...
1374 */
1375 irq_desc[0].chip = &ioapic_edge_type;
1377 /*
1378 * Add it to the IO-APIC irq-routing table:
1379 */
1380 spin_lock_irqsave(&ioapic_lock, flags);
1381 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1382 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1383 spin_unlock_irqrestore(&ioapic_lock, flags);
1385 enable_8259A_irq(0);
1388 static inline void UNEXPECTED_IO_APIC(void)
1392 void __init print_IO_APIC(void)
1394 int apic, i;
1395 union IO_APIC_reg_00 reg_00;
1396 union IO_APIC_reg_01 reg_01;
1397 union IO_APIC_reg_02 reg_02;
1398 union IO_APIC_reg_03 reg_03;
1399 unsigned long flags;
1401 if (apic_verbosity == APIC_QUIET)
1402 return;
1404 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1405 for (i = 0; i < nr_ioapics; i++)
1406 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1407 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1409 /*
1410 * We are a bit conservative about what we expect. We have to
1411 * know about every hardware change ASAP.
1412 */
1413 printk(KERN_INFO "testing the IO APIC.......................\n");
1415 for (apic = 0; apic < nr_ioapics; apic++) {
1417 spin_lock_irqsave(&ioapic_lock, flags);
1418 reg_00.raw = io_apic_read(apic, 0);
1419 reg_01.raw = io_apic_read(apic, 1);
1420 if (reg_01.bits.version >= 0x10)
1421 reg_02.raw = io_apic_read(apic, 2);
1422 if (reg_01.bits.version >= 0x20)
1423 reg_03.raw = io_apic_read(apic, 3);
1424 spin_unlock_irqrestore(&ioapic_lock, flags);
1426 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1427 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1428 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1429 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1430 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1431 if (reg_00.bits.ID >= get_physical_broadcast())
1432 UNEXPECTED_IO_APIC();
1433 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1434 UNEXPECTED_IO_APIC();
1436 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1437 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1438 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1439 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1440 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1441 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1442 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1443 (reg_01.bits.entries != 0x2E) &&
1444 (reg_01.bits.entries != 0x3F)
1446 UNEXPECTED_IO_APIC();
1448 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1449 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1450 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1451 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1452 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1453 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1454 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1456 UNEXPECTED_IO_APIC();
1457 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1458 UNEXPECTED_IO_APIC();
1460 /*
1461 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1462 * but the value of reg_02 is read as the previous read register
1463 * value, so ignore it if reg_02 == reg_01.
1464 */
1465 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1466 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1467 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1468 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1469 UNEXPECTED_IO_APIC();
1472 /*
1473 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1474 * or reg_03, but the value of reg_0[23] is read as the previous read
1475 * register value, so ignore it if reg_03 == reg_0[12].
1476 */
1477 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1478 reg_03.raw != reg_01.raw) {
1479 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1480 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1481 if (reg_03.bits.__reserved_1)
1482 UNEXPECTED_IO_APIC();
1485 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1487 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1488 " Stat Dest Deli Vect: \n");
1490 for (i = 0; i <= reg_01.bits.entries; i++) {
1491 struct IO_APIC_route_entry entry;
1493 spin_lock_irqsave(&ioapic_lock, flags);
1494 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1495 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1496 spin_unlock_irqrestore(&ioapic_lock, flags);
1498 printk(KERN_DEBUG " %02x %03X %02X ",
1499 i,
1500 entry.dest.logical.logical_dest,
1501 entry.dest.physical.physical_dest
1502 );
1504 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1505 entry.mask,
1506 entry.trigger,
1507 entry.irr,
1508 entry.polarity,
1509 entry.delivery_status,
1510 entry.dest_mode,
1511 entry.delivery_mode,
1512 entry.vector
1513 );
1516 if (use_pci_vector())
1517 printk(KERN_INFO "Using vector-based indexing\n");
1518 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1519 for (i = 0; i < NR_IRQS; i++) {
1520 struct irq_pin_list *entry = irq_2_pin + i;
1521 if (entry->pin < 0)
1522 continue;
1523 if (use_pci_vector() && !platform_legacy_irq(i))
1524 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1525 else
1526 printk(KERN_DEBUG "IRQ%d ", i);
1527 for (;;) {
1528 printk("-> %d:%d", entry->apic, entry->pin);
1529 if (!entry->next)
1530 break;
1531 entry = irq_2_pin + entry->next;
1533 printk("\n");
1536 printk(KERN_INFO ".................................... done.\n");
1538 return;
1541 static void print_APIC_bitfield (int base)
1543 unsigned int v;
1544 int i, j;
1546 if (apic_verbosity == APIC_QUIET)
1547 return;
1549 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1550 for (i = 0; i < 8; i++) {
1551 v = apic_read(base + i*0x10);
1552 for (j = 0; j < 32; j++) {
1553 if (v & (1<<j))
1554 printk("1");
1555 else
1556 printk("0");
1558 printk("\n");
1562 void /*__init*/ print_local_APIC(void * dummy)
1564 unsigned int v, ver, maxlvt;
1566 if (apic_verbosity == APIC_QUIET)
1567 return;
1569 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1570 smp_processor_id(), hard_smp_processor_id());
1571 v = apic_read(APIC_ID);
1572 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1573 v = apic_read(APIC_LVR);
1574 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1575 ver = GET_APIC_VERSION(v);
1576 maxlvt = get_maxlvt();
1578 v = apic_read(APIC_TASKPRI);
1579 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1581 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1582 v = apic_read(APIC_ARBPRI);
1583 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1584 v & APIC_ARBPRI_MASK);
1585 v = apic_read(APIC_PROCPRI);
1586 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1589 v = apic_read(APIC_EOI);
1590 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1591 v = apic_read(APIC_RRR);
1592 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1593 v = apic_read(APIC_LDR);
1594 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1595 v = apic_read(APIC_DFR);
1596 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1597 v = apic_read(APIC_SPIV);
1598 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1600 printk(KERN_DEBUG "... APIC ISR field:\n");
1601 print_APIC_bitfield(APIC_ISR);
1602 printk(KERN_DEBUG "... APIC TMR field:\n");
1603 print_APIC_bitfield(APIC_TMR);
1604 printk(KERN_DEBUG "... APIC IRR field:\n");
1605 print_APIC_bitfield(APIC_IRR);
1607 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1608 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1609 apic_write(APIC_ESR, 0);
1610 v = apic_read(APIC_ESR);
1611 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1614 v = apic_read(APIC_ICR);
1615 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1616 v = apic_read(APIC_ICR2);
1617 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1619 v = apic_read(APIC_LVTT);
1620 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1622 if (maxlvt > 3) { /* PC is LVT#4. */
1623 v = apic_read(APIC_LVTPC);
1624 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1626 v = apic_read(APIC_LVT0);
1627 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1628 v = apic_read(APIC_LVT1);
1629 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1631 if (maxlvt > 2) { /* ERR is LVT#3. */
1632 v = apic_read(APIC_LVTERR);
1633 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1636 v = apic_read(APIC_TMICT);
1637 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1638 v = apic_read(APIC_TMCCT);
1639 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1640 v = apic_read(APIC_TDCR);
1641 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1642 printk("\n");
1645 void print_all_local_APICs (void)
1647 on_each_cpu(print_local_APIC, NULL, 1, 1);
1650 void /*__init*/ print_PIC(void)
1652 unsigned int v;
1653 unsigned long flags;
1655 if (apic_verbosity == APIC_QUIET)
1656 return;
1658 printk(KERN_DEBUG "\nprinting PIC contents\n");
1660 spin_lock_irqsave(&i8259A_lock, flags);
1662 v = inb(0xa1) << 8 | inb(0x21);
1663 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1665 v = inb(0xa0) << 8 | inb(0x20);
1666 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1668 outb(0x0b,0xa0);
1669 outb(0x0b,0x20);
1670 v = inb(0xa0) << 8 | inb(0x20);
1671 outb(0x0a,0xa0);
1672 outb(0x0a,0x20);
1674 spin_unlock_irqrestore(&i8259A_lock, flags);
1676 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1678 v = inb(0x4d1) << 8 | inb(0x4d0);
1679 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1681 #endif /* !CONFIG_XEN */
1683 static void __init enable_IO_APIC(void)
1685 union IO_APIC_reg_01 reg_01;
1686 int i8259_apic, i8259_pin;
1687 int i, apic;
1688 unsigned long flags;
1690 for (i = 0; i < PIN_MAP_SIZE; i++) {
1691 irq_2_pin[i].pin = -1;
1692 irq_2_pin[i].next = 0;
1694 if (!pirqs_enabled)
1695 for (i = 0; i < MAX_PIRQS; i++)
1696 pirq_entries[i] = -1;
1698 /*
1699 * The number of IO-APIC IRQ registers (== #pins):
1700 */
1701 for (apic = 0; apic < nr_ioapics; apic++) {
1702 spin_lock_irqsave(&ioapic_lock, flags);
1703 reg_01.raw = io_apic_read(apic, 1);
1704 spin_unlock_irqrestore(&ioapic_lock, flags);
1705 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1707 for(apic = 0; apic < nr_ioapics; apic++) {
1708 int pin;
1709 /* See if any of the pins is in ExtINT mode */
1710 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1711 struct IO_APIC_route_entry entry;
1712 spin_lock_irqsave(&ioapic_lock, flags);
1713 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1714 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1715 spin_unlock_irqrestore(&ioapic_lock, flags);
1718 /* If the interrupt line is enabled and in ExtInt mode
1719 * I have found the pin where the i8259 is connected.
1720 */
1721 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1722 ioapic_i8259.apic = apic;
1723 ioapic_i8259.pin = pin;
1724 goto found_i8259;
1728 found_i8259:
1729 /* Look to see what if the MP table has reported the ExtINT */
1730 /* If we could not find the appropriate pin by looking at the ioapic
1731 * the i8259 probably is not connected the ioapic but give the
1732 * mptable a chance anyway.
1733 */
1734 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1735 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1736 /* Trust the MP table if nothing is setup in the hardware */
1737 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1738 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1739 ioapic_i8259.pin = i8259_pin;
1740 ioapic_i8259.apic = i8259_apic;
1742 /* Complain if the MP table and the hardware disagree */
1743 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1744 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1746 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1749 /*
1750 * Do not trust the IO-APIC being empty at bootup
1751 */
1752 clear_IO_APIC();
1755 /*
1756 * Not an __init, needed by the reboot code
1757 */
1758 void disable_IO_APIC(void)
1760 /*
1761 * Clear the IO-APIC before rebooting:
1762 */
1763 clear_IO_APIC();
1765 #ifndef CONFIG_XEN
1766 /*
1767 * If the i8259 is routed through an IOAPIC
1768 * Put that IOAPIC in virtual wire mode
1769 * so legacy interrupts can be delivered.
1770 */
1771 if (ioapic_i8259.pin != -1) {
1772 struct IO_APIC_route_entry entry;
1773 unsigned long flags;
1775 memset(&entry, 0, sizeof(entry));
1776 entry.mask = 0; /* Enabled */
1777 entry.trigger = 0; /* Edge */
1778 entry.irr = 0;
1779 entry.polarity = 0; /* High */
1780 entry.delivery_status = 0;
1781 entry.dest_mode = 0; /* Physical */
1782 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1783 entry.vector = 0;
1784 entry.dest.physical.physical_dest =
1785 GET_APIC_ID(apic_read(APIC_ID));
1787 /*
1788 * Add it to the IO-APIC irq-routing table:
1789 */
1790 spin_lock_irqsave(&ioapic_lock, flags);
1791 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1792 *(((int *)&entry)+1));
1793 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1794 *(((int *)&entry)+0));
1795 spin_unlock_irqrestore(&ioapic_lock, flags);
1797 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1798 #endif
1801 /*
1802 * function to set the IO-APIC physical IDs based on the
1803 * values stored in the MPC table.
1805 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1806 */
1808 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1809 static void __init setup_ioapic_ids_from_mpc(void)
1811 union IO_APIC_reg_00 reg_00;
1812 physid_mask_t phys_id_present_map;
1813 int apic;
1814 int i;
1815 unsigned char old_id;
1816 unsigned long flags;
1818 /*
1819 * Don't check I/O APIC IDs for xAPIC systems. They have
1820 * no meaning without the serial APIC bus.
1821 */
1822 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1823 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1824 return;
1825 /*
1826 * This is broken; anything with a real cpu count has to
1827 * circumvent this idiocy regardless.
1828 */
1829 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1831 /*
1832 * Set the IOAPIC ID to the value stored in the MPC table.
1833 */
1834 for (apic = 0; apic < nr_ioapics; apic++) {
1836 /* Read the register 0 value */
1837 spin_lock_irqsave(&ioapic_lock, flags);
1838 reg_00.raw = io_apic_read(apic, 0);
1839 spin_unlock_irqrestore(&ioapic_lock, flags);
1841 old_id = mp_ioapics[apic].mpc_apicid;
1843 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1844 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1845 apic, mp_ioapics[apic].mpc_apicid);
1846 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1847 reg_00.bits.ID);
1848 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1851 /*
1852 * Sanity check, is the ID really free? Every APIC in a
1853 * system must have a unique ID or we get lots of nice
1854 * 'stuck on smp_invalidate_needed IPI wait' messages.
1855 */
1856 if (check_apicid_used(phys_id_present_map,
1857 mp_ioapics[apic].mpc_apicid)) {
1858 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1859 apic, mp_ioapics[apic].mpc_apicid);
1860 for (i = 0; i < get_physical_broadcast(); i++)
1861 if (!physid_isset(i, phys_id_present_map))
1862 break;
1863 if (i >= get_physical_broadcast())
1864 panic("Max APIC ID exceeded!\n");
1865 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1866 i);
1867 physid_set(i, phys_id_present_map);
1868 mp_ioapics[apic].mpc_apicid = i;
1869 } else {
1870 physid_mask_t tmp;
1871 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1872 apic_printk(APIC_VERBOSE, "Setting %d in the "
1873 "phys_id_present_map\n",
1874 mp_ioapics[apic].mpc_apicid);
1875 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1879 /*
1880 * We need to adjust the IRQ routing table
1881 * if the ID changed.
1882 */
1883 if (old_id != mp_ioapics[apic].mpc_apicid)
1884 for (i = 0; i < mp_irq_entries; i++)
1885 if (mp_irqs[i].mpc_dstapic == old_id)
1886 mp_irqs[i].mpc_dstapic
1887 = mp_ioapics[apic].mpc_apicid;
1889 /*
1890 * Read the right value from the MPC table and
1891 * write it into the ID register.
1892 */
1893 apic_printk(APIC_VERBOSE, KERN_INFO
1894 "...changing IO-APIC physical APIC ID to %d ...",
1895 mp_ioapics[apic].mpc_apicid);
1897 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1898 spin_lock_irqsave(&ioapic_lock, flags);
1899 io_apic_write(apic, 0, reg_00.raw);
1900 spin_unlock_irqrestore(&ioapic_lock, flags);
1902 /*
1903 * Sanity check
1904 */
1905 spin_lock_irqsave(&ioapic_lock, flags);
1906 reg_00.raw = io_apic_read(apic, 0);
1907 spin_unlock_irqrestore(&ioapic_lock, flags);
1908 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1909 printk("could not set ID!\n");
1910 else
1911 apic_printk(APIC_VERBOSE, " ok.\n");
1914 #else
1915 static void __init setup_ioapic_ids_from_mpc(void) { }
1916 #endif
1918 #ifndef CONFIG_XEN
1919 /*
1920 * There is a nasty bug in some older SMP boards, their mptable lies
1921 * about the timer IRQ. We do the following to work around the situation:
1923 * - timer IRQ defaults to IO-APIC IRQ
1924 * - if this function detects that timer IRQs are defunct, then we fall
1925 * back to ISA timer IRQs
1926 */
1927 static int __init timer_irq_works(void)
1929 unsigned long t1 = jiffies;
1931 local_irq_enable();
1932 /* Let ten ticks pass... */
1933 mdelay((10 * 1000) / HZ);
1935 /*
1936 * Expect a few ticks at least, to be sure some possible
1937 * glue logic does not lock up after one or two first
1938 * ticks in a non-ExtINT mode. Also the local APIC
1939 * might have cached one ExtINT interrupt. Finally, at
1940 * least one tick may be lost due to delays.
1941 */
1942 if (jiffies - t1 > 4)
1943 return 1;
1945 return 0;
1948 /*
1949 * In the SMP+IOAPIC case it might happen that there are an unspecified
1950 * number of pending IRQ events unhandled. These cases are very rare,
1951 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1952 * better to do it this way as thus we do not have to be aware of
1953 * 'pending' interrupts in the IRQ path, except at this point.
1954 */
1955 /*
1956 * Edge triggered needs to resend any interrupt
1957 * that was delayed but this is now handled in the device
1958 * independent code.
1959 */
1961 /*
1962 * Starting up a edge-triggered IO-APIC interrupt is
1963 * nasty - we need to make sure that we get the edge.
1964 * If it is already asserted for some reason, we need
1965 * return 1 to indicate that is was pending.
1967 * This is not complete - we should be able to fake
1968 * an edge even if it isn't on the 8259A...
1969 */
1970 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1972 int was_pending = 0;
1973 unsigned long flags;
1975 spin_lock_irqsave(&ioapic_lock, flags);
1976 if (irq < 16) {
1977 disable_8259A_irq(irq);
1978 if (i8259A_irq_pending(irq))
1979 was_pending = 1;
1981 __unmask_IO_APIC_irq(irq);
1982 spin_unlock_irqrestore(&ioapic_lock, flags);
1984 return was_pending;
1987 /*
1988 * Once we have recorded IRQ_PENDING already, we can mask the
1989 * interrupt for real. This prevents IRQ storms from unhandled
1990 * devices.
1991 */
1992 static void ack_edge_ioapic_irq(unsigned int irq)
1994 move_irq(irq);
1995 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1996 == (IRQ_PENDING | IRQ_DISABLED))
1997 mask_IO_APIC_irq(irq);
1998 ack_APIC_irq();
2001 /*
2002 * Level triggered interrupts can just be masked,
2003 * and shutting down and starting up the interrupt
2004 * is the same as enabling and disabling them -- except
2005 * with a startup need to return a "was pending" value.
2007 * Level triggered interrupts are special because we
2008 * do not touch any IO-APIC register while handling
2009 * them. We ack the APIC in the end-IRQ handler, not
2010 * in the start-IRQ-handler. Protection against reentrance
2011 * from the same interrupt is still provided, both by the
2012 * generic IRQ layer and by the fact that an unacked local
2013 * APIC does not accept IRQs.
2014 */
2015 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2017 unmask_IO_APIC_irq(irq);
2019 return 0; /* don't check for pending */
2022 static void end_level_ioapic_irq (unsigned int irq)
2024 unsigned long v;
2025 int i;
2027 move_irq(irq);
2028 /*
2029 * It appears there is an erratum which affects at least version 0x11
2030 * of I/O APIC (that's the 82093AA and cores integrated into various
2031 * chipsets). Under certain conditions a level-triggered interrupt is
2032 * erroneously delivered as edge-triggered one but the respective IRR
2033 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2034 * message but it will never arrive and further interrupts are blocked
2035 * from the source. The exact reason is so far unknown, but the
2036 * phenomenon was observed when two consecutive interrupt requests
2037 * from a given source get delivered to the same CPU and the source is
2038 * temporarily disabled in between.
2040 * A workaround is to simulate an EOI message manually. We achieve it
2041 * by setting the trigger mode to edge and then to level when the edge
2042 * trigger mode gets detected in the TMR of a local APIC for a
2043 * level-triggered interrupt. We mask the source for the time of the
2044 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2045 * The idea is from Manfred Spraul. --macro
2046 */
2047 i = IO_APIC_VECTOR(irq);
2049 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2051 ack_APIC_irq();
2053 if (!(v & (1 << (i & 0x1f)))) {
2054 atomic_inc(&irq_mis_count);
2055 spin_lock(&ioapic_lock);
2056 __mask_and_edge_IO_APIC_irq(irq);
2057 __unmask_and_level_IO_APIC_irq(irq);
2058 spin_unlock(&ioapic_lock);
2062 #ifdef CONFIG_PCI_MSI
2063 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2065 int irq = vector_to_irq(vector);
2067 return startup_edge_ioapic_irq(irq);
2070 static void ack_edge_ioapic_vector(unsigned int vector)
2072 int irq = vector_to_irq(vector);
2074 move_native_irq(vector);
2075 ack_edge_ioapic_irq(irq);
2078 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2080 int irq = vector_to_irq(vector);
2082 return startup_level_ioapic_irq (irq);
2085 static void end_level_ioapic_vector (unsigned int vector)
2087 int irq = vector_to_irq(vector);
2089 move_native_irq(vector);
2090 end_level_ioapic_irq(irq);
2093 static void mask_IO_APIC_vector (unsigned int vector)
2095 int irq = vector_to_irq(vector);
2097 mask_IO_APIC_irq(irq);
2100 static void unmask_IO_APIC_vector (unsigned int vector)
2102 int irq = vector_to_irq(vector);
2104 unmask_IO_APIC_irq(irq);
2107 #ifdef CONFIG_SMP
2108 static void set_ioapic_affinity_vector (unsigned int vector,
2109 cpumask_t cpu_mask)
2111 int irq = vector_to_irq(vector);
2113 set_native_irq_info(vector, cpu_mask);
2114 set_ioapic_affinity_irq(irq, cpu_mask);
2116 #endif
2117 #endif
2119 static int ioapic_retrigger(unsigned int irq)
2121 send_IPI_self(IO_APIC_VECTOR(irq));
2123 return 1;
2126 /*
2127 * Level and edge triggered IO-APIC interrupts need different handling,
2128 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2129 * handled with the level-triggered descriptor, but that one has slightly
2130 * more overhead. Level-triggered interrupts cannot be handled with the
2131 * edge-triggered handler, without risking IRQ storms and other ugly
2132 * races.
2133 */
2134 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2135 .typename = "IO-APIC-edge",
2136 .startup = startup_edge_ioapic,
2137 .shutdown = shutdown_edge_ioapic,
2138 .enable = enable_edge_ioapic,
2139 .disable = disable_edge_ioapic,
2140 .ack = ack_edge_ioapic,
2141 .end = end_edge_ioapic,
2142 #ifdef CONFIG_SMP
2143 .set_affinity = set_ioapic_affinity,
2144 #endif
2145 .retrigger = ioapic_retrigger,
2146 };
2148 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2149 .typename = "IO-APIC-level",
2150 .startup = startup_level_ioapic,
2151 .shutdown = shutdown_level_ioapic,
2152 .enable = enable_level_ioapic,
2153 .disable = disable_level_ioapic,
2154 .ack = mask_and_ack_level_ioapic,
2155 .end = end_level_ioapic,
2156 #ifdef CONFIG_SMP
2157 .set_affinity = set_ioapic_affinity,
2158 #endif
2159 .retrigger = ioapic_retrigger,
2160 };
2161 #endif /* !CONFIG_XEN */
2163 static inline void init_IO_APIC_traps(void)
2165 int irq;
2167 /*
2168 * NOTE! The local APIC isn't very good at handling
2169 * multiple interrupts at the same interrupt level.
2170 * As the interrupt level is determined by taking the
2171 * vector number and shifting that right by 4, we
2172 * want to spread these out a bit so that they don't
2173 * all fall in the same interrupt level.
2175 * Also, we've got to be careful not to trash gate
2176 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2177 */
2178 for (irq = 0; irq < NR_IRQS ; irq++) {
2179 int tmp = irq;
2180 if (use_pci_vector()) {
2181 if (!platform_legacy_irq(tmp))
2182 if ((tmp = vector_to_irq(tmp)) == -1)
2183 continue;
2185 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2186 /*
2187 * Hmm.. We don't have an entry for this,
2188 * so default to an old-fashioned 8259
2189 * interrupt if we can..
2190 */
2191 if (irq < 16)
2192 make_8259A_irq(irq);
2193 #ifndef CONFIG_XEN
2194 else
2195 /* Strange. Oh, well.. */
2196 irq_desc[irq].chip = &no_irq_type;
2197 #endif
2202 #ifndef CONFIG_XEN
2203 static void enable_lapic_irq (unsigned int irq)
2205 unsigned long v;
2207 v = apic_read(APIC_LVT0);
2208 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2211 static void disable_lapic_irq (unsigned int irq)
2213 unsigned long v;
2215 v = apic_read(APIC_LVT0);
2216 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2219 static void ack_lapic_irq (unsigned int irq)
2221 ack_APIC_irq();
2224 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2226 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2227 .typename = "local-APIC-edge",
2228 .startup = NULL, /* startup_irq() not used for IRQ0 */
2229 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2230 .enable = enable_lapic_irq,
2231 .disable = disable_lapic_irq,
2232 .ack = ack_lapic_irq,
2233 .end = end_lapic_irq
2234 };
2236 static void setup_nmi (void)
2238 /*
2239 * Dirty trick to enable the NMI watchdog ...
2240 * We put the 8259A master into AEOI mode and
2241 * unmask on all local APICs LVT0 as NMI.
2243 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2244 * is from Maciej W. Rozycki - so we do not have to EOI from
2245 * the NMI handler or the timer interrupt.
2246 */
2247 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2249 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2251 apic_printk(APIC_VERBOSE, " done.\n");
2254 /*
2255 * This looks a bit hackish but it's about the only one way of sending
2256 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2257 * not support the ExtINT mode, unfortunately. We need to send these
2258 * cycles as some i82489DX-based boards have glue logic that keeps the
2259 * 8259A interrupt line asserted until INTA. --macro
2260 */
2261 static inline void unlock_ExtINT_logic(void)
2263 int apic, pin, i;
2264 struct IO_APIC_route_entry entry0, entry1;
2265 unsigned char save_control, save_freq_select;
2266 unsigned long flags;
2268 pin = find_isa_irq_pin(8, mp_INT);
2269 apic = find_isa_irq_apic(8, mp_INT);
2270 if (pin == -1)
2271 return;
2273 spin_lock_irqsave(&ioapic_lock, flags);
2274 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2275 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2276 spin_unlock_irqrestore(&ioapic_lock, flags);
2277 clear_IO_APIC_pin(apic, pin);
2279 memset(&entry1, 0, sizeof(entry1));
2281 entry1.dest_mode = 0; /* physical delivery */
2282 entry1.mask = 0; /* unmask IRQ now */
2283 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2284 entry1.delivery_mode = dest_ExtINT;
2285 entry1.polarity = entry0.polarity;
2286 entry1.trigger = 0;
2287 entry1.vector = 0;
2289 spin_lock_irqsave(&ioapic_lock, flags);
2290 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2291 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2292 spin_unlock_irqrestore(&ioapic_lock, flags);
2294 save_control = CMOS_READ(RTC_CONTROL);
2295 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2296 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2297 RTC_FREQ_SELECT);
2298 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2300 i = 100;
2301 while (i-- > 0) {
2302 mdelay(10);
2303 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2304 i -= 10;
2307 CMOS_WRITE(save_control, RTC_CONTROL);
2308 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2309 clear_IO_APIC_pin(apic, pin);
2311 spin_lock_irqsave(&ioapic_lock, flags);
2312 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2313 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2314 spin_unlock_irqrestore(&ioapic_lock, flags);
2317 int timer_uses_ioapic_pin_0;
2319 /*
2320 * This code may look a bit paranoid, but it's supposed to cooperate with
2321 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2322 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2323 * fanatically on his truly buggy board.
2324 */
2325 static inline void check_timer(void)
2327 int apic1, pin1, apic2, pin2;
2328 int vector;
2330 /*
2331 * get/set the timer IRQ vector:
2332 */
2333 disable_8259A_irq(0);
2334 vector = assign_irq_vector(0);
2335 set_intr_gate(vector, interrupt[0]);
2337 /*
2338 * Subtle, code in do_timer_interrupt() expects an AEOI
2339 * mode for the 8259A whenever interrupts are routed
2340 * through I/O APICs. Also IRQ0 has to be enabled in
2341 * the 8259A which implies the virtual wire has to be
2342 * disabled in the local APIC.
2343 */
2344 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2345 init_8259A(1);
2346 timer_ack = 1;
2347 if (timer_over_8254 > 0)
2348 enable_8259A_irq(0);
2350 pin1 = find_isa_irq_pin(0, mp_INT);
2351 apic1 = find_isa_irq_apic(0, mp_INT);
2352 pin2 = ioapic_i8259.pin;
2353 apic2 = ioapic_i8259.apic;
2355 if (pin1 == 0)
2356 timer_uses_ioapic_pin_0 = 1;
2358 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2359 vector, apic1, pin1, apic2, pin2);
2361 if (pin1 != -1) {
2362 /*
2363 * Ok, does IRQ0 through the IOAPIC work?
2364 */
2365 unmask_IO_APIC_irq(0);
2366 if (timer_irq_works()) {
2367 if (nmi_watchdog == NMI_IO_APIC) {
2368 disable_8259A_irq(0);
2369 setup_nmi();
2370 enable_8259A_irq(0);
2372 if (disable_timer_pin_1 > 0)
2373 clear_IO_APIC_pin(0, pin1);
2374 return;
2376 clear_IO_APIC_pin(apic1, pin1);
2377 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2378 "IO-APIC\n");
2381 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2382 if (pin2 != -1) {
2383 printk("\n..... (found pin %d) ...", pin2);
2384 /*
2385 * legacy devices should be connected to IO APIC #0
2386 */
2387 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2388 if (timer_irq_works()) {
2389 printk("works.\n");
2390 if (pin1 != -1)
2391 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2392 else
2393 add_pin_to_irq(0, apic2, pin2);
2394 if (nmi_watchdog == NMI_IO_APIC) {
2395 setup_nmi();
2397 return;
2399 /*
2400 * Cleanup, just in case ...
2401 */
2402 clear_IO_APIC_pin(apic2, pin2);
2404 printk(" failed.\n");
2406 if (nmi_watchdog == NMI_IO_APIC) {
2407 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2408 nmi_watchdog = 0;
2411 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2413 disable_8259A_irq(0);
2414 irq_desc[0].chip = &lapic_irq_type;
2415 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2416 enable_8259A_irq(0);
2418 if (timer_irq_works()) {
2419 printk(" works.\n");
2420 return;
2422 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2423 printk(" failed.\n");
2425 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2427 timer_ack = 0;
2428 init_8259A(0);
2429 make_8259A_irq(0);
2430 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2432 unlock_ExtINT_logic();
2434 if (timer_irq_works()) {
2435 printk(" works.\n");
2436 return;
2438 printk(" failed :(.\n");
2439 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2440 "report. Then try booting with the 'noapic' option");
2442 #else
2443 int timer_uses_ioapic_pin_0 = 0;
2444 #define check_timer() ((void)0)
2445 #endif
2447 /*
2449 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2450 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2451 * Linux doesn't really care, as it's not actually used
2452 * for any interrupt handling anyway.
2453 */
2454 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2456 void __init setup_IO_APIC(void)
2458 enable_IO_APIC();
2460 if (acpi_ioapic)
2461 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2462 else
2463 io_apic_irqs = ~PIC_IRQS;
2465 printk("ENABLING IO-APIC IRQs\n");
2467 /*
2468 * Set up IO-APIC IRQ routing.
2469 */
2470 if (!acpi_ioapic)
2471 setup_ioapic_ids_from_mpc();
2472 #ifndef CONFIG_XEN
2473 sync_Arb_IDs();
2474 #endif
2475 setup_IO_APIC_irqs();
2476 init_IO_APIC_traps();
2477 check_timer();
2478 if (!acpi_ioapic)
2479 print_IO_APIC();
2482 static int __init setup_disable_8254_timer(char *s)
2484 timer_over_8254 = -1;
2485 return 1;
2487 static int __init setup_enable_8254_timer(char *s)
2489 timer_over_8254 = 2;
2490 return 1;
2493 __setup("disable_8254_timer", setup_disable_8254_timer);
2494 __setup("enable_8254_timer", setup_enable_8254_timer);
2496 /*
2497 * Called after all the initialization is done. If we didnt find any
2498 * APIC bugs then we can allow the modify fast path
2499 */
2501 static int __init io_apic_bug_finalize(void)
2503 if(sis_apic_bug == -1)
2504 sis_apic_bug = 0;
2505 if (is_initial_xendomain()) {
2506 struct xen_platform_op op = { .cmd = XENPF_platform_quirk };
2507 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2508 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2509 VOID(HYPERVISOR_platform_op(&op));
2511 return 0;
2514 late_initcall(io_apic_bug_finalize);
2516 struct sysfs_ioapic_data {
2517 struct sys_device dev;
2518 struct IO_APIC_route_entry entry[0];
2519 };
2520 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2522 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2524 struct IO_APIC_route_entry *entry;
2525 struct sysfs_ioapic_data *data;
2526 unsigned long flags;
2527 int i;
2529 data = container_of(dev, struct sysfs_ioapic_data, dev);
2530 entry = data->entry;
2531 spin_lock_irqsave(&ioapic_lock, flags);
2532 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2533 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2534 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2536 spin_unlock_irqrestore(&ioapic_lock, flags);
2538 return 0;
2541 static int ioapic_resume(struct sys_device *dev)
2543 struct IO_APIC_route_entry *entry;
2544 struct sysfs_ioapic_data *data;
2545 unsigned long flags;
2546 union IO_APIC_reg_00 reg_00;
2547 int i;
2549 data = container_of(dev, struct sysfs_ioapic_data, dev);
2550 entry = data->entry;
2552 spin_lock_irqsave(&ioapic_lock, flags);
2553 reg_00.raw = io_apic_read(dev->id, 0);
2554 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2555 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2556 io_apic_write(dev->id, 0, reg_00.raw);
2558 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2559 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2560 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2562 spin_unlock_irqrestore(&ioapic_lock, flags);
2564 return 0;
2567 static struct sysdev_class ioapic_sysdev_class = {
2568 set_kset_name("ioapic"),
2569 .suspend = ioapic_suspend,
2570 .resume = ioapic_resume,
2571 };
2573 static int __init ioapic_init_sysfs(void)
2575 struct sys_device * dev;
2576 int i, size, error = 0;
2578 error = sysdev_class_register(&ioapic_sysdev_class);
2579 if (error)
2580 return error;
2582 for (i = 0; i < nr_ioapics; i++ ) {
2583 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2584 * sizeof(struct IO_APIC_route_entry);
2585 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2586 if (!mp_ioapic_data[i]) {
2587 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2588 continue;
2590 memset(mp_ioapic_data[i], 0, size);
2591 dev = &mp_ioapic_data[i]->dev;
2592 dev->id = i;
2593 dev->cls = &ioapic_sysdev_class;
2594 error = sysdev_register(dev);
2595 if (error) {
2596 kfree(mp_ioapic_data[i]);
2597 mp_ioapic_data[i] = NULL;
2598 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2599 continue;
2603 return 0;
2606 device_initcall(ioapic_init_sysfs);
2608 /* --------------------------------------------------------------------------
2609 ACPI-based IOAPIC Configuration
2610 -------------------------------------------------------------------------- */
2612 #ifdef CONFIG_ACPI
2614 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2616 #ifndef CONFIG_XEN
2617 union IO_APIC_reg_00 reg_00;
2618 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2619 physid_mask_t tmp;
2620 unsigned long flags;
2621 int i = 0;
2623 /*
2624 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2625 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2626 * supports up to 16 on one shared APIC bus.
2628 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2629 * advantage of new APIC bus architecture.
2630 */
2632 if (physids_empty(apic_id_map))
2633 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2635 spin_lock_irqsave(&ioapic_lock, flags);
2636 reg_00.raw = io_apic_read(ioapic, 0);
2637 spin_unlock_irqrestore(&ioapic_lock, flags);
2639 if (apic_id >= get_physical_broadcast()) {
2640 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2641 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2642 apic_id = reg_00.bits.ID;
2645 /*
2646 * Every APIC in a system must have a unique ID or we get lots of nice
2647 * 'stuck on smp_invalidate_needed IPI wait' messages.
2648 */
2649 if (check_apicid_used(apic_id_map, apic_id)) {
2651 for (i = 0; i < get_physical_broadcast(); i++) {
2652 if (!check_apicid_used(apic_id_map, i))
2653 break;
2656 if (i == get_physical_broadcast())
2657 panic("Max apic_id exceeded!\n");
2659 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2660 "trying %d\n", ioapic, apic_id, i);
2662 apic_id = i;
2665 tmp = apicid_to_cpu_present(apic_id);
2666 physids_or(apic_id_map, apic_id_map, tmp);
2668 if (reg_00.bits.ID != apic_id) {
2669 reg_00.bits.ID = apic_id;
2671 spin_lock_irqsave(&ioapic_lock, flags);
2672 io_apic_write(ioapic, 0, reg_00.raw);
2673 reg_00.raw = io_apic_read(ioapic, 0);
2674 spin_unlock_irqrestore(&ioapic_lock, flags);
2676 /* Sanity check */
2677 if (reg_00.bits.ID != apic_id) {
2678 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2679 return -1;
2683 apic_printk(APIC_VERBOSE, KERN_INFO
2684 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2685 #endif /* !CONFIG_XEN */
2687 return apic_id;
2691 int __init io_apic_get_version (int ioapic)
2693 union IO_APIC_reg_01 reg_01;
2694 unsigned long flags;
2696 spin_lock_irqsave(&ioapic_lock, flags);
2697 reg_01.raw = io_apic_read(ioapic, 1);
2698 spin_unlock_irqrestore(&ioapic_lock, flags);
2700 return reg_01.bits.version;
2704 int __init io_apic_get_redir_entries (int ioapic)
2706 union IO_APIC_reg_01 reg_01;
2707 unsigned long flags;
2709 spin_lock_irqsave(&ioapic_lock, flags);
2710 reg_01.raw = io_apic_read(ioapic, 1);
2711 spin_unlock_irqrestore(&ioapic_lock, flags);
2713 return reg_01.bits.entries;
2717 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2719 struct IO_APIC_route_entry entry;
2720 unsigned long flags;
2722 if (!IO_APIC_IRQ(irq)) {
2723 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2724 ioapic);
2725 return -EINVAL;
2728 /*
2729 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2730 * Note that we mask (disable) IRQs now -- these get enabled when the
2731 * corresponding device driver registers for this IRQ.
2732 */
2734 memset(&entry,0,sizeof(entry));
2736 entry.delivery_mode = INT_DELIVERY_MODE;
2737 entry.dest_mode = INT_DEST_MODE;
2738 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2739 entry.trigger = edge_level;
2740 entry.polarity = active_high_low;
2741 entry.mask = 1;
2743 /*
2744 * IRQs < 16 are already in the irq_2_pin[] map
2745 */
2746 if (irq >= 16)
2747 add_pin_to_irq(irq, ioapic, pin);
2749 entry.vector = assign_irq_vector(irq);
2751 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2752 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2753 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2754 edge_level, active_high_low);
2756 ioapic_register_intr(irq, entry.vector, edge_level);
2758 if (!ioapic && (irq < 16))
2759 disable_8259A_irq(irq);
2761 spin_lock_irqsave(&ioapic_lock, flags);
2762 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2763 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2764 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2765 spin_unlock_irqrestore(&ioapic_lock, flags);
2767 return 0;
2770 #endif /* CONFIG_ACPI */