ia64/linux-2.6.18-xen.hg

view arch/xtensa/kernel/pci.c @ 647:a5bb490065f6

Fix the build after public header sync.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Aug 13 14:01:49 2008 +0100 (2008-08-13)
parents 831230e53067
children
line source
1 /*
2 * arch/xtensa/pcibios.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Copyright (C) 2001-2005 Tensilica Inc.
12 *
13 * Based largely on work from Cort (ppc/kernel/pci.c)
14 * IO functions copied from sparc.
15 *
16 * Chris Zankel <chris@zankel.net>
17 *
18 */
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/sched.h>
26 #include <linux/errno.h>
27 #include <linux/bootmem.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/platform.h>
32 #undef DEBUG
34 #ifdef DEBUG
35 #define DBG(x...) printk(x)
36 #else
37 #define DBG(x...)
38 #endif
40 /* PCI Controller */
43 /*
44 * pcibios_alloc_controller
45 * pcibios_enable_device
46 * pcibios_fixups
47 * pcibios_align_resource
48 * pcibios_fixup_bus
49 * pcibios_setup
50 * pci_bus_add_device
51 * pci_mmap_page_range
52 */
54 struct pci_controller* pci_ctrl_head;
55 struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
57 static int pci_bus_count;
59 /*
60 * We need to avoid collisions with `mirrored' VGA ports
61 * and other strange ISA hardware, so we always want the
62 * addresses to be allocated in the 0x000-0x0ff region
63 * modulo 0x400.
64 *
65 * Why? Because some silly external IO cards only decode
66 * the low 10 bits of the IO address. The 0x00-0xff region
67 * is reserved for motherboard devices that decode all 16
68 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
69 * but we want to try to avoid allocating at 0x2900-0x2bff
70 * which might have be mirrored at 0x0100-0x03ff..
71 */
72 void
73 pcibios_align_resource(void *data, struct resource *res, resource_size_t size,
74 resource_size_t align)
75 {
76 struct pci_dev *dev = data;
78 if (res->flags & IORESOURCE_IO) {
79 resource_size_t start = res->start;
81 if (size > 0x100) {
82 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
83 " (%ld bytes)\n", pci_name(dev),
84 dev->resource - res, size);
85 }
87 if (start & 0x300) {
88 start = (start + 0x3ff) & ~0x3ff;
89 res->start = start;
90 }
91 }
92 }
94 int
95 pcibios_enable_resources(struct pci_dev *dev, int mask)
96 {
97 u16 cmd, old_cmd;
98 int idx;
99 struct resource *r;
101 pci_read_config_word(dev, PCI_COMMAND, &cmd);
102 old_cmd = cmd;
103 for(idx=0; idx<6; idx++) {
104 r = &dev->resource[idx];
105 if (!r->start && r->end) {
106 printk (KERN_ERR "PCI: Device %s not available because "
107 "of resource collisions\n", pci_name(dev));
108 return -EINVAL;
109 }
110 if (r->flags & IORESOURCE_IO)
111 cmd |= PCI_COMMAND_IO;
112 if (r->flags & IORESOURCE_MEM)
113 cmd |= PCI_COMMAND_MEMORY;
114 }
115 if (dev->resource[PCI_ROM_RESOURCE].start)
116 cmd |= PCI_COMMAND_MEMORY;
117 if (cmd != old_cmd) {
118 printk("PCI: Enabling device %s (%04x -> %04x)\n",
119 pci_name(dev), old_cmd, cmd);
120 pci_write_config_word(dev, PCI_COMMAND, cmd);
121 }
122 return 0;
123 }
125 struct pci_controller * __init pcibios_alloc_controller(void)
126 {
127 struct pci_controller *pci_ctrl;
129 pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
130 memset(pci_ctrl, 0, sizeof(struct pci_controller));
132 *pci_ctrl_tail = pci_ctrl;
133 pci_ctrl_tail = &pci_ctrl->next;
135 return pci_ctrl;
136 }
138 static int __init pcibios_init(void)
139 {
140 struct pci_controller *pci_ctrl;
141 struct pci_bus *bus;
142 int next_busno = 0, i;
144 printk("PCI: Probing PCI hardware\n");
146 /* Scan all of the recorded PCI controllers. */
147 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
148 pci_ctrl->last_busno = 0xff;
149 bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops,
150 pci_ctrl);
151 if (pci_ctrl->io_resource.flags) {
152 unsigned long offs;
154 offs = (unsigned long)pci_ctrl->io_space.base;
155 pci_ctrl->io_resource.start += offs;
156 pci_ctrl->io_resource.end += offs;
157 bus->resource[0] = &pci_ctrl->io_resource;
158 }
159 for (i = 0; i < 3; ++i)
160 if (pci_ctrl->mem_resources[i].flags)
161 bus->resource[i+1] =&pci_ctrl->mem_resources[i];
162 pci_ctrl->bus = bus;
163 pci_ctrl->last_busno = bus->subordinate;
164 if (next_busno <= pci_ctrl->last_busno)
165 next_busno = pci_ctrl->last_busno+1;
166 }
167 pci_bus_count = next_busno;
169 return platform_pcibios_fixup();
170 }
172 subsys_initcall(pcibios_init);
174 void __init pcibios_fixup_bus(struct pci_bus *bus)
175 {
176 struct pci_controller *pci_ctrl = bus->sysdata;
177 struct resource *res;
178 unsigned long io_offset;
179 int i;
181 io_offset = (unsigned long)pci_ctrl->io_space.base;
182 if (bus->parent == NULL) {
183 /* this is a host bridge - fill in its resources */
184 pci_ctrl->bus = bus;
186 bus->resource[0] = res = &pci_ctrl->io_resource;
187 if (!res->flags) {
188 if (io_offset)
189 printk (KERN_ERR "I/O resource not set for host"
190 " bridge %d\n", pci_ctrl->index);
191 res->start = 0;
192 res->end = IO_SPACE_LIMIT;
193 res->flags = IORESOURCE_IO;
194 }
195 res->start += io_offset;
196 res->end += io_offset;
198 for (i = 0; i < 3; i++) {
199 res = &pci_ctrl->mem_resources[i];
200 if (!res->flags) {
201 if (i > 0)
202 continue;
203 printk(KERN_ERR "Memory resource not set for "
204 "host bridge %d\n", pci_ctrl->index);
205 res->start = 0;
206 res->end = ~0U;
207 res->flags = IORESOURCE_MEM;
208 }
209 bus->resource[i+1] = res;
210 }
211 } else {
212 /* This is a subordinate bridge */
213 pci_read_bridge_bases(bus);
215 for (i = 0; i < 4; i++) {
216 if ((res = bus->resource[i]) == NULL || !res->flags)
217 continue;
218 if (io_offset && (res->flags & IORESOURCE_IO)) {
219 res->start += io_offset;
220 res->end += io_offset;
221 }
222 }
223 }
224 }
226 char __init *pcibios_setup(char *str)
227 {
228 return str;
229 }
231 /* the next one is stolen from the alpha port... */
233 void __init
234 pcibios_update_irq(struct pci_dev *dev, int irq)
235 {
236 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
237 }
239 int pcibios_enable_device(struct pci_dev *dev, int mask)
240 {
241 u16 cmd, old_cmd;
242 int idx;
243 struct resource *r;
245 pci_read_config_word(dev, PCI_COMMAND, &cmd);
246 old_cmd = cmd;
247 for (idx=0; idx<6; idx++) {
248 r = &dev->resource[idx];
249 if (!r->start && r->end) {
250 printk(KERN_ERR "PCI: Device %s not available because "
251 "of resource collisions\n", pci_name(dev));
252 return -EINVAL;
253 }
254 if (r->flags & IORESOURCE_IO)
255 cmd |= PCI_COMMAND_IO;
256 if (r->flags & IORESOURCE_MEM)
257 cmd |= PCI_COMMAND_MEMORY;
258 }
259 if (cmd != old_cmd) {
260 printk("PCI: Enabling device %s (%04x -> %04x)\n",
261 pci_name(dev), old_cmd, cmd);
262 pci_write_config_word(dev, PCI_COMMAND, cmd);
263 }
265 return 0;
266 }
268 #ifdef CONFIG_PROC_FS
270 /*
271 * Return the index of the PCI controller for device pdev.
272 */
274 int
275 pci_controller_num(struct pci_dev *dev)
276 {
277 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
278 return pci_ctrl->index;
279 }
281 #endif /* CONFIG_PROC_FS */
283 /*
284 * Platform support for /proc/bus/pci/X/Y mmap()s,
285 * modelled on the sparc64 implementation by Dave Miller.
286 * -- paulus.
287 */
289 /*
290 * Adjust vm_pgoff of VMA such that it is the physical page offset
291 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
292 *
293 * Basically, the user finds the base address for his device which he wishes
294 * to mmap. They read the 32-bit value from the config space base register,
295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
296 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
297 *
298 * Returns negative error code on failure, zero on success.
299 */
300 static __inline__ int
301 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
302 enum pci_mmap_state mmap_state)
303 {
304 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
305 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
306 unsigned long io_offset = 0;
307 int i, res_bit;
309 if (pci_ctrl == 0)
310 return -EINVAL; /* should never happen */
312 /* If memory, add on the PCI bridge address offset */
313 if (mmap_state == pci_mmap_mem) {
314 res_bit = IORESOURCE_MEM;
315 } else {
316 io_offset = (unsigned long)pci_ctrl->io_space.base;
317 offset += io_offset;
318 res_bit = IORESOURCE_IO;
319 }
321 /*
322 * Check that the offset requested corresponds to one of the
323 * resources of the device.
324 */
325 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
326 struct resource *rp = &dev->resource[i];
327 int flags = rp->flags;
329 /* treat ROM as memory (should be already) */
330 if (i == PCI_ROM_RESOURCE)
331 flags |= IORESOURCE_MEM;
333 /* Active and same type? */
334 if ((flags & res_bit) == 0)
335 continue;
337 /* In the range of this resource? */
338 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
339 continue;
341 /* found it! construct the final physical address */
342 if (mmap_state == pci_mmap_io)
343 offset += pci_ctrl->io_space.start - io_offset;
344 vma->vm_pgoff = offset >> PAGE_SHIFT;
345 return 0;
346 }
348 return -EINVAL;
349 }
351 /*
352 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
353 * device mapping.
354 */
355 static __inline__ void
356 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
357 enum pci_mmap_state mmap_state, int write_combine)
358 {
359 int prot = pgprot_val(vma->vm_page_prot);
361 /* Set to write-through */
362 prot &= ~_PAGE_NO_CACHE;
363 #if 0
364 if (!write_combine)
365 prot |= _PAGE_WRITETHRU;
366 #endif
367 vma->vm_page_prot = __pgprot(prot);
368 }
370 /*
371 * Perform the actual remap of the pages for a PCI device mapping, as
372 * appropriate for this architecture. The region in the process to map
373 * is described by vm_start and vm_end members of VMA, the base physical
374 * address is found in vm_pgoff.
375 * The pci device structure is provided so that architectures may make mapping
376 * decisions on a per-device or per-bus basis.
377 *
378 * Returns a negative error code on failure, zero on success.
379 */
380 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
381 enum pci_mmap_state mmap_state,
382 int write_combine)
383 {
384 int ret;
386 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
387 if (ret < 0)
388 return ret;
390 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
392 ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
393 vma->vm_end - vma->vm_start,vma->vm_page_prot);
395 return ret;
396 }
398 /*
399 * This probably belongs here rather than ioport.c because
400 * we do not want this crud linked into SBus kernels.
401 * Also, think for a moment about likes of floppy.c that
402 * include architecture specific parts. They may want to redefine ins/outs.
403 *
404 * We do not use horroble macroses here because we want to
405 * advance pointer by sizeof(size).
406 */
407 void outsb(unsigned long addr, const void *src, unsigned long count) {
408 while (count) {
409 count -= 1;
410 writeb(*(const char *)src, addr);
411 src += 1;
412 addr += 1;
413 }
414 }
416 void outsw(unsigned long addr, const void *src, unsigned long count) {
417 while (count) {
418 count -= 2;
419 writew(*(const short *)src, addr);
420 src += 2;
421 addr += 2;
422 }
423 }
425 void outsl(unsigned long addr, const void *src, unsigned long count) {
426 while (count) {
427 count -= 4;
428 writel(*(const long *)src, addr);
429 src += 4;
430 addr += 4;
431 }
432 }
434 void insb(unsigned long addr, void *dst, unsigned long count) {
435 while (count) {
436 count -= 1;
437 *(unsigned char *)dst = readb(addr);
438 dst += 1;
439 addr += 1;
440 }
441 }
443 void insw(unsigned long addr, void *dst, unsigned long count) {
444 while (count) {
445 count -= 2;
446 *(unsigned short *)dst = readw(addr);
447 dst += 2;
448 addr += 2;
449 }
450 }
452 void insl(unsigned long addr, void *dst, unsigned long count) {
453 while (count) {
454 count -= 4;
455 /*
456 * XXX I am sure we are in for an unaligned trap here.
457 */
458 *(unsigned long *)dst = readl(addr);
459 dst += 4;
460 addr += 4;
461 }
462 }