ia64/linux-2.6.18-xen.hg

view arch/cris/arch-v10/kernel/time.c @ 647:a5bb490065f6

Fix the build after public header sync.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Aug 13 14:01:49 2008 +0100 (2008-08-13)
parents 831230e53067
children
line source
1 /* $Id: time.c,v 1.5 2004/09/29 06:12:46 starvik Exp $
2 *
3 * linux/arch/cris/arch-v10/kernel/time.c
4 *
5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * Copyright (C) 1999-2002 Axis Communications AB
7 *
8 */
10 #include <linux/timex.h>
11 #include <linux/time.h>
12 #include <linux/jiffies.h>
13 #include <linux/interrupt.h>
14 #include <linux/swap.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <asm/arch/svinto.h>
18 #include <asm/types.h>
19 #include <asm/signal.h>
20 #include <asm/io.h>
21 #include <asm/delay.h>
22 #include <asm/rtc.h>
24 /* define this if you need to use print_timestamp */
25 /* it will make jiffies at 96 hz instead of 100 hz though */
26 #undef USE_CASCADE_TIMERS
28 extern void update_xtime_from_cmos(void);
29 extern int set_rtc_mmss(unsigned long nowtime);
30 extern int setup_irq(int, struct irqaction *);
31 extern int have_rtc;
33 unsigned long get_ns_in_jiffie(void)
34 {
35 unsigned char timer_count, t1;
36 unsigned short presc_count;
37 unsigned long ns;
38 unsigned long flags;
40 local_irq_save(flags);
41 local_irq_disable();
42 timer_count = *R_TIMER0_DATA;
43 presc_count = *R_TIM_PRESC_STATUS;
44 /* presc_count might be wrapped */
45 t1 = *R_TIMER0_DATA;
47 if (timer_count != t1){
48 /* it wrapped, read prescaler again... */
49 presc_count = *R_TIM_PRESC_STATUS;
50 timer_count = t1;
51 }
52 local_irq_restore(flags);
53 if (presc_count >= PRESCALE_VALUE/2 ){
54 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
55 } else {
56 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
57 }
59 ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
60 ( (presc_count) * (1000000000/PRESCALE_FREQ));
61 return ns;
62 }
64 unsigned long do_slow_gettimeoffset(void)
65 {
66 unsigned long count, t1;
67 unsigned long usec_count = 0;
68 unsigned short presc_count;
70 static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
71 static unsigned long jiffies_p = 0;
73 /*
74 * cache volatile jiffies temporarily; we have IRQs turned off.
75 */
76 unsigned long jiffies_t;
78 /* The timer interrupt comes from Etrax timer 0. In order to get
79 * better precision, we check the current value. It might have
80 * underflowed already though.
81 */
83 #ifndef CONFIG_SVINTO_SIM
84 /* Not available in the xsim simulator. */
85 count = *R_TIMER0_DATA;
86 presc_count = *R_TIM_PRESC_STATUS;
87 /* presc_count might be wrapped */
88 t1 = *R_TIMER0_DATA;
89 if (count != t1){
90 /* it wrapped, read prescaler again... */
91 presc_count = *R_TIM_PRESC_STATUS;
92 count = t1;
93 }
94 #else
95 count = 0;
96 presc_count = 0;
97 #endif
99 jiffies_t = jiffies;
101 /*
102 * avoiding timer inconsistencies (they are rare, but they happen)...
103 * there are one problem that must be avoided here:
104 * 1. the timer counter underflows
105 */
106 if( jiffies_t == jiffies_p ) {
107 if( count > count_p ) {
108 /* Timer wrapped, use new count and prescale
109 * increase the time corresponding to one jiffie
110 */
111 usec_count = 1000000/HZ;
112 }
113 } else
114 jiffies_p = jiffies_t;
115 count_p = count;
116 if (presc_count >= PRESCALE_VALUE/2 ){
117 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
118 } else {
119 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
120 }
121 /* Convert timer value to usec */
122 usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
123 (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
125 return usec_count;
126 }
128 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
129 *
130 * 3.10.4 Watchdog timer
132 * When the watchdog timer is started, it generates an NMI if the watchdog
133 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
134 * stopped after an additional 3.3 ms, the watchdog resets the chip.
135 * The watchdog timer is stopped after reset. The watchdog timer is controlled
136 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
137 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
138 * described in the table below:
139 *
140 * Watchdog Value written:
141 * state: To enable: To key: Operation:
142 * -------- ---------- ------- ----------
143 * stopped 0 X No effect.
144 * stopped 1 key_val Start watchdog with key = key_val.
145 * started 0 ~key Stop watchdog
146 * started 1 ~key Restart watchdog with key = ~key.
147 * started X new_key_val Change key to new_key_val.
148 *
149 * Note: '~' is the bitwise NOT operator.
150 *
151 */
153 /* right now, starting the watchdog is the same as resetting it */
154 #define start_watchdog reset_watchdog
156 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
157 static int watchdog_key = 0; /* arbitrary number */
158 #endif
160 /* number of pages to consider "out of memory". it is normal that the memory
161 * is used though, so put this really low.
162 */
164 #define WATCHDOG_MIN_FREE_PAGES 8
166 void
167 reset_watchdog(void)
168 {
169 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
170 /* only keep watchdog happy as long as we have memory left! */
171 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
172 /* reset the watchdog with the inverse of the old key */
173 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
174 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
175 IO_STATE(R_WATCHDOG, enable, start);
176 }
177 #endif
178 }
180 /* stop the watchdog - we still need the correct key */
182 void
183 stop_watchdog(void)
184 {
185 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
186 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
187 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
188 IO_STATE(R_WATCHDOG, enable, stop);
189 #endif
190 }
192 /* last time the cmos clock got updated */
193 static long last_rtc_update = 0;
195 /*
196 * timer_interrupt() needs to keep up the real-time clock,
197 * as well as call the "do_timer()" routine every clocktick
198 */
200 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
202 extern void cris_do_profile(struct pt_regs *regs);
204 static inline irqreturn_t
205 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
206 {
207 /* acknowledge the timer irq */
209 #ifdef USE_CASCADE_TIMERS
210 *R_TIMER_CTRL =
211 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
212 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
213 IO_STATE( R_TIMER_CTRL, i1, clr) |
214 IO_STATE( R_TIMER_CTRL, tm1, run) |
215 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
216 IO_STATE( R_TIMER_CTRL, i0, clr) |
217 IO_STATE( R_TIMER_CTRL, tm0, run) |
218 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
219 #else
220 *R_TIMER_CTRL = r_timer_ctrl_shadow |
221 IO_STATE(R_TIMER_CTRL, i0, clr);
222 #endif
224 /* reset watchdog otherwise it resets us! */
226 reset_watchdog();
228 /* call the real timer interrupt handler */
230 do_timer(regs);
232 cris_do_profile(regs); /* Save profiling information */
234 /*
235 * If we have an externally synchronized Linux clock, then update
236 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
237 * called as close as possible to 500 ms before the new second starts.
238 *
239 * The division here is not time critical since it will run once in
240 * 11 minutes
241 */
242 if (ntp_synced() &&
243 xtime.tv_sec > last_rtc_update + 660 &&
244 (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
245 (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
246 if (set_rtc_mmss(xtime.tv_sec) == 0)
247 last_rtc_update = xtime.tv_sec;
248 else
249 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
250 }
251 return IRQ_HANDLED;
252 }
254 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
255 * it needs to be IRQF_DISABLED to make the jiffies update work properly
256 */
258 static struct irqaction irq2 = { timer_interrupt, IRQF_SHARED | IRQF_DISABLED,
259 CPU_MASK_NONE, "timer", NULL, NULL};
261 void __init
262 time_init(void)
263 {
264 /* probe for the RTC and read it if it exists
265 * Before the RTC can be probed the loops_per_usec variable needs
266 * to be initialized to make usleep work. A better value for
267 * loops_per_usec is calculated by the kernel later once the
268 * clock has started.
269 */
270 loops_per_usec = 50;
272 if(RTC_INIT() < 0) {
273 /* no RTC, start at 1980 */
274 xtime.tv_sec = 0;
275 xtime.tv_nsec = 0;
276 have_rtc = 0;
277 } else {
278 /* get the current time */
279 have_rtc = 1;
280 update_xtime_from_cmos();
281 }
283 /*
284 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
285 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
286 */
287 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
289 /* Setup the etrax timers
290 * Base frequency is 25000 hz, divider 250 -> 100 HZ
291 * In normal mode, we use timer0, so timer1 is free. In cascade
292 * mode (which we sometimes use for debugging) both timers are used.
293 * Remember that linux/timex.h contains #defines that rely on the
294 * timer settings below (hz and divide factor) !!!
295 */
297 #ifdef USE_CASCADE_TIMERS
298 *R_TIMER_CTRL =
299 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
300 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
301 IO_STATE( R_TIMER_CTRL, i1, nop) |
302 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
303 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
304 IO_STATE( R_TIMER_CTRL, i0, nop) |
305 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
306 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
308 *R_TIMER_CTRL = r_timer_ctrl_shadow =
309 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
310 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
311 IO_STATE( R_TIMER_CTRL, i1, nop) |
312 IO_STATE( R_TIMER_CTRL, tm1, run) |
313 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
314 IO_STATE( R_TIMER_CTRL, i0, nop) |
315 IO_STATE( R_TIMER_CTRL, tm0, run) |
316 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
317 #else
318 *R_TIMER_CTRL =
319 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
320 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
321 IO_STATE(R_TIMER_CTRL, i1, nop) |
322 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
323 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
324 IO_STATE(R_TIMER_CTRL, i0, nop) |
325 IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
326 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
328 *R_TIMER_CTRL = r_timer_ctrl_shadow =
329 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
330 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
331 IO_STATE(R_TIMER_CTRL, i1, nop) |
332 IO_STATE(R_TIMER_CTRL, tm1, run) |
333 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
334 IO_STATE(R_TIMER_CTRL, i0, nop) |
335 IO_STATE(R_TIMER_CTRL, tm0, run) |
336 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
338 *R_TIMER_PRESCALE = PRESCALE_VALUE;
339 #endif
341 *R_IRQ_MASK0_SET =
342 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
344 /* now actually register the timer irq handler that calls timer_interrupt() */
346 setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
348 /* enable watchdog if we should use one */
350 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
351 printk("Enabling watchdog...\n");
352 start_watchdog();
354 /* If we use the hardware watchdog, we want to trap it as an NMI
355 and dump registers before it resets us. For this to happen, we
356 must set the "m" NMI enable flag (which once set, is unset only
357 when an NMI is taken).
359 The same goes for the external NMI, but that doesn't have any
360 driver or infrastructure support yet. */
361 asm ("setf m");
363 *R_IRQ_MASK0_SET =
364 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
365 *R_VECT_MASK_SET =
366 IO_STATE(R_VECT_MASK_SET, nmi, set);
367 #endif
368 }