ia64/linux-2.6.18-xen.hg

view arch/i386/kernel/cpu/common-xen.c @ 871:9cbcc9008446

xen/x86: don't initialize cpu_data[]'s apicid field on generic code

Afaict, this is not only redundant with the intialization done in
drivers/xen/core/smpboot.c, but actually results - at least for
secondary CPUs - in the Xen-specific value written to be later
overwritten with whatever the generic code determines (with no
guarantee that the two values are identical).

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu May 14 10:09:15 2009 +0100 (2009-05-14)
parents d43906ea0e9c
children
line source
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
10 #include <asm/i387.h>
11 #include <asm/msr.h>
12 #include <asm/io.h>
13 #include <asm/mmu_context.h>
14 #include <asm/mtrr.h>
15 #include <asm/mce.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
18 #include <asm/apic.h>
19 #include <mach_apic.h>
20 #else
21 #ifdef CONFIG_XEN
22 #define phys_pkg_id(a,b) a
23 #endif
24 #endif
25 #include <asm/hypervisor.h>
27 #include "cpu.h"
29 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
30 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
32 #ifndef CONFIG_XEN
33 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
34 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
35 #endif
37 static int cachesize_override __cpuinitdata = -1;
38 static int disable_x86_fxsr __cpuinitdata;
39 static int disable_x86_serial_nr __cpuinitdata = 1;
40 static int disable_x86_sep __cpuinitdata;
42 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
44 extern int disable_pse;
46 static void default_init(struct cpuinfo_x86 * c)
47 {
48 /* Not much we can do here... */
49 /* Check if at least it has cpuid */
50 if (c->cpuid_level == -1) {
51 /* No cpuid. It must be an ancient CPU */
52 if (c->x86 == 4)
53 strcpy(c->x86_model_id, "486");
54 else if (c->x86 == 3)
55 strcpy(c->x86_model_id, "386");
56 }
57 }
59 static struct cpu_dev default_cpu = {
60 .c_init = default_init,
61 .c_vendor = "Unknown",
62 };
63 static struct cpu_dev * this_cpu = &default_cpu;
65 static int __init cachesize_setup(char *str)
66 {
67 get_option (&str, &cachesize_override);
68 return 1;
69 }
70 __setup("cachesize=", cachesize_setup);
72 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
73 {
74 unsigned int *v;
75 char *p, *q;
77 if (cpuid_eax(0x80000000) < 0x80000004)
78 return 0;
80 v = (unsigned int *) c->x86_model_id;
81 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
82 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
83 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
84 c->x86_model_id[48] = 0;
86 /* Intel chips right-justify this string for some dumb reason;
87 undo that brain damage */
88 p = q = &c->x86_model_id[0];
89 while ( *p == ' ' )
90 p++;
91 if ( p != q ) {
92 while ( *p )
93 *q++ = *p++;
94 while ( q <= &c->x86_model_id[48] )
95 *q++ = '\0'; /* Zero-pad the rest */
96 }
98 return 1;
99 }
102 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
103 {
104 unsigned int n, dummy, ecx, edx, l2size;
106 n = cpuid_eax(0x80000000);
108 if (n >= 0x80000005) {
109 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
110 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
111 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
112 c->x86_cache_size=(ecx>>24)+(edx>>24);
113 }
115 if (n < 0x80000006) /* Some chips just has a large L1. */
116 return;
118 ecx = cpuid_ecx(0x80000006);
119 l2size = ecx >> 16;
121 /* do processor-specific cache resizing */
122 if (this_cpu->c_size_cache)
123 l2size = this_cpu->c_size_cache(c,l2size);
125 /* Allow user to override all this if necessary. */
126 if (cachesize_override != -1)
127 l2size = cachesize_override;
129 if ( l2size == 0 )
130 return; /* Again, no L2 cache is possible */
132 c->x86_cache_size = l2size;
134 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
135 l2size, ecx & 0xFF);
136 }
138 /* Naming convention should be: <Name> [(<Codename>)] */
139 /* This table only is used unless init_<vendor>() below doesn't set it; */
140 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
142 /* Look up CPU names by table lookup. */
143 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
144 {
145 struct cpu_model_info *info;
147 if ( c->x86_model >= 16 )
148 return NULL; /* Range check */
150 if (!this_cpu)
151 return NULL;
153 info = this_cpu->c_models;
155 while (info && info->family) {
156 if (info->family == c->x86)
157 return info->model_names[c->x86_model];
158 info++;
159 }
160 return NULL; /* Not found */
161 }
164 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
165 {
166 char *v = c->x86_vendor_id;
167 int i;
168 static int printed;
170 for (i = 0; i < X86_VENDOR_NUM; i++) {
171 if (cpu_devs[i]) {
172 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
173 (cpu_devs[i]->c_ident[1] &&
174 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
175 c->x86_vendor = i;
176 if (!early)
177 this_cpu = cpu_devs[i];
178 return;
179 }
180 }
181 }
182 if (!printed) {
183 printed++;
184 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
185 printk(KERN_ERR "CPU: Your system may be unstable.\n");
186 }
187 c->x86_vendor = X86_VENDOR_UNKNOWN;
188 this_cpu = &default_cpu;
189 }
192 static int __init x86_fxsr_setup(char * s)
193 {
194 disable_x86_fxsr = 1;
195 return 1;
196 }
197 __setup("nofxsr", x86_fxsr_setup);
200 static int __init x86_sep_setup(char * s)
201 {
202 disable_x86_sep = 1;
203 return 1;
204 }
205 __setup("nosep", x86_sep_setup);
208 /* Standard macro to see if a specific flag is changeable */
209 static inline int flag_is_changeable_p(u32 flag)
210 {
211 u32 f1, f2;
213 asm("pushfl\n\t"
214 "pushfl\n\t"
215 "popl %0\n\t"
216 "movl %0,%1\n\t"
217 "xorl %2,%0\n\t"
218 "pushl %0\n\t"
219 "popfl\n\t"
220 "pushfl\n\t"
221 "popl %0\n\t"
222 "popfl\n\t"
223 : "=&r" (f1), "=&r" (f2)
224 : "ir" (flag));
226 return ((f1^f2) & flag) != 0;
227 }
230 /* Probe for the CPUID instruction */
231 static int __cpuinit have_cpuid_p(void)
232 {
233 return flag_is_changeable_p(X86_EFLAGS_ID);
234 }
236 /* Do minimum CPU detection early.
237 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
238 The others are not touched to avoid unwanted side effects.
240 WARNING: this function is only called on the BP. Don't add code here
241 that is supposed to run on all CPUs. */
242 static void __init early_cpu_detect(void)
243 {
244 struct cpuinfo_x86 *c = &boot_cpu_data;
246 c->x86_cache_alignment = 32;
248 if (!have_cpuid_p())
249 return;
251 /* Get vendor name */
252 cpuid(0x00000000, &c->cpuid_level,
253 (int *)&c->x86_vendor_id[0],
254 (int *)&c->x86_vendor_id[8],
255 (int *)&c->x86_vendor_id[4]);
257 get_cpu_vendor(c, 1);
259 c->x86 = 4;
260 if (c->cpuid_level >= 0x00000001) {
261 u32 junk, tfms, cap0, misc;
262 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
263 c->x86 = (tfms >> 8) & 15;
264 c->x86_model = (tfms >> 4) & 15;
265 if (c->x86 == 0xf)
266 c->x86 += (tfms >> 20) & 0xff;
267 if (c->x86 >= 0x6)
268 c->x86_model += ((tfms >> 16) & 0xF) << 4;
269 c->x86_mask = tfms & 15;
270 if (cap0 & (1<<19))
271 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
272 }
273 }
275 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
276 {
277 u32 tfms, xlvl;
278 int ebx;
280 if (have_cpuid_p()) {
281 /* Get vendor name */
282 cpuid(0x00000000, &c->cpuid_level,
283 (int *)&c->x86_vendor_id[0],
284 (int *)&c->x86_vendor_id[8],
285 (int *)&c->x86_vendor_id[4]);
287 get_cpu_vendor(c, 0);
288 /* Initialize the standard set of capabilities */
289 /* Note that the vendor-specific code below might override */
291 /* Intel-defined flags: level 0x00000001 */
292 if ( c->cpuid_level >= 0x00000001 ) {
293 u32 capability, excap;
294 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
295 c->x86_capability[0] = capability;
296 c->x86_capability[4] = excap;
297 c->x86 = (tfms >> 8) & 15;
298 c->x86_model = (tfms >> 4) & 15;
299 if (c->x86 == 0xf)
300 c->x86 += (tfms >> 20) & 0xff;
301 if (c->x86 >= 0x6)
302 c->x86_model += ((tfms >> 16) & 0xF) << 4;
303 c->x86_mask = tfms & 15;
304 #ifndef CONFIG_XEN
305 #ifdef CONFIG_X86_HT
306 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
307 #else
308 c->apicid = (ebx >> 24) & 0xFF;
309 #endif
310 #endif
311 } else {
312 /* Have CPUID level 0 only - unheard of */
313 c->x86 = 4;
314 }
316 /* AMD-defined flags: level 0x80000001 */
317 xlvl = cpuid_eax(0x80000000);
318 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
319 if ( xlvl >= 0x80000001 ) {
320 c->x86_capability[1] = cpuid_edx(0x80000001);
321 c->x86_capability[6] = cpuid_ecx(0x80000001);
322 }
323 if ( xlvl >= 0x80000004 )
324 get_model_name(c); /* Default name */
325 }
326 }
328 early_intel_workaround(c);
330 #ifdef CONFIG_X86_HT
331 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
332 #endif
333 }
335 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
336 {
337 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
338 /* Disable processor serial number */
339 unsigned long lo,hi;
340 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
341 lo |= 0x200000;
342 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
343 printk(KERN_NOTICE "CPU serial number disabled.\n");
344 clear_bit(X86_FEATURE_PN, c->x86_capability);
346 /* Disabling the serial number may affect the cpuid level */
347 c->cpuid_level = cpuid_eax(0);
348 }
349 }
351 static int __init x86_serial_nr_setup(char *s)
352 {
353 disable_x86_serial_nr = 0;
354 return 1;
355 }
356 __setup("serialnumber", x86_serial_nr_setup);
360 /*
361 * This does the hard work of actually picking apart the CPU stuff...
362 */
363 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
364 {
365 int i;
367 c->loops_per_jiffy = loops_per_jiffy;
368 c->x86_cache_size = -1;
369 c->x86_vendor = X86_VENDOR_UNKNOWN;
370 c->cpuid_level = -1; /* CPUID not detected */
371 c->x86_model = c->x86_mask = 0; /* So far unknown... */
372 c->x86_vendor_id[0] = '\0'; /* Unset */
373 c->x86_model_id[0] = '\0'; /* Unset */
374 c->x86_max_cores = 1;
375 memset(&c->x86_capability, 0, sizeof c->x86_capability);
377 if (!have_cpuid_p()) {
378 /* First of all, decide if this is a 486 or higher */
379 /* It's a 486 if we can modify the AC flag */
380 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
381 c->x86 = 4;
382 else
383 c->x86 = 3;
384 }
386 generic_identify(c);
388 printk(KERN_DEBUG "CPU: After generic identify, caps:");
389 for (i = 0; i < NCAPINTS; i++)
390 printk(" %08lx", c->x86_capability[i]);
391 printk("\n");
393 if (this_cpu->c_identify) {
394 this_cpu->c_identify(c);
396 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
397 for (i = 0; i < NCAPINTS; i++)
398 printk(" %08lx", c->x86_capability[i]);
399 printk("\n");
400 }
402 /*
403 * Vendor-specific initialization. In this section we
404 * canonicalize the feature flags, meaning if there are
405 * features a certain CPU supports which CPUID doesn't
406 * tell us, CPUID claiming incorrect flags, or other bugs,
407 * we handle them here.
408 *
409 * At the end of this section, c->x86_capability better
410 * indicate the features this CPU genuinely supports!
411 */
412 if (this_cpu->c_init)
413 this_cpu->c_init(c);
415 /* Disable the PN if appropriate */
416 squash_the_stupid_serial_number(c);
418 /*
419 * The vendor-specific functions might have changed features. Now
420 * we do "generic changes."
421 */
423 /* TSC disabled? */
424 if ( tsc_disable )
425 clear_bit(X86_FEATURE_TSC, c->x86_capability);
427 /* FXSR disabled? */
428 if (disable_x86_fxsr) {
429 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
430 clear_bit(X86_FEATURE_XMM, c->x86_capability);
431 }
433 /* SEP disabled? */
434 if (disable_x86_sep)
435 clear_bit(X86_FEATURE_SEP, c->x86_capability);
437 if (disable_pse)
438 clear_bit(X86_FEATURE_PSE, c->x86_capability);
440 /* If the model name is still unset, do table lookup. */
441 if ( !c->x86_model_id[0] ) {
442 char *p;
443 p = table_lookup_model(c);
444 if ( p )
445 strcpy(c->x86_model_id, p);
446 else
447 /* Last resort... */
448 sprintf(c->x86_model_id, "%02x/%02x",
449 c->x86, c->x86_model);
450 }
452 /* Now the feature flags better reflect actual CPU features! */
454 printk(KERN_DEBUG "CPU: After all inits, caps:");
455 for (i = 0; i < NCAPINTS; i++)
456 printk(" %08lx", c->x86_capability[i]);
457 printk("\n");
459 /*
460 * On SMP, boot_cpu_data holds the common feature set between
461 * all CPUs; so make sure that we indicate which features are
462 * common between the CPUs. The first time this routine gets
463 * executed, c == &boot_cpu_data.
464 */
465 if ( c != &boot_cpu_data ) {
466 /* AND the already accumulated flags with these */
467 for ( i = 0 ; i < NCAPINTS ; i++ )
468 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
469 }
471 /* Init Machine Check Exception if available. */
472 mcheck_init(c);
474 if (c == &boot_cpu_data)
475 sysenter_setup();
476 enable_sep_cpu();
478 if (c == &boot_cpu_data)
479 mtrr_bp_init();
480 else
481 mtrr_ap_init();
482 }
484 #ifdef CONFIG_X86_HT
485 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
486 {
487 u32 eax, ebx, ecx, edx;
488 int index_msb, core_bits;
490 cpuid(1, &eax, &ebx, &ecx, &edx);
492 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
493 return;
495 smp_num_siblings = (ebx & 0xff0000) >> 16;
497 if (smp_num_siblings == 1) {
498 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
499 } else if (smp_num_siblings > 1 ) {
501 if (smp_num_siblings > NR_CPUS) {
502 printk(KERN_WARNING "CPU: Unsupported number of the "
503 "siblings %d", smp_num_siblings);
504 smp_num_siblings = 1;
505 return;
506 }
508 index_msb = get_count_order(smp_num_siblings);
509 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
511 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
512 c->phys_proc_id);
514 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
516 index_msb = get_count_order(smp_num_siblings) ;
518 core_bits = get_count_order(c->x86_max_cores);
520 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
521 ((1 << core_bits) - 1);
523 if (c->x86_max_cores > 1)
524 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
525 c->cpu_core_id);
526 }
527 }
528 #endif
530 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
531 {
532 char *vendor = NULL;
534 if (c->x86_vendor < X86_VENDOR_NUM)
535 vendor = this_cpu->c_vendor;
536 else if (c->cpuid_level >= 0)
537 vendor = c->x86_vendor_id;
539 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
540 printk("%s ", vendor);
542 if (!c->x86_model_id[0])
543 printk("%d86", c->x86);
544 else
545 printk("%s", c->x86_model_id);
547 if (c->x86_mask || c->cpuid_level >= 0)
548 printk(" stepping %02x\n", c->x86_mask);
549 else
550 printk("\n");
551 }
553 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
555 /* This is hacky. :)
556 * We're emulating future behavior.
557 * In the future, the cpu-specific init functions will be called implicitly
558 * via the magic of initcalls.
559 * They will insert themselves into the cpu_devs structure.
560 * Then, when cpu_init() is called, we can just iterate over that array.
561 */
563 extern int intel_cpu_init(void);
564 extern int cyrix_init_cpu(void);
565 extern int nsc_init_cpu(void);
566 extern int amd_init_cpu(void);
567 extern int centaur_init_cpu(void);
568 extern int transmeta_init_cpu(void);
569 extern int rise_init_cpu(void);
570 extern int nexgen_init_cpu(void);
571 extern int umc_init_cpu(void);
573 void __init early_cpu_init(void)
574 {
575 intel_cpu_init();
576 cyrix_init_cpu();
577 nsc_init_cpu();
578 amd_init_cpu();
579 centaur_init_cpu();
580 transmeta_init_cpu();
581 rise_init_cpu();
582 nexgen_init_cpu();
583 umc_init_cpu();
584 early_cpu_detect();
586 #ifdef CONFIG_DEBUG_PAGEALLOC
587 /* pse is not compatible with on-the-fly unmapping,
588 * disable it even if the cpus claim to support it.
589 */
590 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
591 disable_pse = 1;
592 #endif
593 }
595 static void __cpuinit cpu_gdt_init(const struct Xgt_desc_struct *gdt_descr)
596 {
597 unsigned long frames[16];
598 unsigned long va;
599 int f;
601 for (va = gdt_descr->address, f = 0;
602 va < gdt_descr->address + gdt_descr->size;
603 va += PAGE_SIZE, f++) {
604 frames[f] = virt_to_mfn(va);
605 make_lowmem_page_readonly(
606 (void *)va, XENFEAT_writable_descriptor_tables);
607 }
608 if (HYPERVISOR_set_gdt(frames, (gdt_descr->size + 1) / 8))
609 BUG();
610 }
612 /*
613 * cpu_init() initializes state that is per-CPU. Some data is already
614 * initialized (naturally) in the bootstrap process, such as the GDT
615 * and IDT. We reload them nevertheless, this function acts as a
616 * 'CPU state barrier', nothing should get across.
617 */
618 void __cpuinit cpu_init(void)
619 {
620 int cpu = smp_processor_id();
621 #ifndef CONFIG_X86_NO_TSS
622 struct tss_struct * t = &per_cpu(init_tss, cpu);
623 #endif
624 struct thread_struct *thread = &current->thread;
625 struct desc_struct *gdt;
626 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
628 if (cpu_test_and_set(cpu, cpu_initialized)) {
629 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
630 for (;;) local_irq_enable();
631 }
632 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
634 if (cpu_has_vme || cpu_has_de)
635 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
636 if (tsc_disable && cpu_has_tsc) {
637 printk(KERN_NOTICE "Disabling TSC...\n");
638 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
639 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
640 set_in_cr4(X86_CR4_TSD);
641 }
643 #ifndef CONFIG_XEN
644 /* The CPU hotplug case */
645 if (cpu_gdt_descr->address) {
646 gdt = (struct desc_struct *)cpu_gdt_descr->address;
647 memset(gdt, 0, PAGE_SIZE);
648 goto old_gdt;
649 }
650 /*
651 * This is a horrible hack to allocate the GDT. The problem
652 * is that cpu_init() is called really early for the boot CPU
653 * (and hence needs bootmem) but much later for the secondary
654 * CPUs, when bootmem will have gone away
655 */
656 if (NODE_DATA(0)->bdata->node_bootmem_map) {
657 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
658 /* alloc_bootmem_pages panics on failure, so no check */
659 memset(gdt, 0, PAGE_SIZE);
660 } else {
661 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
662 if (unlikely(!gdt)) {
663 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
664 for (;;)
665 local_irq_enable();
666 }
667 }
668 old_gdt:
669 /*
670 * Initialize the per-CPU GDT with the boot GDT,
671 * and set up the GDT descriptor:
672 */
673 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
675 /* Set up GDT entry for 16bit stack */
676 *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
677 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
678 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
679 (CPU_16BIT_STACK_SIZE - 1);
681 cpu_gdt_descr->size = GDT_SIZE - 1;
682 cpu_gdt_descr->address = (unsigned long)gdt;
683 #else
684 if (cpu == 0 && cpu_gdt_descr->address == 0) {
685 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
686 /* alloc_bootmem_pages panics on failure, so no check */
687 memset(gdt, 0, PAGE_SIZE);
689 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
691 cpu_gdt_descr->size = GDT_SIZE;
692 cpu_gdt_descr->address = (unsigned long)gdt;
693 }
694 #endif
696 cpu_gdt_init(cpu_gdt_descr);
698 /*
699 * Set up and load the per-CPU TSS and LDT
700 */
701 atomic_inc(&init_mm.mm_count);
702 current->active_mm = &init_mm;
703 if (current->mm)
704 BUG();
705 enter_lazy_tlb(&init_mm, current);
707 load_esp0(t, thread);
709 load_LDT(&init_mm.context);
711 #ifdef CONFIG_DOUBLEFAULT
712 /* Set up doublefault TSS pointer in the GDT */
713 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
714 #endif
716 /* Clear %fs and %gs. */
717 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
719 /* Clear all 6 debug registers: */
720 set_debugreg(0, 0);
721 set_debugreg(0, 1);
722 set_debugreg(0, 2);
723 set_debugreg(0, 3);
724 set_debugreg(0, 6);
725 set_debugreg(0, 7);
727 /*
728 * Force FPU initialization:
729 */
730 current_thread_info()->status = 0;
731 clear_used_math();
732 mxcsr_feature_mask_init();
733 }
735 #ifdef CONFIG_HOTPLUG_CPU
736 void __cpuinit cpu_uninit(void)
737 {
738 int cpu = raw_smp_processor_id();
739 cpu_clear(cpu, cpu_initialized);
741 /* lazy TLB state */
742 per_cpu(cpu_tlbstate, cpu).state = 0;
743 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
744 }
745 #endif