ia64/linux-2.6.18-xen.hg

view drivers/pci/pci.c @ 817:9b150690cb22

Backport: PCI: remove unnecessary condition check in pci_restore_bars()

commit bc5f5a8277cb353161454b6704b3186ebcf3a2a3
Author: Yu Zhao <yu.zhao@intel.com>
Date: Sat Nov 22 02:40:00 2008 +0800

PCI: remove unnecessary condition check in pci_restore_bars()

Remove the unnecessary number of resources condition checks
because
the pci_update_resource() will check availability of the
resources.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Mar 13 08:50:44 2009 +0000 (2009-03-13)
parents f0dd7eb92bc9
children 13a42de2f9c5
line source
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
20 #include "pci.h"
22 unsigned int pci_pm_d3_delay = 10;
24 /**
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
27 *
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
30 */
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
33 {
34 struct list_head *tmp;
35 unsigned char max, n;
37 max = bus->subordinate;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
40 if(n > max)
41 max = n;
42 }
43 return max;
44 }
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
47 #if 0
48 /**
49 * pci_max_busnr - returns maximum PCI bus number
50 *
51 * Returns the highest PCI bus number present in the system global list of
52 * PCI buses.
53 */
54 unsigned char __devinit
55 pci_max_busnr(void)
56 {
57 struct pci_bus *bus = NULL;
58 unsigned char max, n;
60 max = 0;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
63 if(n > max)
64 max = n;
65 }
66 return max;
67 }
69 #endif /* 0 */
71 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
72 {
73 u8 id;
74 int ttl = 48;
76 while (ttl--) {
77 pci_bus_read_config_byte(bus, devfn, pos, &pos);
78 if (pos < 0x40)
79 break;
80 pos &= ~3;
81 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
82 &id);
83 if (id == 0xff)
84 break;
85 if (id == cap)
86 return pos;
87 pos += PCI_CAP_LIST_NEXT;
88 }
89 return 0;
90 }
92 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
93 {
94 return __pci_find_next_cap(dev->bus, dev->devfn,
95 pos + PCI_CAP_LIST_NEXT, cap);
96 }
97 EXPORT_SYMBOL_GPL(pci_find_next_capability);
99 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
100 {
101 u16 status;
102 u8 pos;
104 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
105 if (!(status & PCI_STATUS_CAP_LIST))
106 return 0;
108 switch (hdr_type) {
109 case PCI_HEADER_TYPE_NORMAL:
110 case PCI_HEADER_TYPE_BRIDGE:
111 pos = PCI_CAPABILITY_LIST;
112 break;
113 case PCI_HEADER_TYPE_CARDBUS:
114 pos = PCI_CB_CAPABILITY_LIST;
115 break;
116 default:
117 return 0;
118 }
119 return __pci_find_next_cap(bus, devfn, pos, cap);
120 }
122 /**
123 * pci_find_capability - query for devices' capabilities
124 * @dev: PCI device to query
125 * @cap: capability code
126 *
127 * Tell if a device supports a given PCI capability.
128 * Returns the address of the requested capability structure within the
129 * device's PCI configuration space or 0 in case the device does not
130 * support it. Possible values for @cap:
131 *
132 * %PCI_CAP_ID_PM Power Management
133 * %PCI_CAP_ID_AGP Accelerated Graphics Port
134 * %PCI_CAP_ID_VPD Vital Product Data
135 * %PCI_CAP_ID_SLOTID Slot Identification
136 * %PCI_CAP_ID_MSI Message Signalled Interrupts
137 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
138 * %PCI_CAP_ID_PCIX PCI-X
139 * %PCI_CAP_ID_EXP PCI Express
140 */
141 int pci_find_capability(struct pci_dev *dev, int cap)
142 {
143 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
144 }
146 /**
147 * pci_bus_find_capability - query for devices' capabilities
148 * @bus: the PCI bus to query
149 * @devfn: PCI device to query
150 * @cap: capability code
151 *
152 * Like pci_find_capability() but works for pci devices that do not have a
153 * pci_dev structure set up yet.
154 *
155 * Returns the address of the requested capability structure within the
156 * device's PCI configuration space or 0 in case the device does not
157 * support it.
158 */
159 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
160 {
161 u8 hdr_type;
163 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
165 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
166 }
168 /**
169 * pci_find_ext_capability - Find an extended capability
170 * @dev: PCI device to query
171 * @cap: capability code
172 *
173 * Returns the address of the requested extended capability structure
174 * within the device's PCI configuration space or 0 if the device does
175 * not support it. Possible values for @cap:
176 *
177 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
178 * %PCI_EXT_CAP_ID_VC Virtual Channel
179 * %PCI_EXT_CAP_ID_DSN Device Serial Number
180 * %PCI_EXT_CAP_ID_PWR Power Budgeting
181 */
182 int pci_find_ext_capability(struct pci_dev *dev, int cap)
183 {
184 u32 header;
185 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
186 int pos = 0x100;
188 if (dev->cfg_size <= 256)
189 return 0;
191 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
192 return 0;
194 /*
195 * If we have no capabilities, this is indicated by cap ID,
196 * cap version and next pointer all being 0.
197 */
198 if (header == 0)
199 return 0;
201 while (ttl-- > 0) {
202 if (PCI_EXT_CAP_ID(header) == cap)
203 return pos;
205 pos = PCI_EXT_CAP_NEXT(header);
206 if (pos < 0x100)
207 break;
209 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
210 break;
211 }
213 return 0;
214 }
215 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
217 /**
218 * pci_find_parent_resource - return resource region of parent bus of given region
219 * @dev: PCI device structure contains resources to be searched
220 * @res: child resource record for which parent is sought
221 *
222 * For given resource region of given device, return the resource
223 * region of parent bus the given region is contained in or where
224 * it should be allocated from.
225 */
226 struct resource *
227 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
228 {
229 const struct pci_bus *bus = dev->bus;
230 int i;
231 struct resource *best = NULL;
233 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
234 struct resource *r = bus->resource[i];
235 if (!r)
236 continue;
237 if (res->start && !(res->start >= r->start && res->end <= r->end))
238 continue; /* Not contained */
239 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
240 continue; /* Wrong type */
241 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
242 return r; /* Exact match */
243 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
244 best = r; /* Approximating prefetchable by non-prefetchable */
245 }
246 return best;
247 }
249 /**
250 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
251 * @dev: PCI device to have its BARs restored
252 *
253 * Restore the BAR values for a given device, so as to make it
254 * accessible by its driver.
255 */
256 void
257 pci_restore_bars(struct pci_dev *dev)
258 {
259 int i;
261 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
262 pci_update_resource(dev, i);
263 }
265 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
267 /**
268 * pci_set_power_state - Set the power state of a PCI device
269 * @dev: PCI device to be suspended
270 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
271 *
272 * Transition a device to a new power state, using the Power Management
273 * Capabilities in the device's config space.
274 *
275 * RETURN VALUE:
276 * -EINVAL if trying to enter a lower state than we're already in.
277 * 0 if we're already in the requested state.
278 * -EIO if device does not support PCI PM.
279 * 0 if we can successfully change the power state.
280 */
281 int
282 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
283 {
284 int pm, need_restore = 0;
285 u16 pmcsr, pmc;
287 /* bound the state we're entering */
288 if (state > PCI_D3hot)
289 state = PCI_D3hot;
291 /* Validate current state:
292 * Can enter D0 from any state, but if we can only go deeper
293 * to sleep if we're already in a low power state
294 */
295 if (state != PCI_D0 && dev->current_state > state) {
296 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
297 __FUNCTION__, pci_name(dev), state, dev->current_state);
298 return -EINVAL;
299 } else if (dev->current_state == state)
300 return 0; /* we're already there */
302 /*
303 * If the device or the parent bridge can't support PCI PM, ignore
304 * the request if we're doing anything besides putting it into D0
305 * (which would only happen on boot).
306 */
307 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
308 return 0;
310 /* find PCI PM capability in list */
311 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
313 /* abort if the device doesn't support PM capabilities */
314 if (!pm)
315 return -EIO;
317 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
318 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
319 printk(KERN_DEBUG
320 "PCI: %s has unsupported PM cap regs version (%u)\n",
321 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
322 return -EIO;
323 }
325 /* check if this device supports the desired state */
326 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
327 return -EIO;
328 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
329 return -EIO;
331 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
333 /* If we're (effectively) in D3, force entire word to 0.
334 * This doesn't affect PME_Status, disables PME_En, and
335 * sets PowerState to 0.
336 */
337 switch (dev->current_state) {
338 case PCI_D0:
339 case PCI_D1:
340 case PCI_D2:
341 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
342 pmcsr |= state;
343 break;
344 case PCI_UNKNOWN: /* Boot-up */
345 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
346 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
347 need_restore = 1;
348 /* Fall-through: force to D0 */
349 default:
350 pmcsr = 0;
351 break;
352 }
354 /* enter specified state */
355 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
357 /* Mandatory power management transition delays */
358 /* see PCI PM 1.1 5.6.1 table 18 */
359 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
360 msleep(pci_pm_d3_delay);
361 else if (state == PCI_D2 || dev->current_state == PCI_D2)
362 udelay(200);
364 /*
365 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
366 * Firmware method after native method ?
367 */
368 if (platform_pci_set_power_state)
369 platform_pci_set_power_state(dev, state);
371 dev->current_state = state;
373 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
374 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
375 * from D3hot to D0 _may_ perform an internal reset, thereby
376 * going to "D0 Uninitialized" rather than "D0 Initialized".
377 * For example, at least some versions of the 3c905B and the
378 * 3c556B exhibit this behaviour.
379 *
380 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
381 * devices in a D3hot state at boot. Consequently, we need to
382 * restore at least the BARs so that the device will be
383 * accessible to its driver.
384 */
385 if (need_restore)
386 pci_restore_bars(dev);
388 return 0;
389 }
391 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
393 /**
394 * pci_choose_state - Choose the power state of a PCI device
395 * @dev: PCI device to be suspended
396 * @state: target sleep state for the whole system. This is the value
397 * that is passed to suspend() function.
398 *
399 * Returns PCI power state suitable for given device and given system
400 * message.
401 */
403 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
404 {
405 int ret;
407 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
408 return PCI_D0;
410 if (platform_pci_choose_state) {
411 ret = platform_pci_choose_state(dev, state);
412 if (ret >= 0)
413 state.event = ret;
414 }
416 switch (state.event) {
417 case PM_EVENT_ON:
418 return PCI_D0;
419 case PM_EVENT_FREEZE:
420 case PM_EVENT_SUSPEND:
421 return PCI_D3hot;
422 default:
423 printk("They asked me for state %d\n", state.event);
424 BUG();
425 }
426 return PCI_D0;
427 }
429 EXPORT_SYMBOL(pci_choose_state);
431 /**
432 * pci_save_state - save the PCI configuration space of a device before suspending
433 * @dev: - PCI device that we're dealing with
434 */
435 int
436 pci_save_state(struct pci_dev *dev)
437 {
438 int i;
439 /* XXX: 100% dword access ok here? */
440 for (i = 0; i < 16; i++)
441 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
442 if ((i = pci_save_msi_state(dev)) != 0)
443 return i;
444 if ((i = pci_save_msix_state(dev)) != 0)
445 return i;
446 return 0;
447 }
449 /**
450 * pci_restore_state - Restore the saved state of a PCI device
451 * @dev: - PCI device that we're dealing with
452 */
453 int
454 pci_restore_state(struct pci_dev *dev)
455 {
456 int i;
457 int val;
459 /*
460 * The Base Address register should be programmed before the command
461 * register(s)
462 */
463 for (i = 15; i >= 0; i--) {
464 pci_read_config_dword(dev, i * 4, &val);
465 if (val != dev->saved_config_space[i]) {
466 printk(KERN_DEBUG "PM: Writing back config space on "
467 "device %s at offset %x (was %x, writing %x)\n",
468 pci_name(dev), i,
469 val, (int)dev->saved_config_space[i]);
470 pci_write_config_dword(dev,i * 4,
471 dev->saved_config_space[i]);
472 }
473 }
474 pci_restore_msi_state(dev);
475 pci_restore_msix_state(dev);
476 return 0;
477 }
479 /**
480 * pci_enable_device_bars - Initialize some of a device for use
481 * @dev: PCI device to be initialized
482 * @bars: bitmask of BAR's that must be configured
483 *
484 * Initialize device before it's used by a driver. Ask low-level code
485 * to enable selected I/O and memory resources. Wake up the device if it
486 * was suspended. Beware, this function can fail.
487 */
489 int
490 pci_enable_device_bars(struct pci_dev *dev, int bars)
491 {
492 int err;
494 err = pci_set_power_state(dev, PCI_D0);
495 if (err < 0 && err != -EIO)
496 return err;
497 err = pcibios_enable_device(dev, bars);
498 if (err < 0)
499 return err;
500 return 0;
501 }
503 /**
504 * pci_enable_device - Initialize device before it's used by a driver.
505 * @dev: PCI device to be initialized
506 *
507 * Initialize device before it's used by a driver. Ask low-level code
508 * to enable I/O and memory. Wake up the device if it was suspended.
509 * Beware, this function can fail.
510 */
511 int
512 pci_enable_device(struct pci_dev *dev)
513 {
514 int err;
516 if (dev->is_enabled)
517 return 0;
519 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
520 if (err)
521 return err;
522 pci_fixup_device(pci_fixup_enable, dev);
523 dev->is_enabled = 1;
524 return 0;
525 }
527 /**
528 * pcibios_disable_device - disable arch specific PCI resources for device dev
529 * @dev: the PCI device to disable
530 *
531 * Disables architecture specific PCI resources for the device. This
532 * is the default implementation. Architecture implementations can
533 * override this.
534 */
535 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
537 /**
538 * pci_disable_device - Disable PCI device after use
539 * @dev: PCI device to be disabled
540 *
541 * Signal to the system that the PCI device is not in use by the system
542 * anymore. This only involves disabling PCI bus-mastering, if active.
543 */
544 void
545 pci_disable_device(struct pci_dev *dev)
546 {
547 u16 pci_command;
549 if (dev->msi_enabled)
550 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
551 PCI_CAP_ID_MSI);
552 if (dev->msix_enabled)
553 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
554 PCI_CAP_ID_MSIX);
556 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
557 if (pci_command & PCI_COMMAND_MASTER) {
558 pci_command &= ~PCI_COMMAND_MASTER;
559 pci_write_config_word(dev, PCI_COMMAND, pci_command);
560 }
561 dev->is_busmaster = 0;
563 pcibios_disable_device(dev);
564 dev->is_enabled = 0;
565 }
567 /**
568 * pci_enable_wake - enable device to generate PME# when suspended
569 * @dev: - PCI device to operate on
570 * @state: - Current state of device.
571 * @enable: - Flag to enable or disable generation
572 *
573 * Set the bits in the device's PM Capabilities to generate PME# when
574 * the system is suspended.
575 *
576 * -EIO is returned if device doesn't have PM Capabilities.
577 * -EINVAL is returned if device supports it, but can't generate wake events.
578 * 0 if operation is successful.
579 *
580 */
581 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
582 {
583 int pm;
584 u16 value;
586 /* find PCI PM capability in list */
587 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
589 /* If device doesn't support PM Capabilities, but request is to disable
590 * wake events, it's a nop; otherwise fail */
591 if (!pm)
592 return enable ? -EIO : 0;
594 /* Check device's ability to generate PME# */
595 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
597 value &= PCI_PM_CAP_PME_MASK;
598 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
600 /* Check if it can generate PME# from requested state. */
601 if (!value || !(value & (1 << state)))
602 return enable ? -EINVAL : 0;
604 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
606 /* Clear PME_Status by writing 1 to it and enable PME# */
607 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
609 if (!enable)
610 value &= ~PCI_PM_CTRL_PME_ENABLE;
612 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
614 return 0;
615 }
617 /**
618 * pci_enable_ari - enable ARI forwarding if hardware support it
619 * @dev: the PCI device
620 */
621 void pci_enable_ari(struct pci_dev *dev)
622 {
623 int pos;
624 u32 cap;
625 u16 ctrl;
626 struct pci_dev *bridge;
628 if (dev->devfn)
629 return;
631 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
632 if (!pos)
633 return;
635 bridge = dev->bus->self;
636 if (!bridge)
637 return;
639 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
640 if (!pos)
641 return;
643 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
644 if (!(cap & PCI_EXP_DEVCAP2_ARI))
645 return;
647 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
648 ctrl |= PCI_EXP_DEVCTL2_ARI;
649 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
651 bridge->ari_enabled = 1;
652 }
654 int
655 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
656 {
657 u8 pin;
659 pin = dev->pin;
660 if (!pin)
661 return -1;
662 pin--;
663 while (dev->bus->self) {
664 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
665 dev = dev->bus->self;
666 }
667 *bridge = dev;
668 return pin;
669 }
671 /**
672 * pci_release_region - Release a PCI bar
673 * @pdev: PCI device whose resources were previously reserved by pci_request_region
674 * @bar: BAR to release
675 *
676 * Releases the PCI I/O and memory resources previously reserved by a
677 * successful call to pci_request_region. Call this function only
678 * after all use of the PCI regions has ceased.
679 */
680 void pci_release_region(struct pci_dev *pdev, int bar)
681 {
682 if (pci_resource_len(pdev, bar) == 0)
683 return;
684 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
685 release_region(pci_resource_start(pdev, bar),
686 pci_resource_len(pdev, bar));
687 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
688 release_mem_region(pci_resource_start(pdev, bar),
689 pci_resource_len(pdev, bar));
690 }
692 /**
693 * pci_request_region - Reserved PCI I/O and memory resource
694 * @pdev: PCI device whose resources are to be reserved
695 * @bar: BAR to be reserved
696 * @res_name: Name to be associated with resource.
697 *
698 * Mark the PCI region associated with PCI device @pdev BR @bar as
699 * being reserved by owner @res_name. Do not access any
700 * address inside the PCI regions unless this call returns
701 * successfully.
702 *
703 * Returns 0 on success, or %EBUSY on error. A warning
704 * message is also printed on failure.
705 */
706 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
707 {
708 if (pci_resource_len(pdev, bar) == 0)
709 return 0;
711 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
712 if (!request_region(pci_resource_start(pdev, bar),
713 pci_resource_len(pdev, bar), res_name))
714 goto err_out;
715 }
716 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
717 if (!request_mem_region(pci_resource_start(pdev, bar),
718 pci_resource_len(pdev, bar), res_name))
719 goto err_out;
720 }
722 return 0;
724 err_out:
725 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
726 "for device %s\n",
727 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
728 bar + 1, /* PCI BAR # */
729 (unsigned long long)pci_resource_len(pdev, bar),
730 (unsigned long long)pci_resource_start(pdev, bar),
731 pci_name(pdev));
732 return -EBUSY;
733 }
736 /**
737 * pci_release_regions - Release reserved PCI I/O and memory resources
738 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
739 *
740 * Releases all PCI I/O and memory resources previously reserved by a
741 * successful call to pci_request_regions. Call this function only
742 * after all use of the PCI regions has ceased.
743 */
745 void pci_release_regions(struct pci_dev *pdev)
746 {
747 int i;
749 for (i = 0; i < 6; i++)
750 pci_release_region(pdev, i);
751 }
753 /**
754 * pci_request_regions - Reserved PCI I/O and memory resources
755 * @pdev: PCI device whose resources are to be reserved
756 * @res_name: Name to be associated with resource.
757 *
758 * Mark all PCI regions associated with PCI device @pdev as
759 * being reserved by owner @res_name. Do not access any
760 * address inside the PCI regions unless this call returns
761 * successfully.
762 *
763 * Returns 0 on success, or %EBUSY on error. A warning
764 * message is also printed on failure.
765 */
766 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
767 {
768 int i;
770 for (i = 0; i < 6; i++)
771 if(pci_request_region(pdev, i, res_name))
772 goto err_out;
773 return 0;
775 err_out:
776 while(--i >= 0)
777 pci_release_region(pdev, i);
779 return -EBUSY;
780 }
782 /**
783 * pci_set_master - enables bus-mastering for device dev
784 * @dev: the PCI device to enable
785 *
786 * Enables bus-mastering on the device and calls pcibios_set_master()
787 * to do the needed arch specific settings.
788 */
789 void
790 pci_set_master(struct pci_dev *dev)
791 {
792 u16 cmd;
794 pci_read_config_word(dev, PCI_COMMAND, &cmd);
795 if (! (cmd & PCI_COMMAND_MASTER)) {
796 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
797 cmd |= PCI_COMMAND_MASTER;
798 pci_write_config_word(dev, PCI_COMMAND, cmd);
799 }
800 dev->is_busmaster = 1;
801 pcibios_set_master(dev);
802 }
804 #ifndef HAVE_ARCH_PCI_MWI
805 /* This can be overridden by arch code. */
806 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
808 /**
809 * pci_generic_prep_mwi - helper function for pci_set_mwi
810 * @dev: the PCI device for which MWI is enabled
811 *
812 * Helper function for generic implementation of pcibios_prep_mwi
813 * function. Originally copied from drivers/net/acenic.c.
814 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
815 *
816 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
817 */
818 static int
819 pci_generic_prep_mwi(struct pci_dev *dev)
820 {
821 u8 cacheline_size;
823 if (!pci_cache_line_size)
824 return -EINVAL; /* The system doesn't support MWI. */
826 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
827 equal to or multiple of the right value. */
828 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
829 if (cacheline_size >= pci_cache_line_size &&
830 (cacheline_size % pci_cache_line_size) == 0)
831 return 0;
833 /* Write the correct value. */
834 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
835 /* Read it back. */
836 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
837 if (cacheline_size == pci_cache_line_size)
838 return 0;
840 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
841 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
843 return -EINVAL;
844 }
845 #endif /* !HAVE_ARCH_PCI_MWI */
847 /**
848 * pci_set_mwi - enables memory-write-invalidate PCI transaction
849 * @dev: the PCI device for which MWI is enabled
850 *
851 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
852 * and then calls @pcibios_set_mwi to do the needed arch specific
853 * operations or a generic mwi-prep function.
854 *
855 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
856 */
857 int
858 pci_set_mwi(struct pci_dev *dev)
859 {
860 int rc;
861 u16 cmd;
863 #ifdef HAVE_ARCH_PCI_MWI
864 rc = pcibios_prep_mwi(dev);
865 #else
866 rc = pci_generic_prep_mwi(dev);
867 #endif
869 if (rc)
870 return rc;
872 pci_read_config_word(dev, PCI_COMMAND, &cmd);
873 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
874 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
875 cmd |= PCI_COMMAND_INVALIDATE;
876 pci_write_config_word(dev, PCI_COMMAND, cmd);
877 }
879 return 0;
880 }
882 /**
883 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
884 * @dev: the PCI device to disable
885 *
886 * Disables PCI Memory-Write-Invalidate transaction on the device
887 */
888 void
889 pci_clear_mwi(struct pci_dev *dev)
890 {
891 u16 cmd;
893 pci_read_config_word(dev, PCI_COMMAND, &cmd);
894 if (cmd & PCI_COMMAND_INVALIDATE) {
895 cmd &= ~PCI_COMMAND_INVALIDATE;
896 pci_write_config_word(dev, PCI_COMMAND, cmd);
897 }
898 }
900 /**
901 * pci_intx - enables/disables PCI INTx for device dev
902 * @pdev: the PCI device to operate on
903 * @enable: boolean: whether to enable or disable PCI INTx
904 *
905 * Enables/disables PCI INTx for device dev
906 */
907 void
908 pci_intx(struct pci_dev *pdev, int enable)
909 {
910 u16 pci_command, new;
912 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
914 if (enable) {
915 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
916 } else {
917 new = pci_command | PCI_COMMAND_INTX_DISABLE;
918 }
920 if (new != pci_command) {
921 pci_write_config_word(pdev, PCI_COMMAND, new);
922 }
923 }
925 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
926 /*
927 * These can be overridden by arch-specific implementations
928 */
929 int
930 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
931 {
932 if (!pci_dma_supported(dev, mask))
933 return -EIO;
935 dev->dma_mask = mask;
937 return 0;
938 }
940 int
941 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
942 {
943 if (!pci_dma_supported(dev, mask))
944 return -EIO;
946 dev->dev.coherent_dma_mask = mask;
948 return 0;
949 }
950 #endif
952 static int __devinit pci_init(void)
953 {
954 struct pci_dev *dev = NULL;
956 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
957 pci_fixup_device(pci_fixup_final, dev);
958 }
959 return 0;
960 }
962 static int __devinit pci_setup(char *str)
963 {
964 while (str) {
965 char *k = strchr(str, ',');
966 if (k)
967 *k++ = 0;
968 if (*str && (str = pcibios_setup(str)) && *str) {
969 if (!strcmp(str, "nomsi")) {
970 pci_no_msi();
971 } else {
972 printk(KERN_ERR "PCI: Unknown option `%s'\n",
973 str);
974 }
975 }
976 str = k;
977 }
978 return 1;
979 }
981 device_initcall(pci_init);
983 __setup("pci=", pci_setup);
985 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
986 /* FIXME: Some boxes have multiple ISA bridges! */
987 struct pci_dev *isa_bridge;
988 EXPORT_SYMBOL(isa_bridge);
989 #endif
991 EXPORT_SYMBOL_GPL(pci_restore_bars);
992 EXPORT_SYMBOL(pci_enable_device_bars);
993 EXPORT_SYMBOL(pci_enable_device);
994 EXPORT_SYMBOL(pci_disable_device);
995 EXPORT_SYMBOL(pci_find_capability);
996 EXPORT_SYMBOL(pci_bus_find_capability);
997 EXPORT_SYMBOL(pci_release_regions);
998 EXPORT_SYMBOL(pci_request_regions);
999 EXPORT_SYMBOL(pci_release_region);
1000 EXPORT_SYMBOL(pci_request_region);
1001 EXPORT_SYMBOL(pci_set_master);
1002 EXPORT_SYMBOL(pci_set_mwi);
1003 EXPORT_SYMBOL(pci_clear_mwi);
1004 EXPORT_SYMBOL_GPL(pci_intx);
1005 EXPORT_SYMBOL(pci_set_dma_mask);
1006 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1007 EXPORT_SYMBOL(pci_assign_resource);
1008 EXPORT_SYMBOL(pci_find_parent_resource);
1010 EXPORT_SYMBOL(pci_set_power_state);
1011 EXPORT_SYMBOL(pci_save_state);
1012 EXPORT_SYMBOL(pci_restore_state);
1013 EXPORT_SYMBOL(pci_enable_wake);
1015 /* Quirk info */
1017 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1018 EXPORT_SYMBOL(pci_pci_problems);