ia64/linux-2.6.18-xen.hg

view sound/i2c/l3/uda1341.c @ 782:9ab1c319531f

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jan 28 13:07:23 2009 +0900 (2009-01-28)
parents 831230e53067
children
line source
1 /*
2 * Philips UDA1341 mixer device driver
3 * Copyright (c) 2002 Tomas Kasparek <tomas.kasparek@seznam.cz>
4 *
5 * Portions are Copyright (C) 2000 Lernout & Hauspie Speech Products, N.V.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License.
9 *
10 * History:
11 *
12 * 2002-03-13 Tomas Kasparek initial release - based on uda1341.c from OSS
13 * 2002-03-28 Tomas Kasparek basic mixer is working (volume, bass, treble)
14 * 2002-03-30 Tomas Kasparek proc filesystem support, complete mixer and DSP
15 * features support
16 * 2002-04-12 Tomas Kasparek proc interface update, code cleanup
17 * 2002-05-12 Tomas Kasparek another code cleanup
18 */
20 /* $Id: uda1341.c,v 1.18 2005/11/17 14:17:21 tiwai Exp $ */
22 #include <sound/driver.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/ioctl.h>
30 #include <asm/uaccess.h>
32 #include <sound/core.h>
33 #include <sound/control.h>
34 #include <sound/initval.h>
35 #include <sound/info.h>
37 #include <linux/l3/l3.h>
39 #include <sound/uda1341.h>
41 /* {{{ HW regs definition */
43 #define STAT0 0x00
44 #define STAT1 0x80
45 #define STAT_MASK 0x80
47 #define DATA0_0 0x00
48 #define DATA0_1 0x40
49 #define DATA0_2 0x80
50 #define DATA_MASK 0xc0
52 #define IS_DATA0(x) ((x) >= data0_0 && (x) <= data0_2)
53 #define IS_DATA1(x) ((x) == data1)
54 #define IS_STATUS(x) ((x) == stat0 || (x) == stat1)
55 #define IS_EXTEND(x) ((x) >= ext0 && (x) <= ext6)
57 /* }}} */
60 static const char *peak_names[] = {
61 "before",
62 "after",
63 };
65 static const char *filter_names[] = {
66 "flat",
67 "min",
68 "min",
69 "max",
70 };
72 static const char *mixer_names[] = {
73 "double differential",
74 "input channel 1 (line in)",
75 "input channel 2 (microphone)",
76 "digital mixer",
77 };
79 static const char *deemp_names[] = {
80 "none",
81 "32 kHz",
82 "44.1 kHz",
83 "48 kHz",
84 };
86 enum uda1341_regs_names {
87 stat0,
88 stat1,
89 data0_0,
90 data0_1,
91 data0_2,
92 data1,
93 ext0,
94 ext1,
95 ext2,
96 empty,
97 ext4,
98 ext5,
99 ext6,
100 uda1341_reg_last,
101 };
103 static const char *uda1341_reg_names[] = {
104 "stat 0 ",
105 "stat 1 ",
106 "data 00",
107 "data 01",
108 "data 02",
109 "data 1 ",
110 "ext 0",
111 "ext 1",
112 "ext 2",
113 "empty",
114 "ext 4",
115 "ext 5",
116 "ext 6",
117 };
119 static const int uda1341_enum_items[] = {
120 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
121 2, //peak - before/after
122 4, //deemp - none/32/44.1/48
123 0,
124 4, //filter - flat/min/min/max
125 0, 0, 0,
126 4, //mixer - differ/line/mic/mixer
127 0, 0, 0, 0, 0,
128 };
130 static const char ** uda1341_enum_names[] = {
131 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
132 peak_names, //peak - before/after
133 deemp_names, //deemp - none/32/44.1/48
134 NULL,
135 filter_names, //filter - flat/min/min/max
136 NULL, NULL, NULL,
137 mixer_names, //mixer - differ/line/mic/mixer
138 NULL, NULL, NULL, NULL, NULL,
139 };
141 typedef int uda1341_cfg[CMD_LAST];
143 struct uda1341 {
144 int (*write) (struct l3_client *uda1341, unsigned short reg, unsigned short val);
145 int (*read) (struct l3_client *uda1341, unsigned short reg);
146 unsigned char regs[uda1341_reg_last];
147 int active;
148 spinlock_t reg_lock;
149 struct snd_card *card;
150 uda1341_cfg cfg;
151 #ifdef CONFIG_PM
152 unsigned char suspend_regs[uda1341_reg_last];
153 uda1341_cfg suspend_cfg;
154 #endif
155 };
157 /* transfer 8bit integer into string with binary representation */
158 static void int2str_bin8(uint8_t val, char *buf)
159 {
160 const int size = sizeof(val) * 8;
161 int i;
163 for (i= 0; i < size; i++){
164 *(buf++) = (val >> (size - 1)) ? '1' : '0';
165 val <<= 1;
166 }
167 *buf = '\0'; //end the string with zero
168 }
170 /* {{{ HW manipulation routines */
172 static int snd_uda1341_codec_write(struct l3_client *clnt, unsigned short reg, unsigned short val)
173 {
174 struct uda1341 *uda = clnt->driver_data;
175 unsigned char buf[2] = { 0xc0, 0xe0 }; // for EXT addressing
176 int err = 0;
178 uda->regs[reg] = val;
180 if (uda->active) {
181 if (IS_DATA0(reg)) {
182 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)&val, 1);
183 } else if (IS_DATA1(reg)) {
184 err = l3_write(clnt, UDA1341_DATA1, (const unsigned char *)&val, 1);
185 } else if (IS_STATUS(reg)) {
186 err = l3_write(clnt, UDA1341_STATUS, (const unsigned char *)&val, 1);
187 } else if (IS_EXTEND(reg)) {
188 buf[0] |= (reg - ext0) & 0x7; //EXT address
189 buf[1] |= val; //EXT data
190 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)buf, 2);
191 }
192 } else
193 printk(KERN_ERR "UDA1341 codec not active!\n");
194 return err;
195 }
197 static int snd_uda1341_codec_read(struct l3_client *clnt, unsigned short reg)
198 {
199 unsigned char val;
200 int err;
202 err = l3_read(clnt, reg, &val, 1);
203 if (err == 1)
204 // use just 6bits - the rest is address of the reg
205 return val & 63;
206 return err < 0 ? err : -EIO;
207 }
209 static inline int snd_uda1341_valid_reg(struct l3_client *clnt, unsigned short reg)
210 {
211 return reg < uda1341_reg_last;
212 }
214 static int snd_uda1341_update_bits(struct l3_client *clnt, unsigned short reg,
215 unsigned short mask, unsigned short shift,
216 unsigned short value, int flush)
217 {
218 int change;
219 unsigned short old, new;
220 struct uda1341 *uda = clnt->driver_data;
222 #if 0
223 printk(KERN_DEBUG "update_bits: reg: %s mask: %d shift: %d val: %d\n",
224 uda1341_reg_names[reg], mask, shift, value);
225 #endif
227 if (!snd_uda1341_valid_reg(clnt, reg))
228 return -EINVAL;
229 spin_lock(&uda->reg_lock);
230 old = uda->regs[reg];
231 new = (old & ~(mask << shift)) | (value << shift);
232 change = old != new;
233 if (change) {
234 if (flush) uda->write(clnt, reg, new);
235 uda->regs[reg] = new;
236 }
237 spin_unlock(&uda->reg_lock);
238 return change;
239 }
241 static int snd_uda1341_cfg_write(struct l3_client *clnt, unsigned short what,
242 unsigned short value, int flush)
243 {
244 struct uda1341 *uda = clnt->driver_data;
245 int ret = 0;
246 #ifdef CONFIG_PM
247 int reg;
248 #endif
250 #if 0
251 printk(KERN_DEBUG "cfg_write what: %d value: %d\n", what, value);
252 #endif
254 uda->cfg[what] = value;
256 switch(what) {
257 case CMD_RESET:
258 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, 1, flush); // MUTE
259 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 1, flush); // RESET
260 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 0, flush); // RESTORE
261 uda->cfg[CMD_RESET]=0;
262 break;
263 case CMD_FS:
264 ret = snd_uda1341_update_bits(clnt, stat0, 3, 4, value, flush);
265 break;
266 case CMD_FORMAT:
267 ret = snd_uda1341_update_bits(clnt, stat0, 7, 1, value, flush);
268 break;
269 case CMD_OGAIN:
270 ret = snd_uda1341_update_bits(clnt, stat1, 1, 6, value, flush);
271 break;
272 case CMD_IGAIN:
273 ret = snd_uda1341_update_bits(clnt, stat1, 1, 5, value, flush);
274 break;
275 case CMD_DAC:
276 ret = snd_uda1341_update_bits(clnt, stat1, 1, 0, value, flush);
277 break;
278 case CMD_ADC:
279 ret = snd_uda1341_update_bits(clnt, stat1, 1, 1, value, flush);
280 break;
281 case CMD_VOLUME:
282 ret = snd_uda1341_update_bits(clnt, data0_0, 63, 0, value, flush);
283 break;
284 case CMD_BASS:
285 ret = snd_uda1341_update_bits(clnt, data0_1, 15, 2, value, flush);
286 break;
287 case CMD_TREBBLE:
288 ret = snd_uda1341_update_bits(clnt, data0_1, 3, 0, value, flush);
289 break;
290 case CMD_PEAK:
291 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 5, value, flush);
292 break;
293 case CMD_DEEMP:
294 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 3, value, flush);
295 break;
296 case CMD_MUTE:
297 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, value, flush);
298 break;
299 case CMD_FILTER:
300 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 0, value, flush);
301 break;
302 case CMD_CH1:
303 ret = snd_uda1341_update_bits(clnt, ext0, 31, 0, value, flush);
304 break;
305 case CMD_CH2:
306 ret = snd_uda1341_update_bits(clnt, ext1, 31, 0, value, flush);
307 break;
308 case CMD_MIC:
309 ret = snd_uda1341_update_bits(clnt, ext2, 7, 2, value, flush);
310 break;
311 case CMD_MIXER:
312 ret = snd_uda1341_update_bits(clnt, ext2, 3, 0, value, flush);
313 break;
314 case CMD_AGC:
315 ret = snd_uda1341_update_bits(clnt, ext4, 1, 4, value, flush);
316 break;
317 case CMD_IG:
318 ret = snd_uda1341_update_bits(clnt, ext4, 3, 0, value & 0x3, flush);
319 ret = snd_uda1341_update_bits(clnt, ext5, 31, 0, value >> 2, flush);
320 break;
321 case CMD_AGC_TIME:
322 ret = snd_uda1341_update_bits(clnt, ext6, 7, 2, value, flush);
323 break;
324 case CMD_AGC_LEVEL:
325 ret = snd_uda1341_update_bits(clnt, ext6, 3, 0, value, flush);
326 break;
327 #ifdef CONFIG_PM
328 case CMD_SUSPEND:
329 for (reg = stat0; reg < uda1341_reg_last; reg++)
330 uda->suspend_regs[reg] = uda->regs[reg];
331 for (reg = 0; reg < CMD_LAST; reg++)
332 uda->suspend_cfg[reg] = uda->cfg[reg];
333 break;
334 case CMD_RESUME:
335 for (reg = stat0; reg < uda1341_reg_last; reg++)
336 snd_uda1341_codec_write(clnt, reg, uda->suspend_regs[reg]);
337 for (reg = 0; reg < CMD_LAST; reg++)
338 uda->cfg[reg] = uda->suspend_cfg[reg];
339 break;
340 #endif
341 default:
342 ret = -EINVAL;
343 break;
344 }
346 if (!uda->active)
347 printk(KERN_ERR "UDA1341 codec not active!\n");
348 return ret;
349 }
351 /* }}} */
353 /* {{{ Proc interface */
354 #ifdef CONFIG_PROC_FS
356 static const char *format_names[] = {
357 "I2S-bus",
358 "LSB 16bits",
359 "LSB 18bits",
360 "LSB 20bits",
361 "MSB",
362 "in LSB 16bits/out MSB",
363 "in LSB 18bits/out MSB",
364 "in LSB 20bits/out MSB",
365 };
367 static const char *fs_names[] = {
368 "512*fs",
369 "384*fs",
370 "256*fs",
371 "Unused - bad value!",
372 };
374 static const char* bass_values[][16] = {
375 {"0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB", "0 dB",
376 "0 dB", "0 dB", "0 dB", "0 dB", "undefined", }, //flat
377 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "18 dB",
378 "18 dB", "18 dB", "18 dB", "18 dB", "undefined",}, // min
379 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "18 dB",
380 "18 dB", "18 dB", "18 dB", "18 dB", "undefined",}, // min
381 {"0 dB", "2 dB", "4 dB", "6 dB", "8 dB", "10 dB", "12 dB", "14 dB", "16 dB", "18 dB", "20 dB",
382 "22 dB", "24 dB", "24 dB", "24 dB", "undefined",}, // max
383 };
385 static const char *mic_sens_value[] = {
386 "-3 dB", "0 dB", "3 dB", "9 dB", "15 dB", "21 dB", "27 dB", "not used",
387 };
389 static const unsigned short AGC_atime[] = {
390 11, 16, 11, 16, 21, 11, 16, 21,
391 };
393 static const unsigned short AGC_dtime[] = {
394 100, 100, 200, 200, 200, 400, 400, 400,
395 };
397 static const char *AGC_level[] = {
398 "-9.0", "-11.5", "-15.0", "-17.5",
399 };
401 static const char *ig_small_value[] = {
402 "-3.0", "-2.5", "-2.0", "-1.5", "-1.0", "-0.5",
403 };
405 /*
406 * this was computed as peak_value[i] = pow((63-i)*1.42,1.013)
407 *
408 * UDA1341 datasheet on page 21: Peak value (dB) = (Peak level - 63.5)*5*log2
409 * There is an table with these values [level]=value: [3]=-90.31, [7]=-84.29
410 * [61]=-2.78, [62] = -1.48, [63] = 0.0
411 * I tried to compute it, but using but even using logarithm with base either 10 or 2
412 * i was'n able to get values in the table from the formula. So I constructed another
413 * formula (see above) to interpolate the values as good as possible. If there is some
414 * mistake, please contact me on tomas.kasparek@seznam.cz. Thanks.
415 * UDA1341TS datasheet is available at:
416 * http://www-us9.semiconductors.com/acrobat/datasheets/UDA1341TS_3.pdf
417 */
418 static const char *peak_value[] = {
419 "-INF dB", "N.A.", "N.A", "90.31 dB", "N.A.", "N.A.", "N.A.", "-84.29 dB",
420 "-82.65 dB", "-81.13 dB", "-79.61 dB", "-78.09 dB", "-76.57 dB", "-75.05 dB", "-73.53 dB",
421 "-72.01 dB", "-70.49 dB", "-68.97 dB", "-67.45 dB", "-65.93 dB", "-64.41 dB", "-62.90 dB",
422 "-61.38 dB", "-59.86 dB", "-58.35 dB", "-56.83 dB", "-55.32 dB", "-53.80 dB", "-52.29 dB",
423 "-50.78 dB", "-49.26 dB", "-47.75 dB", "-46.24 dB", "-44.73 dB", "-43.22 dB", "-41.71 dB",
424 "-40.20 dB", "-38.69 dB", "-37.19 dB", "-35.68 dB", "-34.17 dB", "-32.67 dB", "-31.17 dB",
425 "-29.66 dB", "-28.16 dB", "-26.66 dB", "-25.16 dB", "-23.66 dB", "-22.16 dB", "-20.67 dB",
426 "-19.17 dB", "-17.68 dB", "-16.19 dB", "-14.70 dB", "-13.21 dB", "-11.72 dB", "-10.24 dB",
427 "-8.76 dB", "-7.28 dB", "-5.81 dB", "-4.34 dB", "-2.88 dB", "-1.43 dB", "0.00 dB",
428 };
430 static void snd_uda1341_proc_read(struct snd_info_entry *entry,
431 struct snd_info_buffer *buffer)
432 {
433 struct l3_client *clnt = entry->private_data;
434 struct uda1341 *uda = clnt->driver_data;
435 int peak;
437 peak = snd_uda1341_codec_read(clnt, UDA1341_DATA1);
438 if (peak < 0)
439 peak = 0;
441 snd_iprintf(buffer, "%s\n\n", uda->card->longname);
443 // for information about computed values see UDA1341TS datasheet pages 15 - 21
444 snd_iprintf(buffer, "DAC power : %s\n", uda->cfg[CMD_DAC] ? "on" : "off");
445 snd_iprintf(buffer, "ADC power : %s\n", uda->cfg[CMD_ADC] ? "on" : "off");
446 snd_iprintf(buffer, "Clock frequency : %s\n", fs_names[uda->cfg[CMD_FS]]);
447 snd_iprintf(buffer, "Data format : %s\n\n", format_names[uda->cfg[CMD_FORMAT]]);
449 snd_iprintf(buffer, "Filter mode : %s\n", filter_names[uda->cfg[CMD_FILTER]]);
450 snd_iprintf(buffer, "Mixer mode : %s\n", mixer_names[uda->cfg[CMD_MIXER]]);
451 snd_iprintf(buffer, "De-emphasis : %s\n", deemp_names[uda->cfg[CMD_DEEMP]]);
452 snd_iprintf(buffer, "Peak detection pos. : %s\n", uda->cfg[CMD_PEAK] ? "after" : "before");
453 snd_iprintf(buffer, "Peak value : %s\n\n", peak_value[peak]);
455 snd_iprintf(buffer, "Automatic Gain Ctrl : %s\n", uda->cfg[CMD_AGC] ? "on" : "off");
456 snd_iprintf(buffer, "AGC attack time : %d ms\n", AGC_atime[uda->cfg[CMD_AGC_TIME]]);
457 snd_iprintf(buffer, "AGC decay time : %d ms\n", AGC_dtime[uda->cfg[CMD_AGC_TIME]]);
458 snd_iprintf(buffer, "AGC output level : %s dB\n\n", AGC_level[uda->cfg[CMD_AGC_LEVEL]]);
460 snd_iprintf(buffer, "Mute : %s\n", uda->cfg[CMD_MUTE] ? "on" : "off");
462 if (uda->cfg[CMD_VOLUME] == 0)
463 snd_iprintf(buffer, "Volume : 0 dB\n");
464 else if (uda->cfg[CMD_VOLUME] < 62)
465 snd_iprintf(buffer, "Volume : %d dB\n", -1*uda->cfg[CMD_VOLUME] +1);
466 else
467 snd_iprintf(buffer, "Volume : -INF dB\n");
468 snd_iprintf(buffer, "Bass : %s\n", bass_values[uda->cfg[CMD_FILTER]][uda->cfg[CMD_BASS]]);
469 snd_iprintf(buffer, "Trebble : %d dB\n", uda->cfg[CMD_FILTER] ? 2*uda->cfg[CMD_TREBBLE] : 0);
470 snd_iprintf(buffer, "Input Gain (6dB) : %s\n", uda->cfg[CMD_IGAIN] ? "on" : "off");
471 snd_iprintf(buffer, "Output Gain (6dB) : %s\n", uda->cfg[CMD_OGAIN] ? "on" : "off");
472 snd_iprintf(buffer, "Mic sensitivity : %s\n", mic_sens_value[uda->cfg[CMD_MIC]]);
475 if(uda->cfg[CMD_CH1] < 31)
476 snd_iprintf(buffer, "Mixer gain channel 1: -%d.%c dB\n",
477 ((uda->cfg[CMD_CH1] >> 1) * 3) + (uda->cfg[CMD_CH1] & 1),
478 uda->cfg[CMD_CH1] & 1 ? '5' : '0');
479 else
480 snd_iprintf(buffer, "Mixer gain channel 1: -INF dB\n");
481 if(uda->cfg[CMD_CH2] < 31)
482 snd_iprintf(buffer, "Mixer gain channel 2: -%d.%c dB\n",
483 ((uda->cfg[CMD_CH2] >> 1) * 3) + (uda->cfg[CMD_CH2] & 1),
484 uda->cfg[CMD_CH2] & 1 ? '5' : '0');
485 else
486 snd_iprintf(buffer, "Mixer gain channel 2: -INF dB\n");
488 if(uda->cfg[CMD_IG] > 5)
489 snd_iprintf(buffer, "Input Amp. Gain ch 2: %d.%c dB\n",
490 (uda->cfg[CMD_IG] >> 1) -3, uda->cfg[CMD_IG] & 1 ? '5' : '0');
491 else
492 snd_iprintf(buffer, "Input Amp. Gain ch 2: %s dB\n", ig_small_value[uda->cfg[CMD_IG]]);
493 }
495 static void snd_uda1341_proc_regs_read(struct snd_info_entry *entry,
496 struct snd_info_buffer *buffer)
497 {
498 struct l3_client *clnt = entry->private_data;
499 struct uda1341 *uda = clnt->driver_data;
500 int reg;
501 char buf[12];
503 for (reg = 0; reg < uda1341_reg_last; reg ++) {
504 if (reg == empty)
505 continue;
506 int2str_bin8(uda->regs[reg], buf);
507 snd_iprintf(buffer, "%s = %s\n", uda1341_reg_names[reg], buf);
508 }
510 int2str_bin8(snd_uda1341_codec_read(clnt, UDA1341_DATA1), buf);
511 snd_iprintf(buffer, "DATA1 = %s\n", buf);
512 }
513 #endif /* CONFIG_PROC_FS */
515 static void __devinit snd_uda1341_proc_init(struct snd_card *card, struct l3_client *clnt)
516 {
517 struct snd_info_entry *entry;
519 if (! snd_card_proc_new(card, "uda1341", &entry))
520 snd_info_set_text_ops(entry, clnt, snd_uda1341_proc_read);
521 if (! snd_card_proc_new(card, "uda1341-regs", &entry))
522 snd_info_set_text_ops(entry, clnt, snd_uda1341_proc_regs_read);
523 }
525 /* }}} */
527 /* {{{ Mixer controls setting */
529 /* {{{ UDA1341 single functions */
531 #define UDA1341_SINGLE(xname, where, reg, shift, mask, invert) \
532 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_single, \
533 .get = snd_uda1341_get_single, .put = snd_uda1341_put_single, \
534 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
535 }
537 static int snd_uda1341_info_single(struct snd_kcontrol *kcontrol,
538 struct snd_ctl_elem_info *uinfo)
539 {
540 int mask = (kcontrol->private_value >> 12) & 63;
542 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
543 uinfo->count = 1;
544 uinfo->value.integer.min = 0;
545 uinfo->value.integer.max = mask;
546 return 0;
547 }
549 static int snd_uda1341_get_single(struct snd_kcontrol *kcontrol,
550 struct snd_ctl_elem_value *ucontrol)
551 {
552 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
553 struct uda1341 *uda = clnt->driver_data;
554 int where = kcontrol->private_value & 31;
555 int mask = (kcontrol->private_value >> 12) & 63;
556 int invert = (kcontrol->private_value >> 18) & 1;
558 ucontrol->value.integer.value[0] = uda->cfg[where];
559 if (invert)
560 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
562 return 0;
563 }
565 static int snd_uda1341_put_single(struct snd_kcontrol *kcontrol,
566 struct snd_ctl_elem_value *ucontrol)
567 {
568 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
569 struct uda1341 *uda = clnt->driver_data;
570 int where = kcontrol->private_value & 31;
571 int reg = (kcontrol->private_value >> 5) & 15;
572 int shift = (kcontrol->private_value >> 9) & 7;
573 int mask = (kcontrol->private_value >> 12) & 63;
574 int invert = (kcontrol->private_value >> 18) & 1;
575 unsigned short val;
577 val = (ucontrol->value.integer.value[0] & mask);
578 if (invert)
579 val = mask - val;
581 uda->cfg[where] = val;
582 return snd_uda1341_update_bits(clnt, reg, mask, shift, val, FLUSH);
583 }
585 /* }}} */
587 /* {{{ UDA1341 enum functions */
589 #define UDA1341_ENUM(xname, where, reg, shift, mask, invert) \
590 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_enum, \
591 .get = snd_uda1341_get_enum, .put = snd_uda1341_put_enum, \
592 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
593 }
595 static int snd_uda1341_info_enum(struct snd_kcontrol *kcontrol,
596 struct snd_ctl_elem_info *uinfo)
597 {
598 int where = kcontrol->private_value & 31;
599 const char **texts;
601 // this register we don't handle this way
602 if (!uda1341_enum_items[where])
603 return -EINVAL;
605 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
606 uinfo->count = 1;
607 uinfo->value.enumerated.items = uda1341_enum_items[where];
609 if (uinfo->value.enumerated.item >= uda1341_enum_items[where])
610 uinfo->value.enumerated.item = uda1341_enum_items[where] - 1;
612 texts = uda1341_enum_names[where];
613 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
614 return 0;
615 }
617 static int snd_uda1341_get_enum(struct snd_kcontrol *kcontrol,
618 struct snd_ctl_elem_value *ucontrol)
619 {
620 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
621 struct uda1341 *uda = clnt->driver_data;
622 int where = kcontrol->private_value & 31;
624 ucontrol->value.enumerated.item[0] = uda->cfg[where];
625 return 0;
626 }
628 static int snd_uda1341_put_enum(struct snd_kcontrol *kcontrol,
629 struct snd_ctl_elem_value *ucontrol)
630 {
631 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
632 struct uda1341 *uda = clnt->driver_data;
633 int where = kcontrol->private_value & 31;
634 int reg = (kcontrol->private_value >> 5) & 15;
635 int shift = (kcontrol->private_value >> 9) & 7;
636 int mask = (kcontrol->private_value >> 12) & 63;
638 uda->cfg[where] = (ucontrol->value.enumerated.item[0] & mask);
640 return snd_uda1341_update_bits(clnt, reg, mask, shift, uda->cfg[where], FLUSH);
641 }
643 /* }}} */
645 /* {{{ UDA1341 2regs functions */
647 #define UDA1341_2REGS(xname, where, reg_1, reg_2, shift_1, shift_2, mask_1, mask_2, invert) \
648 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .info = snd_uda1341_info_2regs, \
649 .get = snd_uda1341_get_2regs, .put = snd_uda1341_put_2regs, \
650 .private_value = where | (reg_1 << 5) | (reg_2 << 9) | (shift_1 << 13) | (shift_2 << 16) | \
651 (mask_1 << 19) | (mask_2 << 25) | (invert << 31) \
652 }
655 static int snd_uda1341_info_2regs(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_info *uinfo)
657 {
658 int mask_1 = (kcontrol->private_value >> 19) & 63;
659 int mask_2 = (kcontrol->private_value >> 25) & 63;
660 int mask;
662 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
663 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
664 uinfo->count = 1;
665 uinfo->value.integer.min = 0;
666 uinfo->value.integer.max = mask;
667 return 0;
668 }
670 static int snd_uda1341_get_2regs(struct snd_kcontrol *kcontrol,
671 struct snd_ctl_elem_value *ucontrol)
672 {
673 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
674 struct uda1341 *uda = clnt->driver_data;
675 int where = kcontrol->private_value & 31;
676 int mask_1 = (kcontrol->private_value >> 19) & 63;
677 int mask_2 = (kcontrol->private_value >> 25) & 63;
678 int invert = (kcontrol->private_value >> 31) & 1;
679 int mask;
681 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
683 ucontrol->value.integer.value[0] = uda->cfg[where];
684 if (invert)
685 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
686 return 0;
687 }
689 static int snd_uda1341_put_2regs(struct snd_kcontrol *kcontrol,
690 struct snd_ctl_elem_value *ucontrol)
691 {
692 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
693 struct uda1341 *uda = clnt->driver_data;
694 int where = kcontrol->private_value & 31;
695 int reg_1 = (kcontrol->private_value >> 5) & 15;
696 int reg_2 = (kcontrol->private_value >> 9) & 15;
697 int shift_1 = (kcontrol->private_value >> 13) & 7;
698 int shift_2 = (kcontrol->private_value >> 16) & 7;
699 int mask_1 = (kcontrol->private_value >> 19) & 63;
700 int mask_2 = (kcontrol->private_value >> 25) & 63;
701 int invert = (kcontrol->private_value >> 31) & 1;
702 int mask;
703 unsigned short val1, val2, val;
705 val = ucontrol->value.integer.value[0];
707 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
709 val1 = val & mask_1;
710 val2 = (val / (mask_1 + 1)) & mask_2;
712 if (invert) {
713 val1 = mask_1 - val1;
714 val2 = mask_2 - val2;
715 }
717 uda->cfg[where] = invert ? mask - val : val;
719 //FIXME - return value
720 snd_uda1341_update_bits(clnt, reg_1, mask_1, shift_1, val1, FLUSH);
721 return snd_uda1341_update_bits(clnt, reg_2, mask_2, shift_2, val2, FLUSH);
722 }
724 /* }}} */
726 static struct snd_kcontrol_new snd_uda1341_controls[] = {
727 UDA1341_SINGLE("Master Playback Switch", CMD_MUTE, data0_2, 2, 1, 1),
728 UDA1341_SINGLE("Master Playback Volume", CMD_VOLUME, data0_0, 0, 63, 1),
730 UDA1341_SINGLE("Bass Playback Volume", CMD_BASS, data0_1, 2, 15, 0),
731 UDA1341_SINGLE("Treble Playback Volume", CMD_TREBBLE, data0_1, 0, 3, 0),
733 UDA1341_SINGLE("Input Gain Switch", CMD_IGAIN, stat1, 5, 1, 0),
734 UDA1341_SINGLE("Output Gain Switch", CMD_OGAIN, stat1, 6, 1, 0),
736 UDA1341_SINGLE("Mixer Gain Channel 1 Volume", CMD_CH1, ext0, 0, 31, 1),
737 UDA1341_SINGLE("Mixer Gain Channel 2 Volume", CMD_CH2, ext1, 0, 31, 1),
739 UDA1341_SINGLE("Mic Sensitivity Volume", CMD_MIC, ext2, 2, 7, 0),
741 UDA1341_SINGLE("AGC Output Level", CMD_AGC_LEVEL, ext6, 0, 3, 0),
742 UDA1341_SINGLE("AGC Time Constant", CMD_AGC_TIME, ext6, 2, 7, 0),
743 UDA1341_SINGLE("AGC Time Constant Switch", CMD_AGC, ext4, 4, 1, 0),
745 UDA1341_SINGLE("DAC Power", CMD_DAC, stat1, 0, 1, 0),
746 UDA1341_SINGLE("ADC Power", CMD_ADC, stat1, 1, 1, 0),
748 UDA1341_ENUM("Peak detection", CMD_PEAK, data0_2, 5, 1, 0),
749 UDA1341_ENUM("De-emphasis", CMD_DEEMP, data0_2, 3, 3, 0),
750 UDA1341_ENUM("Mixer mode", CMD_MIXER, ext2, 0, 3, 0),
751 UDA1341_ENUM("Filter mode", CMD_FILTER, data0_2, 0, 3, 0),
753 UDA1341_2REGS("Gain Input Amplifier Gain (channel 2)", CMD_IG, ext4, ext5, 0, 0, 3, 31, 0),
754 };
756 static void uda1341_free(struct l3_client *clnt)
757 {
758 l3_detach_client(clnt); // calls kfree for driver_data (struct uda1341)
759 kfree(clnt);
760 }
762 static int uda1341_dev_free(struct snd_device *device)
763 {
764 struct l3_client *clnt = device->device_data;
765 uda1341_free(clnt);
766 return 0;
767 }
769 int __init snd_chip_uda1341_mixer_new(struct snd_card *card, struct l3_client **clntp)
770 {
771 static struct snd_device_ops ops = {
772 .dev_free = uda1341_dev_free,
773 };
774 struct l3_client *clnt;
775 int idx, err;
777 snd_assert(card != NULL, return -EINVAL);
779 clnt = kzalloc(sizeof(*clnt), GFP_KERNEL);
780 if (clnt == NULL)
781 return -ENOMEM;
783 if ((err = l3_attach_client(clnt, "l3-bit-sa1100-gpio", UDA1341_ALSA_NAME))) {
784 kfree(clnt);
785 return err;
786 }
788 for (idx = 0; idx < ARRAY_SIZE(snd_uda1341_controls); idx++) {
789 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_uda1341_controls[idx], clnt))) < 0) {
790 uda1341_free(clnt);
791 return err;
792 }
793 }
795 if ((err = snd_device_new(card, SNDRV_DEV_CODEC, clnt, &ops)) < 0) {
796 uda1341_free(clnt);
797 return err;
798 }
800 *clntp = clnt;
801 strcpy(card->mixername, "UDA1341TS Mixer");
802 ((struct uda1341 *)clnt->driver_data)->card = card;
804 snd_uda1341_proc_init(card, clnt);
806 return 0;
807 }
809 /* }}} */
811 /* {{{ L3 operations */
813 static int uda1341_attach(struct l3_client *clnt)
814 {
815 struct uda1341 *uda;
817 uda = kzalloc(sizeof(*uda), 0, GFP_KERNEL);
818 if (!uda)
819 return -ENOMEM;
821 /* init fixed parts of my copy of registers */
822 uda->regs[stat0] = STAT0;
823 uda->regs[stat1] = STAT1;
825 uda->regs[data0_0] = DATA0_0;
826 uda->regs[data0_1] = DATA0_1;
827 uda->regs[data0_2] = DATA0_2;
829 uda->write = snd_uda1341_codec_write;
830 uda->read = snd_uda1341_codec_read;
832 spin_lock_init(&uda->reg_lock);
834 clnt->driver_data = uda;
835 return 0;
836 }
838 static void uda1341_detach(struct l3_client *clnt)
839 {
840 kfree(clnt->driver_data);
841 }
843 static int
844 uda1341_command(struct l3_client *clnt, int cmd, void *arg)
845 {
846 if (cmd != CMD_READ_REG)
847 return snd_uda1341_cfg_write(clnt, cmd, (int) arg, FLUSH);
849 return snd_uda1341_codec_read(clnt, (int) arg);
850 }
852 static int uda1341_open(struct l3_client *clnt)
853 {
854 struct uda1341 *uda = clnt->driver_data;
856 uda->active = 1;
858 /* init default configuration */
859 snd_uda1341_cfg_write(clnt, CMD_RESET, 0, REGS_ONLY);
860 snd_uda1341_cfg_write(clnt, CMD_FS, F256, FLUSH); // unknown state after reset
861 snd_uda1341_cfg_write(clnt, CMD_FORMAT, LSB16, FLUSH); // unknown state after reset
862 snd_uda1341_cfg_write(clnt, CMD_OGAIN, ON, FLUSH); // default off after reset
863 snd_uda1341_cfg_write(clnt, CMD_IGAIN, ON, FLUSH); // default off after reset
864 snd_uda1341_cfg_write(clnt, CMD_DAC, ON, FLUSH); // ??? default value after reset
865 snd_uda1341_cfg_write(clnt, CMD_ADC, ON, FLUSH); // ??? default value after reset
866 snd_uda1341_cfg_write(clnt, CMD_VOLUME, 20, FLUSH); // default 0dB after reset
867 snd_uda1341_cfg_write(clnt, CMD_BASS, 0, REGS_ONLY); // default value after reset
868 snd_uda1341_cfg_write(clnt, CMD_TREBBLE, 0, REGS_ONLY); // default value after reset
869 snd_uda1341_cfg_write(clnt, CMD_PEAK, AFTER, REGS_ONLY);// default value after reset
870 snd_uda1341_cfg_write(clnt, CMD_DEEMP, NONE, REGS_ONLY);// default value after reset
871 //at this moment should be QMUTED by h3600_audio_init
872 snd_uda1341_cfg_write(clnt, CMD_MUTE, OFF, REGS_ONLY); // default value after reset
873 snd_uda1341_cfg_write(clnt, CMD_FILTER, MAX, FLUSH); // defaul flat after reset
874 snd_uda1341_cfg_write(clnt, CMD_CH1, 31, FLUSH); // default value after reset
875 snd_uda1341_cfg_write(clnt, CMD_CH2, 4, FLUSH); // default value after reset
876 snd_uda1341_cfg_write(clnt, CMD_MIC, 4, FLUSH); // default 0dB after reset
877 snd_uda1341_cfg_write(clnt, CMD_MIXER, MIXER, FLUSH); // default doub.dif.mode
878 snd_uda1341_cfg_write(clnt, CMD_AGC, OFF, FLUSH); // default value after reset
879 snd_uda1341_cfg_write(clnt, CMD_IG, 0, FLUSH); // unknown state after reset
880 snd_uda1341_cfg_write(clnt, CMD_AGC_TIME, 0, FLUSH); // default value after reset
881 snd_uda1341_cfg_write(clnt, CMD_AGC_LEVEL, 0, FLUSH); // default value after reset
883 return 0;
884 }
886 static void uda1341_close(struct l3_client *clnt)
887 {
888 struct uda1341 *uda = clnt->driver_data;
890 uda->active = 0;
891 }
893 /* }}} */
895 /* {{{ Module and L3 initialization */
897 static struct l3_ops uda1341_ops = {
898 .open = uda1341_open,
899 .command = uda1341_command,
900 .close = uda1341_close,
901 };
903 static struct l3_driver uda1341_driver = {
904 .name = UDA1341_ALSA_NAME,
905 .attach_client = uda1341_attach,
906 .detach_client = uda1341_detach,
907 .ops = &uda1341_ops,
908 .owner = THIS_MODULE,
909 };
911 static int __init uda1341_init(void)
912 {
913 return l3_add_driver(&uda1341_driver);
914 }
916 static void __exit uda1341_exit(void)
917 {
918 l3_del_driver(&uda1341_driver);
919 }
921 module_init(uda1341_init);
922 module_exit(uda1341_exit);
924 MODULE_AUTHOR("Tomas Kasparek <tomas.kasparek@seznam.cz>");
925 MODULE_LICENSE("GPL");
926 MODULE_DESCRIPTION("Philips UDA1341 CODEC driver for ALSA");
927 MODULE_SUPPORTED_DEVICE("{{UDA1341,UDA1341TS}}");
929 EXPORT_SYMBOL(snd_chip_uda1341_mixer_new);
931 /* }}} */
933 /*
934 * Local variables:
935 * indent-tabs-mode: t
936 * End:
937 */