ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-iop3xx/iop331.h @ 782:9ab1c319531f

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jan 28 13:07:23 2009 +0900 (2009-01-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm/arch-iop3xx/iop331.h
3 *
4 * Intel IOP331 Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
14 #ifndef _IOP331_HW_H_
15 #define _IOP331_HW_H_
18 /*
19 * This is needed for mixed drivers that need to work on all
20 * IOP3xx variants but behave slightly differently on each.
21 */
22 #ifndef __ASSEMBLY__
23 #ifdef CONFIG_ARCH_IOP331
24 /*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */
25 #define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010)
26 #else
27 #define iop_is_331() 0
28 #endif
29 #endif
31 /*
32 * IOP331 I/O and Mem space regions for PCI autoconfiguration
33 */
34 #define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
35 #define IOP331_PCI_LOWER_IO_PA 0x90000000
36 #define IOP331_PCI_LOWER_IO_VA 0xfe000000
37 #define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
38 #define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
39 #define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
40 #define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
41 #define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
43 /* this can be 128M if OMWTVR1 is set */
44 #define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45 /* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
46 #define IOP331_PCI_LOWER_MEM_PA 0x80000000
47 #define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
48 #define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
49 #define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
50 #define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
52 /*
53 * IOP331 chipset registers
54 */
55 #define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56 #define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57 #define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
59 /* Reserved 0x00000000 through 0x000000FF */
61 /* Address Translation Unit 0x00000100 through 0x000001FF */
62 #define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
63 #define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
64 #define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
65 #define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
66 #define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
67 #define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
68 #define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
69 #define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
70 #define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
71 #define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
72 #define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
73 #define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
74 #define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
75 #define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
76 #define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
77 #define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
78 #define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
79 #define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
80 #define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
81 #define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
82 /* Reserved 0x00000138 through 0x0000013B */
83 #define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
84 #define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
85 #define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
86 #define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
87 #define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
88 #define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
89 #define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
90 #define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
91 #define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
92 #define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
93 #define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
94 #define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
95 #define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
96 #define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
97 #define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
98 #define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
99 /* Reserved 0x00000170 through 0x00000177*/
100 #define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
101 /* Reserved 0x0000017C through 0x0000017F*/
102 #define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
103 #define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
104 #define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
105 #define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
106 #define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
107 #define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
108 #define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
109 #define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
110 /* Reserved 0x000001A0 through 0x000001A3*/
111 #define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
112 /* Reserved 0x000001A8 through 0x000001AB*/
113 #define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
114 /* Reserved 0x000001B0 through 0x000001BB*/
115 #define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
116 #define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
117 #define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
118 #define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
119 #define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
120 #define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
121 #define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
122 #define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
123 /* Reserved 0x000001C6 through 0x000001CF */
124 #define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
125 #define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
126 #define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
127 #define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
128 #define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
129 #define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
130 #define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
131 #define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
132 #define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
133 #define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
134 #define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
136 /* Messaging Unit 0x00000300 through 0x000003FF */
138 /* Reserved 0x00000300 through 0x0000030c */
139 #define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
140 #define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
141 #define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
142 #define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
143 #define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
144 #define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
145 #define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
146 #define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
147 #define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
148 #define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
149 /* Reserved 0x00000338 through 0x0000034F */
150 #define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
151 #define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
152 /* Reserved 0x00000358 through 0x0000035C */
153 #define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
154 #define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
155 #define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
156 #define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
157 #define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
158 #define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
159 #define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
160 #define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
161 #define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
162 /* Reserved 0x00000384 through 0x000003FF */
164 /* DMA Controller 0x00000400 through 0x000004FF */
165 #define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
166 #define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
167 #define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
168 #define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
169 #define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
170 #define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
171 #define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
172 #define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
173 #define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
174 /* Reserved 0x00000428 through 0x0000043C */
175 #define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
176 #define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
177 #define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
178 #define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
179 #define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
180 #define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
181 #define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
182 #define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
183 #define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
184 /* Reserved 0x00000468 through 0x000004FF */
186 /* Memory controller 0x00000500 through 0x0005FF */
188 /* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189 #define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
190 #define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
191 #define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
192 #define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
193 #define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
194 #define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
195 #define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
196 #define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
197 #define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
198 #define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
199 #define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
200 #define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
201 #define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
202 #define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
203 #define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
204 /* Reserved 0x000006BC */
205 #define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
206 /* Reserved 0x000006C4 through 0x000006DC */
207 #define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
208 #define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
210 #define IOP331_PBCR_EN 0x1
212 #define IOP331_PBISR_BOOR_ERR 0x1
216 /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
217 /* Internal arbitration unit 0x00000780 through 0x0007BF */
219 /* Interrupt Controller */
220 #define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
221 #define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
222 #define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
223 #define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
224 #define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
225 #define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
226 #define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
227 #define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
228 #define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
229 #define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
230 #define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
231 #define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
232 #define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
233 #define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
234 #define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
235 #define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
238 /* Timers */
240 #define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
241 #define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
243 #define IOP331_TMR_TC 0x01
244 #define IOP331_TMR_EN 0x02
245 #define IOP331_TMR_RELOAD 0x04
246 #define IOP331_TMR_PRIVILEGED 0x09
248 #define IOP331_TMR_RATIO_1_1 0x00
249 #define IOP331_TMR_RATIO_4_1 0x10
250 #define IOP331_TMR_RATIO_8_1 0x20
251 #define IOP331_TMR_RATIO_16_1 0x30
253 #define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
254 #define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
255 #define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
256 #define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
257 #define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
258 #define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
260 #if defined(CONFIG_ARCH_IOP331)
261 #define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
262 #endif
264 #if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
265 #undef IOP331_TICK_RATE
266 #define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
267 #endif
269 /* Application accelerator unit 0x00000800 - 0x000008FF */
270 #define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
271 #define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
272 #define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
273 #define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
274 #define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
275 #define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
276 #define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
277 #define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
278 #define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
279 #define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
280 #define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
281 #define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
282 #define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
283 #define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
284 #define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
285 #define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
286 #define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
287 #define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
288 #define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
289 #define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
290 #define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
291 #define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
292 #define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
293 #define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
294 #define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
295 #define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
296 #define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
297 #define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
298 #define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
299 #define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
300 #define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
301 #define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
302 #define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
303 #define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
304 #define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
305 #define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
306 #define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
307 #define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
308 #define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
309 #define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
310 #define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
311 #define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
314 #define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
315 #define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
316 /* SSP serial port unit 0x00001600 - 0x0000167F */
318 /* I2C bus interface unit 0x00001680 - 0x000016FF */
319 /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
321 #define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680)
322 #define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684)
323 #define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688)
324 #define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
325 /* Reserved 0x00001690 */
326 #define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694)
327 /* Reserved 0x00001698 */
328 /* Reserved 0x0000169C */
329 #define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
330 #define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
331 #define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
332 #define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
333 #define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
334 /* Reserved 0x000016B8 through 0x000016FF */
336 /* 0x00001700 through 0x0000172C UART 0 */
338 /* Reserved 0x00001730 through 0x0000173F */
340 /* 0x00001740 through 0x0000176C UART 1 */
342 #define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
343 #define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
344 #define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
345 #define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
347 /* Reserved 0x00001770 through 0x0000177F */
349 /* General Purpose I/O Registers */
350 #define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
351 #define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
352 #define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
354 /* Reserved 0x0000178c through 0x000019ff */
357 #ifndef __ASSEMBLY__
358 extern void iop331_map_io(void);
359 extern void iop331_init_irq(void);
360 extern void iop331_time_init(void);
361 #endif
363 #endif // _IOP331_HW_H_