ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-iop3xx/iop321.h @ 782:9ab1c319531f

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jan 28 13:07:23 2009 +0900 (2009-01-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm/arch-iop3xx/iop321.h
3 *
4 * Intel IOP321 Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
15 #ifndef _IOP321_HW_H_
16 #define _IOP321_HW_H_
19 /*
20 * This is needed for mixed drivers that need to work on all
21 * IOP3xx variants but behave slightly differently on each.
22 */
23 #ifndef __ASSEMBLY__
24 #ifdef CONFIG_ARCH_IOP321
25 #define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
26 #else
27 #define iop_is_321() 0
28 #endif
29 #endif
31 /*
32 * IOP321 I/O and Mem space regions for PCI autoconfiguration
33 */
34 #define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
35 #define IOP321_PCI_LOWER_IO_PA 0x90000000
36 #define IOP321_PCI_LOWER_IO_VA 0xfe000000
37 #define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
38 #define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
39 #define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
40 #define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
41 #define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
43 /* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
44 #define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45 #define IOP321_PCI_LOWER_MEM_PA 0x80000000
46 #define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
47 #define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
48 #define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
49 #define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
52 /*
53 * IOP321 chipset registers
54 */
55 #define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56 #define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57 #define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
59 /* Reserved 0x00000000 through 0x000000FF */
61 /* Address Translation Unit 0x00000100 through 0x000001FF */
62 #define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
63 #define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
64 #define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
65 #define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
66 #define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
67 #define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
68 #define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
69 #define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
70 #define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
71 #define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
72 #define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
73 #define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
74 #define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
75 #define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
76 #define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
77 #define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
78 #define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
79 #define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
80 #define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
81 /* Reserved 0x00000134 through 0x0000013B */
82 #define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
83 #define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
84 #define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
85 #define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
86 #define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
87 #define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
88 #define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
89 #define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
90 #define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
91 #define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
92 #define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
93 #define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
94 #define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
95 #define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
96 #define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
97 #define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
98 /* Reserved 0x00000170 through 0x00000177*/
99 #define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
100 /* Reserved 0x0000017C through 0x0000017F*/
101 #define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
102 #define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
103 #define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
104 #define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
105 #define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
106 #define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
107 #define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
108 #define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
109 /* Reserved 0x000001A0 through 0x000001A3*/
110 #define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
111 /* Reserved 0x000001A8 through 0x000001AB*/
112 #define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
113 /* Reserved 0x000001B0 through 0x000001BB*/
114 #define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
115 #define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
116 #define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
117 #define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
118 #define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
119 /* Reserved 0x000001C6 through 0x000001DF */
120 #define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
121 #define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
122 #define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
123 #define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
124 #define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
126 /* Messaging Unit 0x00000300 through 0x000003FF */
128 /* Reserved 0x00000300 through 0x0000030c */
129 #define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
130 #define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
131 #define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
132 #define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
133 #define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
134 #define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
135 #define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
136 #define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
137 #define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
138 #define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
139 /* Reserved 0x00000338 through 0x0000034F */
140 #define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
141 #define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
142 /* Reserved 0x00000358 through 0x0000035C */
143 #define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
144 #define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
145 #define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
146 #define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
147 #define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
148 #define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
149 #define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
150 #define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
151 #define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
153 #define IOP321_IIxR_MASK 0x7f /* masks all */
154 #define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
155 #define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
156 #define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
157 #define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
158 #define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
159 #define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
160 #define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
162 /* Reserved 0x00000384 through 0x000003FF */
164 /* DMA Controller 0x00000400 through 0x000004FF */
165 #define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
166 #define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
167 #define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
168 #define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
169 #define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
170 #define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
171 #define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
172 #define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
173 #define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
174 /* Reserved 0x00000428 through 0x0000043C */
175 #define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
176 #define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
177 #define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
178 #define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
179 #define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
180 #define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
181 #define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
182 #define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
183 #define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
184 /* Reserved 0x00000468 through 0x000004FF */
186 /* Memory controller 0x00000500 through 0x0005FF */
188 /* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189 #define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
190 #define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
191 #define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
192 #define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
193 #define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
194 #define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
195 #define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
196 #define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
197 #define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
198 #define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
199 #define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
200 #define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
201 #define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
202 #define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
203 #define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
204 /* Reserved 0x000006BC */
205 #define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
206 /* Reserved 0x000006C4 through 0x000006DC */
207 #define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
208 #define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
210 #define IOP321_PBCR_EN 0x1
212 #define IOP321_PBISR_BOOR_ERR 0x1
214 /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
215 #define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
216 #define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
217 #define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
218 /* reserved 0x00000070c */
219 #define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
220 /* PERC0 DOESN'T EXIST - index from 1! */
221 #define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
223 #define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
225 /* Internal arbitration unit 0x00000780 through 0x0007BF */
226 #define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
227 #define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
228 #define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
230 /* General Purpose I/O Registers */
231 #define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
232 #define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
233 #define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
235 /* Interrupt Controller */
236 #define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
237 #define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
238 #define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
239 #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
241 /* Timers */
243 #define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
244 #define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
246 #ifdef CONFIG_ARCH_IQ80321
247 #define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
248 #elif defined(CONFIG_ARCH_IQ31244)
249 #define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
250 #endif
252 #ifdef CONFIG_ARCH_EP80219
253 #undef IOP321_TICK_RATE
254 #define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
255 #endif
257 #define IOP321_TMR_TC 0x01
258 #define IOP321_TMR_EN 0x02
259 #define IOP321_TMR_RELOAD 0x04
260 #define IOP321_TMR_PRIVILEGED 0x09
262 #define IOP321_TMR_RATIO_1_1 0x00
263 #define IOP321_TMR_RATIO_4_1 0x10
264 #define IOP321_TMR_RATIO_8_1 0x20
265 #define IOP321_TMR_RATIO_16_1 0x30
267 #define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
268 #define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
269 #define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
270 #define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
271 #define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
272 #define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
274 /* Application accelerator unit 0x00000800 - 0x000008FF */
275 #define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
276 #define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
277 #define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
278 #define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
279 #define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
280 #define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
281 #define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
282 #define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
283 #define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
284 #define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
285 #define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
286 #define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
287 #define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
288 #define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
289 #define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
290 #define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
291 #define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
292 #define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
293 #define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
294 #define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
295 #define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
296 #define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
297 #define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
298 #define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
299 #define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
300 #define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
301 #define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
302 #define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
303 #define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
304 #define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
305 #define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
306 #define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
307 #define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
308 #define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
309 #define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
310 #define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
311 #define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
312 #define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
313 #define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
314 #define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
315 #define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
316 #define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
319 /* SSP serial port unit 0x00001600 - 0x0000167F */
320 /* I2C bus interface unit 0x00001680 - 0x000016FF */
321 #define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680)
322 #define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684)
323 #define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688)
324 #define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
325 /* Reserved 0x00001690 */
326 #define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694)
327 /* Reserved 0x00001698 */
328 /* Reserved 0x0000169C */
329 #define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
330 #define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
331 #define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
332 #define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
333 #define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
334 /* Reserved 0x000016B8 through 0x000016FC */
336 /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
339 #ifndef __ASSEMBLY__
340 extern void iop321_map_io(void);
341 extern void iop321_init_irq(void);
342 extern void iop321_time_init(void);
343 #endif
345 #endif // _IOP321_HW_H_