ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-at91rm9200/at91rm9200_sys.h @ 782:9ab1c319531f

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jan 28 13:07:23 2009 +0900 (2009-01-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
16 #ifndef AT91RM9200_SYS_H
17 #define AT91RM9200_SYS_H
19 /*
20 * Advanced Interrupt Controller.
21 */
22 #define AT91_AIC 0x000
24 #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
25 #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
26 #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
27 #define AT91_AIC_SRCTYPE_LOW (0 << 5)
28 #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
29 #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
30 #define AT91_AIC_SRCTYPE_RISING (3 << 5)
32 #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
33 #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
34 #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
35 #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
36 #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
38 #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
39 #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
40 #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
41 #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
42 #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
44 #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
45 #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
46 #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
47 #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
48 #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
49 #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
50 #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
51 #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
52 #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
55 /*
56 * Debug Unit.
57 */
58 #define AT91_DBGU 0x200
60 #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
61 #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
62 #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
63 #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
64 #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
65 #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
66 #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
67 #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
68 #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
69 #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
70 #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
72 #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
73 #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
74 #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
75 #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
76 #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
77 #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
78 #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
79 #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
80 #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
81 #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
84 /*
85 * PIO Controllers.
86 */
87 #define AT91_PIOA 0x400
88 #define AT91_PIOB 0x600
89 #define AT91_PIOC 0x800
90 #define AT91_PIOD 0xa00
92 #define PIO_PER 0x00 /* Enable Register */
93 #define PIO_PDR 0x04 /* Disable Register */
94 #define PIO_PSR 0x08 /* Status Register */
95 #define PIO_OER 0x10 /* Output Enable Register */
96 #define PIO_ODR 0x14 /* Output Disable Register */
97 #define PIO_OSR 0x18 /* Output Status Register */
98 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
99 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
100 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
101 #define PIO_SODR 0x30 /* Set Output Data Register */
102 #define PIO_CODR 0x34 /* Clear Output Data Register */
103 #define PIO_ODSR 0x38 /* Output Data Status Register */
104 #define PIO_PDSR 0x3c /* Pin Data Status Register */
105 #define PIO_IER 0x40 /* Interrupt Enable Register */
106 #define PIO_IDR 0x44 /* Interrupt Disable Register */
107 #define PIO_IMR 0x48 /* Interrupt Mask Register */
108 #define PIO_ISR 0x4c /* Interrupt Status Register */
109 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
110 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
111 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
112 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
113 #define PIO_PUER 0x64 /* Pull-up Enable Register */
114 #define PIO_PUSR 0x68 /* Pull-up Status Register */
115 #define PIO_ASR 0x70 /* Peripheral A Select Register */
116 #define PIO_BSR 0x74 /* Peripheral B Select Register */
117 #define PIO_ABSR 0x78 /* AB Status Register */
118 #define PIO_OWER 0xa0 /* Output Write Enable Register */
119 #define PIO_OWDR 0xa4 /* Output Write Disable Register */
120 #define PIO_OWSR 0xa8 /* Output Write Status Register */
122 #define AT91_PIO_P(n) (1 << (n))
125 /*
126 * Power Management Controller.
127 */
128 #define AT91_PMC 0xc00
130 #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
131 #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
133 #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
134 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
135 #define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
136 #define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
137 #define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
138 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
139 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
140 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
141 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
143 #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
144 #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
145 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
147 #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
148 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
149 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
151 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
152 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
153 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
155 #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
156 #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
157 #define AT91_PMC_DIV (0xff << 0) /* Divider */
158 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
159 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
160 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
161 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
163 #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
164 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
165 #define AT91_PMC_CSS_SLOW (0 << 0)
166 #define AT91_PMC_CSS_MAIN (1 << 0)
167 #define AT91_PMC_CSS_PLLA (2 << 0)
168 #define AT91_PMC_CSS_PLLB (3 << 0)
169 #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
170 #define AT91_PMC_PRES_1 (0 << 2)
171 #define AT91_PMC_PRES_2 (1 << 2)
172 #define AT91_PMC_PRES_4 (2 << 2)
173 #define AT91_PMC_PRES_8 (3 << 2)
174 #define AT91_PMC_PRES_16 (4 << 2)
175 #define AT91_PMC_PRES_32 (5 << 2)
176 #define AT91_PMC_PRES_64 (6 << 2)
177 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
178 #define AT91_PMC_MDIV_1 (0 << 8)
179 #define AT91_PMC_MDIV_2 (1 << 8)
180 #define AT91_PMC_MDIV_3 (2 << 8)
181 #define AT91_PMC_MDIV_4 (3 << 8)
183 #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
185 #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
186 #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
187 #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
188 #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
189 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
190 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
191 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
192 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
193 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
194 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
195 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
196 #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
199 /*
200 * System Timer.
201 */
202 #define AT91_ST 0xd00
204 #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
205 #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
206 #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
207 #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
208 #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
209 #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
210 #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
211 #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
212 #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
213 #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
214 #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
215 #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
216 #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
217 #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
218 #define AT91_ST_ALMS (1 << 3) /* Alarm Status */
219 #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
220 #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
221 #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
222 #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
223 #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
224 #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
225 #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
228 /*
229 * Real-time Clock.
230 */
231 #define AT91_RTC 0xe00
233 #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
234 #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
235 #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
236 #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
237 #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
238 #define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
239 #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
240 #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
241 #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
242 #define AT91_RTC_CALEVSEL_WEEK (0 << 16)
243 #define AT91_RTC_CALEVSEL_MONTH (1 << 16)
244 #define AT91_RTC_CALEVSEL_YEAR (2 << 16)
246 #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
247 #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
249 #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
250 #define AT91_RTC_SEC (0x7f << 0) /* Current Second */
251 #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
252 #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
253 #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
255 #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
256 #define AT91_RTC_CENT (0x7f << 0) /* Current Century */
257 #define AT91_RTC_YEAR (0xff << 8) /* Current Year */
258 #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
259 #define AT91_RTC_DAY (7 << 21) /* Current Day */
260 #define AT91_RTC_DATE (0x3f << 24) /* Current Date */
262 #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
263 #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
264 #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
265 #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
267 #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
268 #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
269 #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
271 #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
272 #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
273 #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
274 #define AT91_RTC_SECEV (1 << 2) /* Second Event */
275 #define AT91_RTC_TIMEV (1 << 3) /* Time Event */
276 #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
278 #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
279 #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
280 #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
281 #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
283 #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
284 #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
285 #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
286 #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
287 #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
290 /*
291 * Memory Controller.
292 */
293 #define AT91_MC 0xf00
295 #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
296 #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
298 #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
299 #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
300 #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
301 #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
302 #define AT91_MC_ABTSZ_BYTE (0 << 8)
303 #define AT91_MC_ABTSZ_HALFWORD (1 << 8)
304 #define AT91_MC_ABTSZ_WORD (2 << 8)
305 #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
306 #define AT91_MC_ABTTYP_DATAREAD (0 << 10)
307 #define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
308 #define AT91_MC_ABTTYP_FETCH (2 << 10)
309 #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
310 #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
311 #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
312 #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
313 #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
314 #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
315 #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
316 #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
318 #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
320 #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
321 #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
322 #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
323 #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
324 #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
326 /* External Bus Interface (EBI) registers */
327 #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
328 #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
329 #define AT91_EBI_CS0A_SMC (0 << 0)
330 #define AT91_EBI_CS0A_BFC (1 << 0)
331 #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
332 #define AT91_EBI_CS1A_SMC (0 << 1)
333 #define AT91_EBI_CS1A_SDRAMC (1 << 1)
334 #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
335 #define AT91_EBI_CS3A_SMC (0 << 3)
336 #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
337 #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
338 #define AT91_EBI_CS4A_SMC (0 << 4)
339 #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
340 #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
341 #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
343 /* Static Memory Controller (SMC) registers */
344 #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
345 #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
346 #define AT91_SMC_NWS_(x) ((x) << 0)
347 #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
348 #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
349 #define AT91_SMC_TDF_(x) ((x) << 8)
350 #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
351 #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
352 #define AT91_SMC_DBW_16 (1 << 13)
353 #define AT91_SMC_DBW_8 (2 << 13)
354 #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
355 #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
356 #define AT91_SMC_ACSS_STD (0 << 16)
357 #define AT91_SMC_ACSS_1 (1 << 16)
358 #define AT91_SMC_ACSS_2 (2 << 16)
359 #define AT91_SMC_ACSS_3 (3 << 16)
360 #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
361 #define AT91_SMC_RWSETUP_(x) ((x) << 24)
362 #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
363 #define AT91_SMC_RWHOLD_(x) ((x) << 28)
365 /* SDRAM Controller registers */
366 #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
367 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
368 #define AT91_SDRAMC_MODE_NORMAL (0 << 0)
369 #define AT91_SDRAMC_MODE_NOP (1 << 0)
370 #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
371 #define AT91_SDRAMC_MODE_LMR (3 << 0)
372 #define AT91_SDRAMC_MODE_REFRESH (4 << 0)
373 #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
374 #define AT91_SDRAMC_DBW_32 (0 << 4)
375 #define AT91_SDRAMC_DBW_16 (1 << 4)
377 #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
378 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
380 #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
381 #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
382 #define AT91_SDRAMC_NC_8 (0 << 0)
383 #define AT91_SDRAMC_NC_9 (1 << 0)
384 #define AT91_SDRAMC_NC_10 (2 << 0)
385 #define AT91_SDRAMC_NC_11 (3 << 0)
386 #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
387 #define AT91_SDRAMC_NR_11 (0 << 2)
388 #define AT91_SDRAMC_NR_12 (1 << 2)
389 #define AT91_SDRAMC_NR_13 (2 << 2)
390 #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
391 #define AT91_SDRAMC_NB_2 (0 << 4)
392 #define AT91_SDRAMC_NB_4 (1 << 4)
393 #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
394 #define AT91_SDRAMC_CAS_2 (2 << 5)
395 #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
396 #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
397 #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
398 #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
399 #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
400 #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
402 #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
403 #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
404 #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
405 #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
406 #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
407 #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
409 /* Burst Flash Controller register */
410 #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
411 #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
412 #define AT91_BFC_BFCOM_DISABLED (0 << 0)
413 #define AT91_BFC_BFCOM_ASYNC (1 << 0)
414 #define AT91_BFC_BFCOM_BURST (2 << 0)
415 #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
416 #define AT91_BFC_BFCC_MCK (1 << 2)
417 #define AT91_BFC_BFCC_DIV2 (2 << 2)
418 #define AT91_BFC_BFCC_DIV4 (3 << 2)
419 #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
420 #define AT91_BFC_PAGES (7 << 8) /* Page Size */
421 #define AT91_BFC_PAGES_NO_PAGE (0 << 8)
422 #define AT91_BFC_PAGES_16 (1 << 8)
423 #define AT91_BFC_PAGES_32 (2 << 8)
424 #define AT91_BFC_PAGES_64 (3 << 8)
425 #define AT91_BFC_PAGES_128 (4 << 8)
426 #define AT91_BFC_PAGES_256 (5 << 8)
427 #define AT91_BFC_PAGES_512 (6 << 8)
428 #define AT91_BFC_PAGES_1024 (7 << 8)
429 #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
430 #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
431 #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
432 #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
433 #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
435 #endif