ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-at91rm9200/at91rm9200_emac.h @ 782:9ab1c319531f

merge with linux-2.6.18-xen.hg
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jan 28 13:07:23 2009 +0900 (2009-01-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_emac.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Ethernet MAC registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
16 #ifndef AT91RM9200_EMAC_H
17 #define AT91RM9200_EMAC_H
19 #define AT91_EMAC_CTL 0x00 /* Control Register */
20 #define AT91_EMAC_LB (1 << 0) /* Loopback */
21 #define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
22 #define AT91_EMAC_RE (1 << 2) /* Receive Enable */
23 #define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
24 #define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
25 #define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
26 #define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
27 #define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
28 #define AT91_EMAC_BP (1 << 8) /* Back Pressure */
30 #define AT91_EMAC_CFG 0x04 /* Configuration Register */
31 #define AT91_EMAC_SPD (1 << 0) /* Speed */
32 #define AT91_EMAC_FD (1 << 1) /* Full Duplex */
33 #define AT91_EMAC_BR (1 << 2) /* Bit Rate */
34 #define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
35 #define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
36 #define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
37 #define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
38 #define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
39 #define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
40 #define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
41 #define AT91_EMAC_CLK_DIV8 (0 << 10)
42 #define AT91_EMAC_CLK_DIV16 (1 << 10)
43 #define AT91_EMAC_CLK_DIV32 (2 << 10)
44 #define AT91_EMAC_CLK_DIV64 (3 << 10)
45 #define AT91_EMAC_RTY (1 << 12) /* Retry Test */
46 #define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
48 #define AT91_EMAC_SR 0x08 /* Status Register */
49 #define AT91_EMAC_SR_LINK (1 << 0) /* Link */
50 #define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
51 #define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
53 #define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
55 #define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
56 #define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
57 #define AT91_EMAC_NCRC (1 << 15) /* No CRC */
59 #define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
60 #define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
61 #define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
62 #define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
63 #define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
64 #define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
65 #define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
66 #define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
68 #define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
70 #define AT91_EMAC_RSR 0x20 /* Receive Status Register */
71 #define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
72 #define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
73 #define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
75 #define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
76 #define AT91_EMAC_DONE (1 << 0) /* Management Done */
77 #define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
78 #define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
79 #define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
80 #define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
81 #define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
82 #define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
83 #define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
84 #define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
85 #define AT91_EMAC_LINK (1 << 9) /* Link */
86 #define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
87 #define AT91_EMAC_ABT (1 << 11) /* Abort */
89 #define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
90 #define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
91 #define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
93 #define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
94 #define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
95 #define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
96 #define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
97 #define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
98 #define AT91_EMAC_RW_W (1 << 28)
99 #define AT91_EMAC_RW_R (2 << 28)
100 #define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
102 /*
103 * Statistics Registers.
104 */
105 #define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
106 #define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
107 #define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
108 #define AT91_EMAC_OK 0x4c /* Frames Received OK */
109 #define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
110 #define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
111 #define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
112 #define AT91_EMAC_LCOL 0x5c /* Late Collision */
113 #define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
114 #define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
115 #define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
116 #define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
117 #define AT91_EMAC_ROV 0x70 /* Receive Overrun */
118 #define AT91_EMAC_CDE 0x74 /* Code Error */
119 #define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
120 #define AT91_EMAC_RJB 0x7c /* Receive Jabber */
121 #define AT91_EMAC_USF 0x80 /* Undersize Frame */
122 #define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
124 /*
125 * Address Registers.
126 */
127 #define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
128 #define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
129 #define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
130 #define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
131 #define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
132 #define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
133 #define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
134 #define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
135 #define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
136 #define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
138 #endif