ia64/linux-2.6.18-xen.hg

view arch/v850/kernel/rte_mb_a_pci.c @ 854:950b9eb27661

usbback: fix urb interval value for interrupt urbs.

Signed-off-by: Noboru Iwamatsu <n_iwamatsu@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:51:20 2009 +0100 (2009-04-06)
parents 831230e53067
children
line source
1 /*
2 * arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board
3 *
4 * Copyright (C) 2001,02,03,05 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03,05 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/pci.h>
21 #include <asm/machdep.h>
23 /* __nomods_init is like __devinit, but is a no-op when modules are enabled.
24 This is used by some routines that can be called either during boot
25 or by a module. */
26 #ifdef CONFIG_MODULES
27 #define __nomods_init /*nothing*/
28 #else
29 #define __nomods_init __devinit
30 #endif
32 /* PCI devices on the Mother-A board can only do DMA to/from the MB SRAM
33 (the RTE-V850E/MA1-CB cpu board doesn't support PCI access to
34 CPU-board memory), and since linux DMA buffers are allocated in
35 normal kernel memory, we basically have to copy DMA blocks around
36 (this is like a `bounce buffer'). When a DMA block is `mapped', we
37 allocate an identically sized block in MB SRAM, and if we're doing
38 output to the device, copy the CPU-memory block to the MB-SRAM block.
39 When an active block is `unmapped', we will copy the block back to
40 CPU memory if necessary, and then deallocate the MB SRAM block.
41 Ack. */
43 /* Where the motherboard SRAM is in the PCI-bus address space (the
44 first 512K of it is also mapped at PCI address 0). */
45 #define PCI_MB_SRAM_ADDR 0x800000
47 /* Convert CPU-view MB SRAM address to/from PCI-view addresses of the
48 same memory. */
49 #define MB_SRAM_TO_PCI(mb_sram_addr) \
50 ((dma_addr_t)mb_sram_addr - MB_A_SRAM_ADDR + PCI_MB_SRAM_ADDR)
51 #define PCI_TO_MB_SRAM(pci_addr) \
52 (void *)(pci_addr - PCI_MB_SRAM_ADDR + MB_A_SRAM_ADDR)
54 static void pcibios_assign_resources (void);
56 struct mb_pci_dev_irq {
57 unsigned dev; /* PCI device number */
58 unsigned irq_base; /* First IRQ */
59 unsigned query_pin; /* True if we should read the device's
60 Interrupt Pin info, and allocate
61 interrupt IRQ_BASE + PIN. */
62 };
64 /* PCI interrupts are mapped statically to GBUS interrupts. */
65 static struct mb_pci_dev_irq mb_pci_dev_irqs[] = {
66 /* Motherboard SB82558 ethernet controller */
67 { 10, IRQ_MB_A_LAN, 0 },
68 /* PCI slot 1 */
69 { 8, IRQ_MB_A_PCI1(0), 1 },
70 /* PCI slot 2 */
71 { 9, IRQ_MB_A_PCI2(0), 1 }
72 };
73 #define NUM_MB_PCI_DEV_IRQS \
74 (sizeof mb_pci_dev_irqs / sizeof mb_pci_dev_irqs[0])
77 /* PCI configuration primitives. */
79 #define CONFIG_DMCFGA(bus, devfn, offs) \
80 (0x80000000 \
81 | ((offs) & ~0x3) \
82 | ((devfn) << 8) \
83 | ((bus)->number << 16))
85 static int
86 mb_pci_read (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 *rval)
87 {
88 u32 addr;
89 int flags;
91 local_irq_save (flags);
93 MB_A_PCI_PCICR = 0x7;
94 MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
96 addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
98 switch (size) {
99 case 1: *rval = *(volatile u8 *)addr; break;
100 case 2: *rval = *(volatile u16 *)addr; break;
101 case 4: *rval = *(volatile u32 *)addr; break;
102 }
104 if (MB_A_PCI_PCISR & 0x2000) {
105 MB_A_PCI_PCISR = 0x2000;
106 *rval = ~0;
107 }
109 MB_A_PCI_DMCFGA = 0;
111 local_irq_restore (flags);
113 return PCIBIOS_SUCCESSFUL;
114 }
116 static int
117 mb_pci_write (struct pci_bus *bus, unsigned devfn, int offs, int size, u32 val)
118 {
119 u32 addr;
120 int flags;
122 local_irq_save (flags);
124 MB_A_PCI_PCICR = 0x7;
125 MB_A_PCI_DMCFGA = CONFIG_DMCFGA (bus, devfn, offs);
127 addr = MB_A_PCI_IO_ADDR + (offs & 0x3);
129 switch (size) {
130 case 1: *(volatile u8 *)addr = val; break;
131 case 2: *(volatile u16 *)addr = val; break;
132 case 4: *(volatile u32 *)addr = val; break;
133 }
135 if (MB_A_PCI_PCISR & 0x2000)
136 MB_A_PCI_PCISR = 0x2000;
138 MB_A_PCI_DMCFGA = 0;
140 local_irq_restore (flags);
142 return PCIBIOS_SUCCESSFUL;
143 }
145 static struct pci_ops mb_pci_config_ops = {
146 .read = mb_pci_read,
147 .write = mb_pci_write,
148 };
151 /* PCI Initialization. */
153 static struct pci_bus *mb_pci_bus = 0;
155 /* Do initial PCI setup. */
156 static int __devinit pcibios_init (void)
157 {
158 u32 id = MB_A_PCI_PCIHIDR;
159 u16 vendor = id & 0xFFFF;
160 u16 device = (id >> 16) & 0xFFFF;
162 if (vendor == PCI_VENDOR_ID_PLX && device == PCI_DEVICE_ID_PLX_9080) {
163 printk (KERN_INFO
164 "PCI: PLX Technology PCI9080 HOST/PCI bridge\n");
166 MB_A_PCI_PCICR = 0x147;
168 MB_A_PCI_PCIBAR0 = 0x007FFF00;
169 MB_A_PCI_PCIBAR1 = 0x0000FF00;
170 MB_A_PCI_PCIBAR2 = 0x00800000;
172 MB_A_PCI_PCILTR = 0x20;
174 MB_A_PCI_PCIPBAM |= 0x3;
176 MB_A_PCI_PCISR = ~0; /* Clear errors. */
178 /* Reprogram the motherboard's IO/config address space,
179 as we don't support the GCS7 address space that the
180 default uses. */
182 /* Significant address bits used for decoding PCI GCS5 space
183 accessess. */
184 MB_A_PCI_DMRR = ~(MB_A_PCI_MEM_SIZE - 1);
186 /* I don't understand this, but the SolutionGear example code
187 uses such an offset, and it doesn't work without it. XXX */
188 #if GCS5_SIZE == 0x00800000
189 #define GCS5_CFG_OFFS 0x00800000
190 #else
191 #define GCS5_CFG_OFFS 0
192 #endif
194 /* Address bit values for matching. Note that we have to give
195 the address from the motherboard's point of view, which is
196 different than the CPU's. */
197 /* PCI memory space. */
198 MB_A_PCI_DMLBAM = GCS5_CFG_OFFS + 0x0;
199 /* PCI I/O space. */
200 MB_A_PCI_DMLBAI =
201 GCS5_CFG_OFFS + (MB_A_PCI_IO_ADDR - GCS5_ADDR);
203 mb_pci_bus = pci_scan_bus (0, &mb_pci_config_ops, 0);
205 pcibios_assign_resources ();
206 } else
207 printk (KERN_ERR "PCI: HOST/PCI bridge not found\n");
209 return 0;
210 }
212 subsys_initcall (pcibios_init);
214 char __devinit *pcibios_setup (char *option)
215 {
216 /* Don't handle any options. */
217 return option;
218 }
221 int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
222 {
223 u16 cmd, old_cmd;
224 int idx;
225 struct resource *r;
227 pci_read_config_word(dev, PCI_COMMAND, &cmd);
228 old_cmd = cmd;
229 for (idx = 0; idx < 6; idx++) {
230 r = &dev->resource[idx];
231 if (!r->start && r->end) {
232 printk(KERN_ERR "PCI: Device %s not available because "
233 "of resource collisions\n", pci_name(dev));
234 return -EINVAL;
235 }
236 if (r->flags & IORESOURCE_IO)
237 cmd |= PCI_COMMAND_IO;
238 if (r->flags & IORESOURCE_MEM)
239 cmd |= PCI_COMMAND_MEMORY;
240 }
241 if (cmd != old_cmd) {
242 printk("PCI: Enabling device %s (%04x -> %04x)\n",
243 pci_name(dev), old_cmd, cmd);
244 pci_write_config_word(dev, PCI_COMMAND, cmd);
245 }
246 return 0;
247 }
250 /* Resource allocation. */
251 static void __devinit pcibios_assign_resources (void)
252 {
253 struct pci_dev *dev = NULL;
254 struct resource *r;
256 for_each_pci_dev(dev) {
257 unsigned di_num;
258 unsigned class = dev->class >> 8;
260 if (class && class != PCI_CLASS_BRIDGE_HOST) {
261 unsigned r_num;
262 for(r_num = 0; r_num < 6; r_num++) {
263 r = &dev->resource[r_num];
264 if (!r->start && r->end)
265 pci_assign_resource (dev, r_num);
266 }
267 }
269 /* Assign interrupts. */
270 for (di_num = 0; di_num < NUM_MB_PCI_DEV_IRQS; di_num++) {
271 struct mb_pci_dev_irq *di = &mb_pci_dev_irqs[di_num];
273 if (di->dev == PCI_SLOT (dev->devfn)) {
274 unsigned irq = di->irq_base;
276 if (di->query_pin) {
277 /* Find out which interrupt pin
278 this device uses (each PCI
279 slot has 4). */
280 u8 irq_pin;
282 pci_read_config_byte (dev,
283 PCI_INTERRUPT_PIN,
284 &irq_pin);
286 if (irq_pin == 0)
287 /* Doesn't use interrupts. */
288 continue;
289 else
290 irq += irq_pin - 1;
291 }
293 pcibios_update_irq (dev, irq);
294 }
295 }
296 }
297 }
299 void __devinit pcibios_update_irq (struct pci_dev *dev, int irq)
300 {
301 dev->irq = irq;
302 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
303 }
305 void __devinit
306 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
307 struct resource *res)
308 {
309 unsigned long offset = 0;
311 if (res->flags & IORESOURCE_IO) {
312 offset = MB_A_PCI_IO_ADDR;
313 } else if (res->flags & IORESOURCE_MEM) {
314 offset = MB_A_PCI_MEM_ADDR;
315 }
317 region->start = res->start - offset;
318 region->end = res->end - offset;
319 }
322 /* Stubs for things we don't use. */
324 /* Called after each bus is probed, but before its children are examined. */
325 void pcibios_fixup_bus(struct pci_bus *b)
326 {
327 }
329 void
330 pcibios_align_resource (void *data, struct resource *res,
331 resource_size_t size, resource_size_t align)
332 {
333 }
335 void pcibios_set_master (struct pci_dev *dev)
336 {
337 }
340 /* Mother-A SRAM memory allocation. This is a simple first-fit allocator. */
342 /* A memory free-list node. */
343 struct mb_sram_free_area {
344 void *mem;
345 unsigned long size;
346 struct mb_sram_free_area *next;
347 };
349 /* The tail of the free-list, which starts out containing all the SRAM. */
350 static struct mb_sram_free_area mb_sram_free_tail = {
351 (void *)MB_A_SRAM_ADDR, MB_A_SRAM_SIZE, 0
352 };
354 /* The free-list. */
355 static struct mb_sram_free_area *mb_sram_free_areas = &mb_sram_free_tail;
357 /* The free-list of free free-list nodes. (:-) */
358 static struct mb_sram_free_area *mb_sram_free_free_areas = 0;
360 /* Spinlock protecting the above globals. */
361 static DEFINE_SPINLOCK(mb_sram_lock);
363 /* Allocate a memory block at least SIZE bytes long in the Mother-A SRAM
364 space. */
365 static void *alloc_mb_sram (size_t size)
366 {
367 struct mb_sram_free_area *prev, *fa;
368 int flags;
369 void *mem = 0;
371 spin_lock_irqsave (mb_sram_lock, flags);
373 /* Look for a free area that can contain SIZE bytes. */
374 for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
375 if (fa->size >= size) {
376 /* Found one! */
377 mem = fa->mem;
379 if (fa->size == size) {
380 /* In fact, it fits exactly, so remove
381 this node from the free-list. */
382 if (prev)
383 prev->next = fa->next;
384 else
385 mb_sram_free_areas = fa->next;
386 /* Put it on the free-list-entry-free-list. */
387 fa->next = mb_sram_free_free_areas;
388 mb_sram_free_free_areas = fa;
389 } else {
390 /* FA is bigger than SIZE, so just
391 reduce its size to account for this
392 allocation. */
393 fa->mem += size;
394 fa->size -= size;
395 }
397 break;
398 }
400 spin_unlock_irqrestore (mb_sram_lock, flags);
402 return mem;
403 }
405 /* Return the memory area MEM of size SIZE to the MB SRAM free pool. */
406 static void free_mb_sram (void *mem, size_t size)
407 {
408 struct mb_sram_free_area *prev, *fa, *new_fa;
409 int flags;
410 void *end = mem + size;
412 spin_lock_irqsave (mb_sram_lock, flags);
414 retry:
415 /* Find an adjacent free-list entry. */
416 for (prev = 0, fa = mb_sram_free_areas; fa; prev = fa, fa = fa->next)
417 if (fa->mem == end) {
418 /* FA is just after MEM, grow down to encompass it. */
419 fa->mem = mem;
420 fa->size += size;
421 goto done;
422 } else if (fa->mem + fa->size == mem) {
423 struct mb_sram_free_area *next_fa = fa->next;
425 /* FA is just before MEM, expand to encompass it. */
426 fa->size += size;
428 /* See if FA can now be merged with its successor. */
429 if (next_fa && fa->mem + fa->size == next_fa->mem) {
430 /* Yup; merge NEXT_FA's info into FA. */
431 fa->size += next_fa->size;
432 fa->next = next_fa->next;
433 /* Free NEXT_FA. */
434 next_fa->next = mb_sram_free_free_areas;
435 mb_sram_free_free_areas = next_fa;
436 }
437 goto done;
438 } else if (fa->mem > mem)
439 /* We've reached the right spot in the free-list
440 without finding an adjacent free-area, so add
441 a new free area to hold mem. */
442 break;
444 /* Make a new free-list entry. */
446 /* First, get a free-list entry. */
447 if (! mb_sram_free_free_areas) {
448 /* There are none, so make some. */
449 void *block;
450 size_t block_size = sizeof (struct mb_sram_free_area) * 8;
452 /* Don't hold the lock while calling kmalloc (I'm not
453 sure whether it would be a problem, since we use
454 GFP_ATOMIC, but it makes me nervous). */
455 spin_unlock_irqrestore (mb_sram_lock, flags);
457 block = kmalloc (block_size, GFP_ATOMIC);
458 if (! block)
459 panic ("free_mb_sram: can't allocate free-list entry");
461 /* Now get the lock back. */
462 spin_lock_irqsave (mb_sram_lock, flags);
464 /* Add the new free free-list entries. */
465 while (block_size > 0) {
466 struct mb_sram_free_area *nfa = block;
467 nfa->next = mb_sram_free_free_areas;
468 mb_sram_free_free_areas = nfa;
469 block += sizeof *nfa;
470 block_size -= sizeof *nfa;
471 }
473 /* Since we dropped the lock to call kmalloc, the
474 free-list could have changed, so retry from the
475 beginning. */
476 goto retry;
477 }
479 /* Remove NEW_FA from the free-list of free-list entries. */
480 new_fa = mb_sram_free_free_areas;
481 mb_sram_free_free_areas = new_fa->next;
483 /* NEW_FA initially holds only MEM. */
484 new_fa->mem = mem;
485 new_fa->size = size;
487 /* Insert NEW_FA in the free-list between PREV and FA. */
488 new_fa->next = fa;
489 if (prev)
490 prev->next = new_fa;
491 else
492 mb_sram_free_areas = new_fa;
494 done:
495 spin_unlock_irqrestore (mb_sram_lock, flags);
496 }
499 /* Maintainence of CPU -> Mother-A DMA mappings. */
501 struct dma_mapping {
502 void *cpu_addr;
503 void *mb_sram_addr;
504 size_t size;
505 struct dma_mapping *next;
506 };
508 /* A list of mappings from CPU addresses to MB SRAM addresses for active
509 DMA blocks (that have been `granted' to the PCI device). */
510 static struct dma_mapping *active_dma_mappings = 0;
512 /* A list of free mapping objects. */
513 static struct dma_mapping *free_dma_mappings = 0;
515 /* Spinlock protecting the above globals. */
516 static DEFINE_SPINLOCK(dma_mappings_lock);
518 static struct dma_mapping *new_dma_mapping (size_t size)
519 {
520 int flags;
521 struct dma_mapping *mapping;
522 void *mb_sram_block = alloc_mb_sram (size);
524 if (! mb_sram_block)
525 return 0;
527 spin_lock_irqsave (dma_mappings_lock, flags);
529 if (! free_dma_mappings) {
530 /* We're out of mapping structures, make more. */
531 void *mblock;
532 size_t mblock_size = sizeof (struct dma_mapping) * 8;
534 /* Don't hold the lock while calling kmalloc (I'm not
535 sure whether it would be a problem, since we use
536 GFP_ATOMIC, but it makes me nervous). */
537 spin_unlock_irqrestore (dma_mappings_lock, flags);
539 mblock = kmalloc (mblock_size, GFP_ATOMIC);
540 if (! mblock) {
541 free_mb_sram (mb_sram_block, size);
542 return 0;
543 }
545 /* Get the lock back. */
546 spin_lock_irqsave (dma_mappings_lock, flags);
548 /* Add the new mapping structures to the free-list. */
549 while (mblock_size > 0) {
550 struct dma_mapping *fm = mblock;
551 fm->next = free_dma_mappings;
552 free_dma_mappings = fm;
553 mblock += sizeof *fm;
554 mblock_size -= sizeof *fm;
555 }
556 }
558 /* Get a mapping struct from the freelist. */
559 mapping = free_dma_mappings;
560 free_dma_mappings = mapping->next;
562 /* Initialize the mapping. Other fields should be filled in by
563 caller. */
564 mapping->mb_sram_addr = mb_sram_block;
565 mapping->size = size;
567 /* Add it to the list of active mappings. */
568 mapping->next = active_dma_mappings;
569 active_dma_mappings = mapping;
571 spin_unlock_irqrestore (dma_mappings_lock, flags);
573 return mapping;
574 }
576 static struct dma_mapping *find_dma_mapping (void *mb_sram_addr)
577 {
578 int flags;
579 struct dma_mapping *mapping;
581 spin_lock_irqsave (dma_mappings_lock, flags);
583 for (mapping = active_dma_mappings; mapping; mapping = mapping->next)
584 if (mapping->mb_sram_addr == mb_sram_addr) {
585 spin_unlock_irqrestore (dma_mappings_lock, flags);
586 return mapping;
587 }
589 panic ("find_dma_mapping: unmapped PCI DMA addr 0x%x",
590 MB_SRAM_TO_PCI (mb_sram_addr));
591 }
593 static struct dma_mapping *deactivate_dma_mapping (void *mb_sram_addr)
594 {
595 int flags;
596 struct dma_mapping *mapping, *prev;
598 spin_lock_irqsave (dma_mappings_lock, flags);
600 for (prev = 0, mapping = active_dma_mappings;
601 mapping;
602 prev = mapping, mapping = mapping->next)
603 {
604 if (mapping->mb_sram_addr == mb_sram_addr) {
605 /* This is the MAPPING; deactivate it. */
606 if (prev)
607 prev->next = mapping->next;
608 else
609 active_dma_mappings = mapping->next;
611 spin_unlock_irqrestore (dma_mappings_lock, flags);
613 return mapping;
614 }
615 }
617 panic ("deactivate_dma_mapping: unmapped PCI DMA addr 0x%x",
618 MB_SRAM_TO_PCI (mb_sram_addr));
619 }
621 /* Return MAPPING to the freelist. */
622 static inline void
623 free_dma_mapping (struct dma_mapping *mapping)
624 {
625 int flags;
627 free_mb_sram (mapping->mb_sram_addr, mapping->size);
629 spin_lock_irqsave (dma_mappings_lock, flags);
631 mapping->next = free_dma_mappings;
632 free_dma_mappings = mapping;
634 spin_unlock_irqrestore (dma_mappings_lock, flags);
635 }
638 /* Single PCI DMA mappings. */
640 /* `Grant' to PDEV the memory block at CPU_ADDR, for doing DMA. The
641 32-bit PCI bus mastering address to use is returned. the device owns
642 this memory until either pci_unmap_single or pci_dma_sync_single is
643 performed. */
644 dma_addr_t
645 pci_map_single (struct pci_dev *pdev, void *cpu_addr, size_t size, int dir)
646 {
647 struct dma_mapping *mapping = new_dma_mapping (size);
649 if (! mapping)
650 return 0;
652 mapping->cpu_addr = cpu_addr;
654 if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_TODEVICE)
655 memcpy (mapping->mb_sram_addr, cpu_addr, size);
657 return MB_SRAM_TO_PCI (mapping->mb_sram_addr);
658 }
660 /* Return to the CPU the PCI DMA memory block previously `granted' to
661 PDEV, at DMA_ADDR. */
662 void pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
663 int dir)
664 {
665 void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
666 struct dma_mapping *mapping = deactivate_dma_mapping (mb_sram_addr);
668 if (size != mapping->size)
669 panic ("pci_unmap_single: size (%d) doesn't match"
670 " size of mapping at PCI DMA addr 0x%x (%d)\n",
671 size, dma_addr, mapping->size);
673 /* Copy back the DMA'd contents if necessary. */
674 if (dir == PCI_DMA_BIDIRECTIONAL || dir == PCI_DMA_FROMDEVICE)
675 memcpy (mapping->cpu_addr, mb_sram_addr, size);
677 /* Return mapping to the freelist. */
678 free_dma_mapping (mapping);
679 }
681 /* Make physical memory consistent for a single streaming mode DMA
682 translation after a transfer.
684 If you perform a pci_map_single() but wish to interrogate the
685 buffer using the cpu, yet do not wish to teardown the PCI dma
686 mapping, you must call this function before doing so. At the next
687 point you give the PCI dma address back to the card, you must first
688 perform a pci_dma_sync_for_device, and then the device again owns
689 the buffer. */
690 void
691 pci_dma_sync_single_for_cpu (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
692 int dir)
693 {
694 void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
695 struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
697 /* Synchronize the DMA buffer with the CPU buffer if necessary. */
698 if (dir == PCI_DMA_FROMDEVICE)
699 memcpy (mapping->cpu_addr, mb_sram_addr, size);
700 else if (dir == PCI_DMA_TODEVICE)
701 ; /* nothing to do */
702 else
703 panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
704 }
706 void
707 pci_dma_sync_single_for_device (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
708 int dir)
709 {
710 void *mb_sram_addr = PCI_TO_MB_SRAM (dma_addr);
711 struct dma_mapping *mapping = find_dma_mapping (mb_sram_addr);
713 /* Synchronize the DMA buffer with the CPU buffer if necessary. */
714 if (dir == PCI_DMA_FROMDEVICE)
715 ; /* nothing to do */
716 else if (dir == PCI_DMA_TODEVICE)
717 memcpy (mb_sram_addr, mapping->cpu_addr, size);
718 else
719 panic("pci_dma_sync_single: unsupported sync dir: %d", dir);
720 }
723 /* Scatter-gather PCI DMA mappings. */
725 /* Do multiple DMA mappings at once. */
726 int
727 pci_map_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir)
728 {
729 BUG ();
730 return 0;
731 }
733 /* Unmap multiple DMA mappings at once. */
734 void
735 pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir)
736 {
737 BUG ();
738 }
740 /* Make physical memory consistent for a set of streaming mode DMA
741 translations after a transfer. The same as pci_dma_sync_single_* but
742 for a scatter-gather list, same rules and usage. */
744 void
745 pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
746 struct scatterlist *sg, int sg_len,
747 int dir)
748 {
749 BUG ();
750 }
752 void
753 pci_dma_sync_sg_for_device (struct pci_dev *dev,
754 struct scatterlist *sg, int sg_len,
755 int dir)
756 {
757 BUG ();
758 }
761 /* PCI mem mapping. */
763 /* Allocate and map kernel buffer using consistent mode DMA for PCI
764 device. Returns non-NULL cpu-view pointer to the buffer if
765 successful and sets *DMA_ADDR to the pci side dma address as well,
766 else DMA_ADDR is undefined. */
767 void *
768 pci_alloc_consistent (struct pci_dev *pdev, size_t size, dma_addr_t *dma_addr)
769 {
770 void *mb_sram_mem = alloc_mb_sram (size);
771 if (mb_sram_mem)
772 *dma_addr = MB_SRAM_TO_PCI (mb_sram_mem);
773 return mb_sram_mem;
774 }
776 /* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
777 be values that were returned from pci_alloc_consistent. SIZE must be
778 the same as what as passed into pci_alloc_consistent. References to
779 the memory and mappings assosciated with CPU_ADDR or DMA_ADDR past
780 this call are illegal. */
781 void
782 pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
783 dma_addr_t dma_addr)
784 {
785 void *mb_sram_mem = PCI_TO_MB_SRAM (dma_addr);
786 free_mb_sram (mb_sram_mem, size);
787 }
790 /* iomap/iomap */
792 void __iomem *pci_iomap (struct pci_dev *dev, int bar, unsigned long max)
793 {
794 unsigned long start = pci_resource_start (dev, bar);
795 unsigned long len = pci_resource_len (dev, bar);
797 if (!start || len == 0)
798 return 0;
800 /* None of the ioremap functions actually do anything, other than
801 re-casting their argument, so don't bother differentiating them. */
802 return ioremap (start, len);
803 }
805 void pci_iounmap (struct pci_dev *dev, void __iomem *addr)
806 {
807 /* nothing */
808 }
811 /* symbol exports (for modules) */
813 EXPORT_SYMBOL (pci_map_single);
814 EXPORT_SYMBOL (pci_unmap_single);
815 EXPORT_SYMBOL (pci_alloc_consistent);
816 EXPORT_SYMBOL (pci_free_consistent);
817 EXPORT_SYMBOL (pci_dma_sync_single_for_cpu);
818 EXPORT_SYMBOL (pci_dma_sync_single_for_device);
819 EXPORT_SYMBOL (pci_iomap);
820 EXPORT_SYMBOL (pci_iounmap);