ia64/linux-2.6.18-xen.hg

view arch/powerpc/oprofile/op_model_rs64.c @ 854:950b9eb27661

usbback: fix urb interval value for interrupt urbs.

Signed-off-by: Noboru Iwamatsu <n_iwamatsu@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:51:20 2009 +0100 (2009-04-06)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
10 #include <linux/oprofile.h>
11 #include <linux/init.h>
12 #include <linux/smp.h>
13 #include <asm/ptrace.h>
14 #include <asm/system.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
17 #include <asm/oprofile_impl.h>
19 #define dbg(args...)
21 static void ctrl_write(unsigned int i, unsigned int val)
22 {
23 unsigned int tmp = 0;
24 unsigned long shift = 0, mask = 0;
26 dbg("ctrl_write %d %x\n", i, val);
28 switch(i) {
29 case 0:
30 tmp = mfspr(SPRN_MMCR0);
31 shift = 6;
32 mask = 0x7F;
33 break;
34 case 1:
35 tmp = mfspr(SPRN_MMCR0);
36 shift = 0;
37 mask = 0x3F;
38 break;
39 case 2:
40 tmp = mfspr(SPRN_MMCR1);
41 shift = 31 - 4;
42 mask = 0x1F;
43 break;
44 case 3:
45 tmp = mfspr(SPRN_MMCR1);
46 shift = 31 - 9;
47 mask = 0x1F;
48 break;
49 case 4:
50 tmp = mfspr(SPRN_MMCR1);
51 shift = 31 - 14;
52 mask = 0x1F;
53 break;
54 case 5:
55 tmp = mfspr(SPRN_MMCR1);
56 shift = 31 - 19;
57 mask = 0x1F;
58 break;
59 case 6:
60 tmp = mfspr(SPRN_MMCR1);
61 shift = 31 - 24;
62 mask = 0x1F;
63 break;
64 case 7:
65 tmp = mfspr(SPRN_MMCR1);
66 shift = 31 - 28;
67 mask = 0xF;
68 break;
69 }
71 tmp = tmp & ~(mask << shift);
72 tmp |= val << shift;
74 switch(i) {
75 case 0:
76 case 1:
77 mtspr(SPRN_MMCR0, tmp);
78 break;
79 default:
80 mtspr(SPRN_MMCR1, tmp);
81 }
83 dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
84 mfspr(SPRN_MMCR1));
85 }
87 static unsigned long reset_value[OP_MAX_COUNTER];
89 static int num_counters;
91 static void rs64_reg_setup(struct op_counter_config *ctr,
92 struct op_system_config *sys,
93 int num_ctrs)
94 {
95 int i;
97 num_counters = num_ctrs;
99 for (i = 0; i < num_counters; ++i)
100 reset_value[i] = 0x80000000UL - ctr[i].count;
102 /* XXX setup user and kernel profiling */
103 }
105 static void rs64_cpu_setup(void *unused)
106 {
107 unsigned int mmcr0;
109 /* reset MMCR0 and set the freeze bit */
110 mmcr0 = MMCR0_FC;
111 mtspr(SPRN_MMCR0, mmcr0);
113 /* reset MMCR1, MMCRA */
114 mtspr(SPRN_MMCR1, 0);
116 if (cpu_has_feature(CPU_FTR_MMCRA))
117 mtspr(SPRN_MMCRA, 0);
119 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
120 /* Only applies to POWER3, but should be safe on RS64 */
121 mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
122 mtspr(SPRN_MMCR0, mmcr0);
124 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
125 mfspr(SPRN_MMCR0));
126 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
127 mfspr(SPRN_MMCR1));
128 }
130 static void rs64_start(struct op_counter_config *ctr)
131 {
132 int i;
133 unsigned int mmcr0;
135 /* set the PMM bit (see comment below) */
136 mtmsrd(mfmsr() | MSR_PMM);
138 for (i = 0; i < num_counters; ++i) {
139 if (ctr[i].enabled) {
140 ctr_write(i, reset_value[i]);
141 ctrl_write(i, ctr[i].event);
142 } else {
143 ctr_write(i, 0);
144 }
145 }
147 mmcr0 = mfspr(SPRN_MMCR0);
149 /*
150 * now clear the freeze bit, counting will not start until we
151 * rfid from this excetion, because only at that point will
152 * the PMM bit be cleared
153 */
154 mmcr0 &= ~MMCR0_FC;
155 mtspr(SPRN_MMCR0, mmcr0);
157 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
158 }
160 static void rs64_stop(void)
161 {
162 unsigned int mmcr0;
164 /* freeze counters */
165 mmcr0 = mfspr(SPRN_MMCR0);
166 mmcr0 |= MMCR0_FC;
167 mtspr(SPRN_MMCR0, mmcr0);
169 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
171 mb();
172 }
174 static void rs64_handle_interrupt(struct pt_regs *regs,
175 struct op_counter_config *ctr)
176 {
177 unsigned int mmcr0;
178 int is_kernel;
179 int val;
180 int i;
181 unsigned long pc = mfspr(SPRN_SIAR);
183 is_kernel = is_kernel_addr(pc);
185 /* set the PMM bit (see comment below) */
186 mtmsrd(mfmsr() | MSR_PMM);
188 for (i = 0; i < num_counters; ++i) {
189 val = ctr_read(i);
190 if (val < 0) {
191 if (ctr[i].enabled) {
192 oprofile_add_ext_sample(pc, regs, i, is_kernel);
193 ctr_write(i, reset_value[i]);
194 } else {
195 ctr_write(i, 0);
196 }
197 }
198 }
200 mmcr0 = mfspr(SPRN_MMCR0);
202 /* reset the perfmon trigger */
203 mmcr0 |= MMCR0_PMXE;
205 /*
206 * now clear the freeze bit, counting will not start until we
207 * rfid from this exception, because only at that point will
208 * the PMM bit be cleared
209 */
210 mmcr0 &= ~MMCR0_FC;
211 mtspr(SPRN_MMCR0, mmcr0);
212 }
214 struct op_powerpc_model op_model_rs64 = {
215 .reg_setup = rs64_reg_setup,
216 .cpu_setup = rs64_cpu_setup,
217 .start = rs64_start,
218 .stop = rs64_stop,
219 .handle_interrupt = rs64_handle_interrupt,
220 };