ia64/linux-2.6.18-xen.hg

view arch/powerpc/oprofile/op_model_7450.c @ 854:950b9eb27661

usbback: fix urb interval value for interrupt urbs.

Signed-off-by: Noboru Iwamatsu <n_iwamatsu@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:51:20 2009 +0100 (2009-04-06)
parents 831230e53067
children
line source
1 /*
2 * oprofile/op_model_7450.c
3 *
4 * Freescale 745x/744x oprofile support, based on fsl_booke support
5 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
6 *
7 * Copyright (c) 2004 Freescale Semiconductor, Inc
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
18 #include <linux/oprofile.h>
19 #include <linux/init.h>
20 #include <linux/smp.h>
21 #include <asm/ptrace.h>
22 #include <asm/system.h>
23 #include <asm/processor.h>
24 #include <asm/cputable.h>
25 #include <asm/page.h>
26 #include <asm/pmc.h>
27 #include <asm/oprofile_impl.h>
29 static unsigned long reset_value[OP_MAX_COUNTER];
31 static int oprofile_running;
32 static u32 mmcr0_val, mmcr1_val, mmcr2_val;
34 #define MMCR0_PMC1_SHIFT 6
35 #define MMCR0_PMC2_SHIFT 0
36 #define MMCR1_PMC3_SHIFT 27
37 #define MMCR1_PMC4_SHIFT 22
38 #define MMCR1_PMC5_SHIFT 17
39 #define MMCR1_PMC6_SHIFT 11
41 #define mmcr0_event1(event) \
42 ((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
43 #define mmcr0_event2(event) \
44 ((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)
46 #define mmcr1_event3(event) \
47 ((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
48 #define mmcr1_event4(event) \
49 ((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
50 #define mmcr1_event5(event) \
51 ((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
52 #define mmcr1_event6(event) \
53 ((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)
55 #define MMCR0_INIT (MMCR0_FC | MMCR0_FCS | MMCR0_FCP | MMCR0_FCM1 | MMCR0_FCM0)
57 /* Unfreezes the counters on this CPU, enables the interrupt,
58 * enables the counters to trigger the interrupt, and sets the
59 * counters to only count when the mark bit is not set.
60 */
61 static void pmc_start_ctrs(void)
62 {
63 u32 mmcr0 = mfspr(SPRN_MMCR0);
65 mmcr0 &= ~(MMCR0_FC | MMCR0_FCM0);
66 mmcr0 |= (MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
68 mtspr(SPRN_MMCR0, mmcr0);
69 }
71 /* Disables the counters on this CPU, and freezes them */
72 static void pmc_stop_ctrs(void)
73 {
74 u32 mmcr0 = mfspr(SPRN_MMCR0);
76 mmcr0 |= MMCR0_FC;
77 mmcr0 &= ~(MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
79 mtspr(SPRN_MMCR0, mmcr0);
80 }
82 /* Configures the counters on this CPU based on the global
83 * settings */
84 static void fsl7450_cpu_setup(void *unused)
85 {
86 /* freeze all counters */
87 pmc_stop_ctrs();
89 mtspr(SPRN_MMCR0, mmcr0_val);
90 mtspr(SPRN_MMCR1, mmcr1_val);
91 mtspr(SPRN_MMCR2, mmcr2_val);
92 }
94 #define NUM_CTRS 6
96 /* Configures the global settings for the countes on all CPUs. */
97 static void fsl7450_reg_setup(struct op_counter_config *ctr,
98 struct op_system_config *sys,
99 int num_ctrs)
100 {
101 int i;
103 /* Our counters count up, and "count" refers to
104 * how much before the next interrupt, and we interrupt
105 * on overflow. So we calculate the starting value
106 * which will give us "count" until overflow.
107 * Then we set the events on the enabled counters */
108 for (i = 0; i < NUM_CTRS; ++i)
109 reset_value[i] = 0x80000000UL - ctr[i].count;
111 /* Set events for Counters 1 & 2 */
112 mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event)
113 | mmcr0_event2(ctr[1].event);
115 /* Setup user/kernel bits */
116 if (sys->enable_kernel)
117 mmcr0_val &= ~(MMCR0_FCS);
119 if (sys->enable_user)
120 mmcr0_val &= ~(MMCR0_FCP);
122 /* Set events for Counters 3-6 */
123 mmcr1_val = mmcr1_event3(ctr[2].event)
124 | mmcr1_event4(ctr[3].event)
125 | mmcr1_event5(ctr[4].event)
126 | mmcr1_event6(ctr[5].event);
128 mmcr2_val = 0;
129 }
131 /* Sets the counters on this CPU to the chosen values, and starts them */
132 static void fsl7450_start(struct op_counter_config *ctr)
133 {
134 int i;
136 mtmsr(mfmsr() | MSR_PMM);
138 for (i = 0; i < NUM_CTRS; ++i) {
139 if (ctr[i].enabled)
140 ctr_write(i, reset_value[i]);
141 else
142 ctr_write(i, 0);
143 }
145 /* Clear the freeze bit, and enable the interrupt.
146 * The counters won't actually start until the rfi clears
147 * the PMM bit */
148 pmc_start_ctrs();
150 oprofile_running = 1;
151 }
153 /* Stop the counters on this CPU */
154 static void fsl7450_stop(void)
155 {
156 /* freeze counters */
157 pmc_stop_ctrs();
159 oprofile_running = 0;
161 mb();
162 }
165 /* Handle the interrupt on this CPU, and log a sample for each
166 * event that triggered the interrupt */
167 static void fsl7450_handle_interrupt(struct pt_regs *regs,
168 struct op_counter_config *ctr)
169 {
170 unsigned long pc;
171 int is_kernel;
172 int val;
173 int i;
175 /* set the PMM bit (see comment below) */
176 mtmsr(mfmsr() | MSR_PMM);
178 pc = mfspr(SPRN_SIAR);
179 is_kernel = is_kernel_addr(pc);
181 for (i = 0; i < NUM_CTRS; ++i) {
182 val = ctr_read(i);
183 if (val < 0) {
184 if (oprofile_running && ctr[i].enabled) {
185 oprofile_add_ext_sample(pc, regs, i, is_kernel);
186 ctr_write(i, reset_value[i]);
187 } else {
188 ctr_write(i, 0);
189 }
190 }
191 }
193 /* The freeze bit was set by the interrupt. */
194 /* Clear the freeze bit, and reenable the interrupt.
195 * The counters won't actually start until the rfi clears
196 * the PMM bit */
197 pmc_start_ctrs();
198 }
200 struct op_powerpc_model op_model_7450= {
201 .reg_setup = fsl7450_reg_setup,
202 .cpu_setup = fsl7450_cpu_setup,
203 .start = fsl7450_start,
204 .stop = fsl7450_stop,
205 .handle_interrupt = fsl7450_handle_interrupt,
206 };