ia64/linux-2.6.18-xen.hg

view drivers/pci/pci.h @ 882:8dec4aa9b8b9

PCI pass through: PCIe IO space multiplexing

This is required for more than 16 HVM domain to boot from
PCIe pass through device.

Linux as dom0 exclusively assigns IO space to downstream PCI bridges
and the assignment unit of PCI bridge IO space is 4K. So the only up
to 16 PCIe device can be accessed via IO space within 64K IO ports.
PCI expansion ROM BIOS often uses IO port access to boot from the
device, so on virtualized environment, it means only up to 16 guest
domain can boot from pass-through device.

This patch allows PCIe IO space sharing of pass-through device.
- reassign IO space of PCIe devices specified by
"guestiomuldev=[<segment>:]<bus>:<dev>[,[<segment:><bus>:dev]][,...]"
to be shared.
This is implemented as Linux PCI quirk fixup.

The sharing unit is PCIe switch. Ie IO space of the end point
devices under the same switch will be shared. If there are more than
one switches, two areas of IO space will be used.

- And the driver which arbitrates the accesses to the multiplexed PCIe
IO space. Later qemu-dm will use this.

Limitation:
IO port of IO shared devices can't be accessed from dom0 Linux device
driver. But this wouldn't be a big issue because PCIe specification
discourages the use of IO space and recommends that IO space should be
used only for bootable device with ROM code. OS device driver should
work without IO space access.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu May 28 09:57:49 2009 +0100 (2009-05-28)
parents a3ad7a5f2dcd
children b998614e2e2a
line source
1 /* Functions internal to the PCI core code */
3 extern int pci_uevent(struct device *dev, char **envp, int num_envp,
4 char *buffer, int buffer_size);
5 extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
6 extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
7 extern void pci_cleanup_rom(struct pci_dev *dev);
8 extern int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
9 resource_size_t size, resource_size_t align,
10 resource_size_t min, unsigned int type_mask,
11 void (*alignf)(void *, struct resource *,
12 resource_size_t, resource_size_t),
13 void *alignf_data);
14 /* Firmware callbacks */
15 extern int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
16 extern int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t state);
18 extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
20 extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
21 extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
22 extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
23 extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
24 extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
25 extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
27 /* PCI /proc functions */
28 #ifdef CONFIG_PROC_FS
29 extern int pci_proc_attach_device(struct pci_dev *dev);
30 extern int pci_proc_detach_device(struct pci_dev *dev);
31 extern int pci_proc_detach_bus(struct pci_bus *bus);
32 #else
33 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
34 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
35 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
36 #endif
38 /* Functions for PCI Hotplug drivers to use */
39 extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
40 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
42 extern void pci_remove_legacy_files(struct pci_bus *bus);
44 /* Lock for read/write access to pci device and bus lists */
45 extern struct rw_semaphore pci_bus_sem;
47 #ifdef CONFIG_X86_IO_APIC
48 extern int pci_msi_quirk;
49 #else
50 #define pci_msi_quirk 0
51 #endif
52 extern unsigned int pci_pm_d3_delay;
53 #ifdef CONFIG_PCI_MSI
54 void disable_msi_mode(struct pci_dev *dev, int pos, int type);
55 void pci_no_msi(void);
56 #else
57 static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { }
58 static inline void pci_no_msi(void) { }
59 #endif
60 #if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM)
61 int pci_save_msi_state(struct pci_dev *dev);
62 int pci_save_msix_state(struct pci_dev *dev);
63 void pci_restore_msi_state(struct pci_dev *dev);
64 void pci_restore_msix_state(struct pci_dev *dev);
65 #else
66 static inline int pci_save_msi_state(struct pci_dev *dev) { return 0; }
67 static inline int pci_save_msix_state(struct pci_dev *dev) { return 0; }
68 static inline void pci_restore_msi_state(struct pci_dev *dev) {}
69 static inline void pci_restore_msix_state(struct pci_dev *dev) {}
70 #endif
71 static inline int pci_no_d1d2(struct pci_dev *dev)
72 {
73 unsigned int parent_dstates = 0;
75 if (dev->bus->self)
76 parent_dstates = dev->bus->self->no_d1d2;
77 return (dev->no_d1d2 || parent_dstates);
79 }
80 extern int pcie_mch_quirk;
81 extern struct device_attribute pci_dev_attrs[];
82 extern struct class_device_attribute class_device_attr_cpuaffinity;
84 /**
85 * pci_match_one_device - Tell if a PCI device structure has a matching
86 * PCI device id structure
87 * @id: single PCI device id structure to match
88 * @dev: the PCI device structure to match against
89 *
90 * Returns the matching pci_device_id structure or %NULL if there is no match.
91 */
92 static inline const struct pci_device_id *
93 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
94 {
95 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
96 (id->device == PCI_ANY_ID || id->device == dev->device) &&
97 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
98 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
99 !((id->class ^ dev->class) & id->class_mask))
100 return id;
101 return NULL;
102 }
104 #ifdef CONFIG_PCI_REASSIGN
105 extern void pci_disable_bridge_window(struct pci_dev *dev);
106 #endif
107 #ifdef CONFIG_PCI_GUESTDEV
108 extern int pci_is_reassigndev(struct pci_dev *dev);
109 #else
110 #define pci_is_reassigndev(dev) 0
111 #endif
113 #ifdef CONFIG_PCI_GUESTDEV
114 int pci_is_guestdev_to_reassign(struct pci_dev *dev);
115 #endif /* CONFIG_PCI_GUESTDEV */
117 enum pci_bar_type {
118 pci_bar_unknown, /* Standard PCI BAR probe */
119 pci_bar_io, /* An io port BAR */
120 pci_bar_mem32, /* A 32-bit memory BAR */
121 pci_bar_mem64, /* A 64-bit memory BAR */
122 };
124 extern int pci_setup_device(struct pci_dev *dev);
125 extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
126 struct resource *res, unsigned int reg);
127 extern int pci_resource_bar(struct pci_dev *dev, int resno,
128 enum pci_bar_type *type);
129 extern void pci_enable_ari(struct pci_dev *dev);
130 /**
131 * pci_ari_enabled - query ARI forwarding status
132 * @bus: the PCI bus
133 *
134 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
135 */
136 static inline int pci_ari_enabled(struct pci_bus *bus)
137 {
138 return bus->self && bus->self->ari_enabled;
139 }
141 /* Single Root I/O Virtualization */
142 struct pci_sriov {
143 int pos; /* capability position */
144 int nres; /* number of resources */
145 u32 cap; /* SR-IOV Capabilities */
146 u16 ctrl; /* SR-IOV Control */
147 u16 total; /* total VFs associated with the PF */
148 u16 initial; /* initial VFs associated with the PF */
149 u16 nr_virtfn; /* number of VFs available */
150 u16 offset; /* first VF Routing ID offset */
151 u16 stride; /* following VF stride */
152 u32 pgsz; /* page size for BAR alignment */
153 u8 link; /* Function Dependency Link */
154 struct pci_dev *dev; /* lowest numbered PF */
155 struct pci_dev *self; /* this PF */
156 struct mutex lock; /* lock for VF bus */
157 };
159 #ifdef CONFIG_PCI_IOV
160 extern int pci_iov_init(struct pci_dev *dev);
161 extern void pci_iov_release(struct pci_dev *dev);
162 extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
163 enum pci_bar_type *type);
164 extern void pci_restore_iov_state(struct pci_dev *dev);
165 extern int pci_iov_bus_range(struct pci_bus *bus);
166 #else
167 static inline int pci_iov_init(struct pci_dev *dev)
168 {
169 return -ENODEV;
170 }
171 static inline void pci_iov_release(struct pci_dev *dev)
173 {
174 }
175 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
176 enum pci_bar_type *type)
177 {
178 return 0;
179 }
180 static inline void pci_restore_iov_state(struct pci_dev *dev)
181 {
182 }
183 static inline int pci_iov_bus_range(struct pci_bus *bus)
184 {
185 return 0;
186 }
187 #endif /* CONFIG_PCI_IOV */