ia64/linux-2.6.18-xen.hg

view drivers/pci/pci.c @ 882:8dec4aa9b8b9

PCI pass through: PCIe IO space multiplexing

This is required for more than 16 HVM domain to boot from
PCIe pass through device.

Linux as dom0 exclusively assigns IO space to downstream PCI bridges
and the assignment unit of PCI bridge IO space is 4K. So the only up
to 16 PCIe device can be accessed via IO space within 64K IO ports.
PCI expansion ROM BIOS often uses IO port access to boot from the
device, so on virtualized environment, it means only up to 16 guest
domain can boot from pass-through device.

This patch allows PCIe IO space sharing of pass-through device.
- reassign IO space of PCIe devices specified by
"guestiomuldev=[<segment>:]<bus>:<dev>[,[<segment:><bus>:dev]][,...]"
to be shared.
This is implemented as Linux PCI quirk fixup.

The sharing unit is PCIe switch. Ie IO space of the end point
devices under the same switch will be shared. If there are more than
one switches, two areas of IO space will be used.

- And the driver which arbitrates the accesses to the multiplexed PCIe
IO space. Later qemu-dm will use this.

Limitation:
IO port of IO shared devices can't be accessed from dom0 Linux device
driver. But this wouldn't be a big issue because PCIe specification
discourages the use of IO space and recommends that IO space should be
used only for bootable device with ROM code. OS device driver should
work without IO space access.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu May 28 09:57:49 2009 +0100 (2009-05-28)
parents 5ad6b350e4ab
children
line source
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
20 #include "pci.h"
22 unsigned int pci_pm_d3_delay = 10;
24 /**
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
27 *
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
30 */
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
33 {
34 struct list_head *tmp;
35 unsigned char max, n;
37 max = bus->subordinate;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
40 if(n > max)
41 max = n;
42 }
43 return max;
44 }
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
47 #if 0
48 /**
49 * pci_max_busnr - returns maximum PCI bus number
50 *
51 * Returns the highest PCI bus number present in the system global list of
52 * PCI buses.
53 */
54 unsigned char __devinit
55 pci_max_busnr(void)
56 {
57 struct pci_bus *bus = NULL;
58 unsigned char max, n;
60 max = 0;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
63 if(n > max)
64 max = n;
65 }
66 return max;
67 }
69 #endif /* 0 */
71 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
72 {
73 u8 id;
74 int ttl = 48;
76 while (ttl--) {
77 pci_bus_read_config_byte(bus, devfn, pos, &pos);
78 if (pos < 0x40)
79 break;
80 pos &= ~3;
81 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
82 &id);
83 if (id == 0xff)
84 break;
85 if (id == cap)
86 return pos;
87 pos += PCI_CAP_LIST_NEXT;
88 }
89 return 0;
90 }
92 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
93 {
94 return __pci_find_next_cap(dev->bus, dev->devfn,
95 pos + PCI_CAP_LIST_NEXT, cap);
96 }
97 EXPORT_SYMBOL_GPL(pci_find_next_capability);
99 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
100 {
101 u16 status;
102 u8 pos;
104 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
105 if (!(status & PCI_STATUS_CAP_LIST))
106 return 0;
108 switch (hdr_type) {
109 case PCI_HEADER_TYPE_NORMAL:
110 case PCI_HEADER_TYPE_BRIDGE:
111 pos = PCI_CAPABILITY_LIST;
112 break;
113 case PCI_HEADER_TYPE_CARDBUS:
114 pos = PCI_CB_CAPABILITY_LIST;
115 break;
116 default:
117 return 0;
118 }
119 return __pci_find_next_cap(bus, devfn, pos, cap);
120 }
122 /**
123 * pci_find_capability - query for devices' capabilities
124 * @dev: PCI device to query
125 * @cap: capability code
126 *
127 * Tell if a device supports a given PCI capability.
128 * Returns the address of the requested capability structure within the
129 * device's PCI configuration space or 0 in case the device does not
130 * support it. Possible values for @cap:
131 *
132 * %PCI_CAP_ID_PM Power Management
133 * %PCI_CAP_ID_AGP Accelerated Graphics Port
134 * %PCI_CAP_ID_VPD Vital Product Data
135 * %PCI_CAP_ID_SLOTID Slot Identification
136 * %PCI_CAP_ID_MSI Message Signalled Interrupts
137 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
138 * %PCI_CAP_ID_PCIX PCI-X
139 * %PCI_CAP_ID_EXP PCI Express
140 */
141 int pci_find_capability(struct pci_dev *dev, int cap)
142 {
143 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
144 }
146 /**
147 * pci_bus_find_capability - query for devices' capabilities
148 * @bus: the PCI bus to query
149 * @devfn: PCI device to query
150 * @cap: capability code
151 *
152 * Like pci_find_capability() but works for pci devices that do not have a
153 * pci_dev structure set up yet.
154 *
155 * Returns the address of the requested capability structure within the
156 * device's PCI configuration space or 0 in case the device does not
157 * support it.
158 */
159 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
160 {
161 u8 hdr_type;
163 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
165 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
166 }
168 /**
169 * pci_find_ext_capability - Find an extended capability
170 * @dev: PCI device to query
171 * @cap: capability code
172 *
173 * Returns the address of the requested extended capability structure
174 * within the device's PCI configuration space or 0 if the device does
175 * not support it. Possible values for @cap:
176 *
177 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
178 * %PCI_EXT_CAP_ID_VC Virtual Channel
179 * %PCI_EXT_CAP_ID_DSN Device Serial Number
180 * %PCI_EXT_CAP_ID_PWR Power Budgeting
181 */
182 int pci_find_ext_capability(struct pci_dev *dev, int cap)
183 {
184 u32 header;
185 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
186 int pos = 0x100;
188 if (dev->cfg_size <= 256)
189 return 0;
191 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
192 return 0;
194 /*
195 * If we have no capabilities, this is indicated by cap ID,
196 * cap version and next pointer all being 0.
197 */
198 if (header == 0)
199 return 0;
201 while (ttl-- > 0) {
202 if (PCI_EXT_CAP_ID(header) == cap)
203 return pos;
205 pos = PCI_EXT_CAP_NEXT(header);
206 if (pos < 0x100)
207 break;
209 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
210 break;
211 }
213 return 0;
214 }
215 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
217 /**
218 * pci_find_parent_resource - return resource region of parent bus of given region
219 * @dev: PCI device structure contains resources to be searched
220 * @res: child resource record for which parent is sought
221 *
222 * For given resource region of given device, return the resource
223 * region of parent bus the given region is contained in or where
224 * it should be allocated from.
225 */
226 struct resource *
227 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
228 {
229 const struct pci_bus *bus = dev->bus;
230 int i;
231 struct resource *best = NULL;
233 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
234 struct resource *r = bus->resource[i];
235 if (!r)
236 continue;
237 if (res->start && !(res->start >= r->start && res->end <= r->end))
238 continue; /* Not contained */
239 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
240 continue; /* Wrong type */
241 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
242 return r; /* Exact match */
243 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
244 best = r; /* Approximating prefetchable by non-prefetchable */
245 }
246 return best;
247 }
249 /**
250 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
251 * @dev: PCI device to have its BARs restored
252 *
253 * Restore the BAR values for a given device, so as to make it
254 * accessible by its driver.
255 */
256 void
257 pci_restore_bars(struct pci_dev *dev)
258 {
259 int i;
261 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
262 pci_update_resource(dev, i);
263 }
265 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
267 /**
268 * pci_set_power_state - Set the power state of a PCI device
269 * @dev: PCI device to be suspended
270 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
271 *
272 * Transition a device to a new power state, using the Power Management
273 * Capabilities in the device's config space.
274 *
275 * RETURN VALUE:
276 * -EINVAL if trying to enter a lower state than we're already in.
277 * 0 if we're already in the requested state.
278 * -EIO if device does not support PCI PM.
279 * 0 if we can successfully change the power state.
280 */
281 int
282 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
283 {
284 int pm, need_restore = 0;
285 u16 pmcsr, pmc;
287 /* bound the state we're entering */
288 if (state > PCI_D3hot)
289 state = PCI_D3hot;
291 /* Validate current state:
292 * Can enter D0 from any state, but if we can only go deeper
293 * to sleep if we're already in a low power state
294 */
295 if (state != PCI_D0 && dev->current_state > state) {
296 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
297 __FUNCTION__, pci_name(dev), state, dev->current_state);
298 return -EINVAL;
299 } else if (dev->current_state == state)
300 return 0; /* we're already there */
302 /*
303 * If the device or the parent bridge can't support PCI PM, ignore
304 * the request if we're doing anything besides putting it into D0
305 * (which would only happen on boot).
306 */
307 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
308 return 0;
310 /* find PCI PM capability in list */
311 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
313 /* abort if the device doesn't support PM capabilities */
314 if (!pm)
315 return -EIO;
317 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
318 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
319 printk(KERN_DEBUG
320 "PCI: %s has unsupported PM cap regs version (%u)\n",
321 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
322 return -EIO;
323 }
325 /* check if this device supports the desired state */
326 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
327 return -EIO;
328 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
329 return -EIO;
331 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
333 /* If we're (effectively) in D3, force entire word to 0.
334 * This doesn't affect PME_Status, disables PME_En, and
335 * sets PowerState to 0.
336 */
337 switch (dev->current_state) {
338 case PCI_D0:
339 case PCI_D1:
340 case PCI_D2:
341 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
342 pmcsr |= state;
343 break;
344 case PCI_UNKNOWN: /* Boot-up */
345 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
346 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
347 need_restore = 1;
348 /* Fall-through: force to D0 */
349 default:
350 pmcsr = 0;
351 break;
352 }
354 /* enter specified state */
355 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
357 /* Mandatory power management transition delays */
358 /* see PCI PM 1.1 5.6.1 table 18 */
359 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
360 msleep(pci_pm_d3_delay);
361 else if (state == PCI_D2 || dev->current_state == PCI_D2)
362 udelay(200);
364 /*
365 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
366 * Firmware method after native method ?
367 */
368 if (platform_pci_set_power_state)
369 platform_pci_set_power_state(dev, state);
371 dev->current_state = state;
373 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
374 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
375 * from D3hot to D0 _may_ perform an internal reset, thereby
376 * going to "D0 Uninitialized" rather than "D0 Initialized".
377 * For example, at least some versions of the 3c905B and the
378 * 3c556B exhibit this behaviour.
379 *
380 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
381 * devices in a D3hot state at boot. Consequently, we need to
382 * restore at least the BARs so that the device will be
383 * accessible to its driver.
384 */
385 if (need_restore)
386 pci_restore_bars(dev);
388 return 0;
389 }
391 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
393 /**
394 * pci_choose_state - Choose the power state of a PCI device
395 * @dev: PCI device to be suspended
396 * @state: target sleep state for the whole system. This is the value
397 * that is passed to suspend() function.
398 *
399 * Returns PCI power state suitable for given device and given system
400 * message.
401 */
403 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
404 {
405 int ret;
407 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
408 return PCI_D0;
410 if (platform_pci_choose_state) {
411 ret = platform_pci_choose_state(dev, state);
412 if (ret >= 0)
413 state.event = ret;
414 }
416 switch (state.event) {
417 case PM_EVENT_ON:
418 return PCI_D0;
419 case PM_EVENT_FREEZE:
420 case PM_EVENT_SUSPEND:
421 return PCI_D3hot;
422 default:
423 printk("They asked me for state %d\n", state.event);
424 BUG();
425 }
426 return PCI_D0;
427 }
429 EXPORT_SYMBOL(pci_choose_state);
431 #define PCI_EXP_SAVE_REGS 7
433 static int pci_save_pcie_state(struct pci_dev *dev)
434 {
435 int pos, i = 0;
436 struct pci_cap_saved_state *save_state;
437 u16 *cap;
439 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
440 if (pos <= 0)
441 return 0;
443 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
444 if (!save_state) {
445 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
446 return -ENOMEM;
447 }
448 cap = (u16 *)&save_state->data[0];
450 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
451 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
452 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
453 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
454 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
455 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
456 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
458 return 0;
459 }
461 static void pci_restore_pcie_state(struct pci_dev *dev)
462 {
463 int i = 0, pos;
464 struct pci_cap_saved_state *save_state;
465 u16 *cap;
467 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
468 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
469 if (!save_state || pos <= 0)
470 return;
471 cap = (u16 *)&save_state->data[0];
473 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
474 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
475 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
476 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
477 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
478 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
479 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
480 }
483 static int pci_save_pcix_state(struct pci_dev *dev)
484 {
485 int pos;
486 struct pci_cap_saved_state *save_state;
488 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
489 if (pos <= 0)
490 return 0;
492 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
493 if (!save_state) {
494 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
495 return -ENOMEM;
496 }
498 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
500 return 0;
501 }
503 static void pci_restore_pcix_state(struct pci_dev *dev)
504 {
505 int i = 0, pos;
506 struct pci_cap_saved_state *save_state;
507 u16 *cap;
509 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
510 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
511 if (!save_state || pos <= 0)
512 return;
513 cap = (u16 *)&save_state->data[0];
515 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
516 }
519 /**
520 * pci_save_state - save the PCI configuration space of a device before suspending
521 * @dev: - PCI device that we're dealing with
522 */
523 int
524 pci_save_state(struct pci_dev *dev)
525 {
526 int i;
527 /* XXX: 100% dword access ok here? */
528 for (i = 0; i < 16; i++)
529 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
530 if ((i = pci_save_msi_state(dev)) != 0)
531 return i;
532 if ((i = pci_save_msix_state(dev)) != 0)
533 return i;
534 if ((i = pci_save_pcie_state(dev)) != 0)
535 return i;
536 if ((i = pci_save_pcix_state(dev)) != 0)
537 return i;
539 return 0;
540 }
542 /**
543 * pci_restore_state - Restore the saved state of a PCI device
544 * @dev: - PCI device that we're dealing with
545 */
546 int
547 pci_restore_state(struct pci_dev *dev)
548 {
549 int i;
550 int val;
552 /* PCI Express register must be restored first */
553 pci_restore_pcie_state(dev);
555 /*
556 * The Base Address register should be programmed before the command
557 * register(s)
558 */
559 for (i = 15; i >= 0; i--) {
560 pci_read_config_dword(dev, i * 4, &val);
561 if (val != dev->saved_config_space[i]) {
562 printk(KERN_DEBUG "PM: Writing back config space on "
563 "device %s at offset %x (was %x, writing %x)\n",
564 pci_name(dev), i,
565 val, (int)dev->saved_config_space[i]);
566 pci_write_config_dword(dev,i * 4,
567 dev->saved_config_space[i]);
568 }
569 }
570 pci_restore_pcix_state(dev);
571 pci_restore_msi_state(dev);
572 pci_restore_msix_state(dev);
573 pci_restore_iov_state(dev);
575 return 0;
576 }
578 /**
579 * pci_enable_device_bars - Initialize some of a device for use
580 * @dev: PCI device to be initialized
581 * @bars: bitmask of BAR's that must be configured
582 *
583 * Initialize device before it's used by a driver. Ask low-level code
584 * to enable selected I/O and memory resources. Wake up the device if it
585 * was suspended. Beware, this function can fail.
586 */
588 int
589 pci_enable_device_bars(struct pci_dev *dev, int bars)
590 {
591 int err;
593 err = pci_set_power_state(dev, PCI_D0);
594 if (err < 0 && err != -EIO)
595 return err;
596 err = pcibios_enable_device(dev, bars);
597 if (err < 0)
598 return err;
599 return 0;
600 }
602 /**
603 * pci_enable_device - Initialize device before it's used by a driver.
604 * @dev: PCI device to be initialized
605 *
606 * Initialize device before it's used by a driver. Ask low-level code
607 * to enable I/O and memory. Wake up the device if it was suspended.
608 * Beware, this function can fail.
609 */
610 int
611 pci_enable_device(struct pci_dev *dev)
612 {
613 int err;
615 if (dev->is_enabled)
616 return 0;
618 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
619 if (err)
620 return err;
621 pci_fixup_device(pci_fixup_enable, dev);
622 dev->is_enabled = 1;
623 return 0;
624 }
626 /**
627 * pcibios_disable_device - disable arch specific PCI resources for device dev
628 * @dev: the PCI device to disable
629 *
630 * Disables architecture specific PCI resources for the device. This
631 * is the default implementation. Architecture implementations can
632 * override this.
633 */
634 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
636 /**
637 * pci_disable_device - Disable PCI device after use
638 * @dev: PCI device to be disabled
639 *
640 * Signal to the system that the PCI device is not in use by the system
641 * anymore. This only involves disabling PCI bus-mastering, if active.
642 */
643 void
644 pci_disable_device(struct pci_dev *dev)
645 {
646 u16 pci_command;
648 if (dev->msi_enabled)
649 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
650 PCI_CAP_ID_MSI);
651 if (dev->msix_enabled)
652 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
653 PCI_CAP_ID_MSIX);
655 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
656 if (pci_command & PCI_COMMAND_MASTER) {
657 pci_command &= ~PCI_COMMAND_MASTER;
658 pci_write_config_word(dev, PCI_COMMAND, pci_command);
659 }
660 dev->is_busmaster = 0;
662 pcibios_disable_device(dev);
663 dev->is_enabled = 0;
664 }
666 /**
667 * pci_enable_wake - enable device to generate PME# when suspended
668 * @dev: - PCI device to operate on
669 * @state: - Current state of device.
670 * @enable: - Flag to enable or disable generation
671 *
672 * Set the bits in the device's PM Capabilities to generate PME# when
673 * the system is suspended.
674 *
675 * -EIO is returned if device doesn't have PM Capabilities.
676 * -EINVAL is returned if device supports it, but can't generate wake events.
677 * 0 if operation is successful.
678 *
679 */
680 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
681 {
682 int pm;
683 u16 value;
685 /* find PCI PM capability in list */
686 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
688 /* If device doesn't support PM Capabilities, but request is to disable
689 * wake events, it's a nop; otherwise fail */
690 if (!pm)
691 return enable ? -EIO : 0;
693 /* Check device's ability to generate PME# */
694 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
696 value &= PCI_PM_CAP_PME_MASK;
697 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
699 /* Check if it can generate PME# from requested state. */
700 if (!value || !(value & (1 << state)))
701 return enable ? -EINVAL : 0;
703 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
705 /* Clear PME_Status by writing 1 to it and enable PME# */
706 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
708 if (!enable)
709 value &= ~PCI_PM_CTRL_PME_ENABLE;
711 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
713 return 0;
714 }
716 /**
717 * pci_add_save_buffer - allocate buffer for saving given capability registers
718 * @dev: the PCI device
719 * @cap: the capability to allocate the buffer for
720 * @size: requested size of the buffer
721 */
722 static int pci_add_cap_save_buffer(
723 struct pci_dev *dev, char cap, unsigned int size)
724 {
725 int pos;
726 struct pci_cap_saved_state *save_state;
728 pos = pci_find_capability(dev, cap);
729 if (pos <= 0)
730 return 0;
732 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
733 if (!save_state)
734 return -ENOMEM;
736 save_state->cap_nr = cap;
737 pci_add_saved_cap(dev, save_state);
739 return 0;
740 }
742 /**
743 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
744 * @dev: the PCI device
745 */
746 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
747 {
748 int error;
750 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
751 PCI_EXP_SAVE_REGS * sizeof(u16));
752 if (error)
753 dev_err(&dev->dev,
754 "unable to preallocate PCI Express save buffer\n");
756 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
757 if (error)
758 dev_err(&dev->dev,
759 "unable to preallocate PCI-X save buffer\n");
760 }
762 /**
763 * pci_enable_ari - enable ARI forwarding if hardware support it
764 * @dev: the PCI device
765 */
766 void pci_enable_ari(struct pci_dev *dev)
767 {
768 int pos;
769 u32 cap;
770 u16 ctrl;
771 struct pci_dev *bridge;
773 if (dev->devfn)
774 return;
776 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
777 if (!pos)
778 return;
780 bridge = dev->bus->self;
781 if (!bridge)
782 return;
784 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
785 if (!pos)
786 return;
788 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
789 if (!(cap & PCI_EXP_DEVCAP2_ARI))
790 return;
792 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
793 ctrl |= PCI_EXP_DEVCTL2_ARI;
794 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
796 bridge->ari_enabled = 1;
797 }
799 int
800 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
801 {
802 u8 pin;
804 pin = dev->pin;
805 if (!pin)
806 return -1;
807 pin--;
808 while (dev->bus->self) {
809 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
810 dev = dev->bus->self;
811 }
812 *bridge = dev;
813 return pin;
814 }
816 /**
817 * pci_release_region - Release a PCI bar
818 * @pdev: PCI device whose resources were previously reserved by pci_request_region
819 * @bar: BAR to release
820 *
821 * Releases the PCI I/O and memory resources previously reserved by a
822 * successful call to pci_request_region. Call this function only
823 * after all use of the PCI regions has ceased.
824 */
825 void pci_release_region(struct pci_dev *pdev, int bar)
826 {
827 if (pci_resource_len(pdev, bar) == 0)
828 return;
829 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
830 release_region(pci_resource_start(pdev, bar),
831 pci_resource_len(pdev, bar));
832 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
833 release_mem_region(pci_resource_start(pdev, bar),
834 pci_resource_len(pdev, bar));
835 }
837 /**
838 * pci_request_region - Reserved PCI I/O and memory resource
839 * @pdev: PCI device whose resources are to be reserved
840 * @bar: BAR to be reserved
841 * @res_name: Name to be associated with resource.
842 *
843 * Mark the PCI region associated with PCI device @pdev BR @bar as
844 * being reserved by owner @res_name. Do not access any
845 * address inside the PCI regions unless this call returns
846 * successfully.
847 *
848 * Returns 0 on success, or %EBUSY on error. A warning
849 * message is also printed on failure.
850 */
851 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
852 {
853 if (pci_resource_len(pdev, bar) == 0)
854 return 0;
856 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
857 if (!request_region(pci_resource_start(pdev, bar),
858 pci_resource_len(pdev, bar), res_name))
859 goto err_out;
860 }
861 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
862 if (!request_mem_region(pci_resource_start(pdev, bar),
863 pci_resource_len(pdev, bar), res_name))
864 goto err_out;
865 }
867 return 0;
869 err_out:
870 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
871 "for device %s\n",
872 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
873 bar + 1, /* PCI BAR # */
874 (unsigned long long)pci_resource_len(pdev, bar),
875 (unsigned long long)pci_resource_start(pdev, bar),
876 pci_name(pdev));
877 return -EBUSY;
878 }
881 /**
882 * pci_release_regions - Release reserved PCI I/O and memory resources
883 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
884 *
885 * Releases all PCI I/O and memory resources previously reserved by a
886 * successful call to pci_request_regions. Call this function only
887 * after all use of the PCI regions has ceased.
888 */
890 void pci_release_regions(struct pci_dev *pdev)
891 {
892 int i;
894 for (i = 0; i < 6; i++)
895 pci_release_region(pdev, i);
896 }
898 /**
899 * pci_request_regions - Reserved PCI I/O and memory resources
900 * @pdev: PCI device whose resources are to be reserved
901 * @res_name: Name to be associated with resource.
902 *
903 * Mark all PCI regions associated with PCI device @pdev as
904 * being reserved by owner @res_name. Do not access any
905 * address inside the PCI regions unless this call returns
906 * successfully.
907 *
908 * Returns 0 on success, or %EBUSY on error. A warning
909 * message is also printed on failure.
910 */
911 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
912 {
913 int i;
915 for (i = 0; i < 6; i++)
916 if(pci_request_region(pdev, i, res_name))
917 goto err_out;
918 return 0;
920 err_out:
921 while(--i >= 0)
922 pci_release_region(pdev, i);
924 return -EBUSY;
925 }
927 /**
928 * pci_set_master - enables bus-mastering for device dev
929 * @dev: the PCI device to enable
930 *
931 * Enables bus-mastering on the device and calls pcibios_set_master()
932 * to do the needed arch specific settings.
933 */
934 void
935 pci_set_master(struct pci_dev *dev)
936 {
937 u16 cmd;
939 pci_read_config_word(dev, PCI_COMMAND, &cmd);
940 if (! (cmd & PCI_COMMAND_MASTER)) {
941 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
942 cmd |= PCI_COMMAND_MASTER;
943 pci_write_config_word(dev, PCI_COMMAND, cmd);
944 }
945 dev->is_busmaster = 1;
946 pcibios_set_master(dev);
947 }
949 #ifndef HAVE_ARCH_PCI_MWI
950 /* This can be overridden by arch code. */
951 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
953 /**
954 * pci_generic_prep_mwi - helper function for pci_set_mwi
955 * @dev: the PCI device for which MWI is enabled
956 *
957 * Helper function for generic implementation of pcibios_prep_mwi
958 * function. Originally copied from drivers/net/acenic.c.
959 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
960 *
961 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
962 */
963 static int
964 pci_generic_prep_mwi(struct pci_dev *dev)
965 {
966 u8 cacheline_size;
968 if (!pci_cache_line_size)
969 return -EINVAL; /* The system doesn't support MWI. */
971 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
972 equal to or multiple of the right value. */
973 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
974 if (cacheline_size >= pci_cache_line_size &&
975 (cacheline_size % pci_cache_line_size) == 0)
976 return 0;
978 /* Write the correct value. */
979 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
980 /* Read it back. */
981 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
982 if (cacheline_size == pci_cache_line_size)
983 return 0;
985 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
986 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
988 return -EINVAL;
989 }
990 #endif /* !HAVE_ARCH_PCI_MWI */
992 /**
993 * pci_set_mwi - enables memory-write-invalidate PCI transaction
994 * @dev: the PCI device for which MWI is enabled
995 *
996 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
997 * and then calls @pcibios_set_mwi to do the needed arch specific
998 * operations or a generic mwi-prep function.
999 *
1000 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1001 */
1002 int
1003 pci_set_mwi(struct pci_dev *dev)
1005 int rc;
1006 u16 cmd;
1008 #ifdef HAVE_ARCH_PCI_MWI
1009 rc = pcibios_prep_mwi(dev);
1010 #else
1011 rc = pci_generic_prep_mwi(dev);
1012 #endif
1014 if (rc)
1015 return rc;
1017 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1018 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1019 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
1020 cmd |= PCI_COMMAND_INVALIDATE;
1021 pci_write_config_word(dev, PCI_COMMAND, cmd);
1024 return 0;
1027 /**
1028 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1029 * @dev: the PCI device to disable
1031 * Disables PCI Memory-Write-Invalidate transaction on the device
1032 */
1033 void
1034 pci_clear_mwi(struct pci_dev *dev)
1036 u16 cmd;
1038 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1039 if (cmd & PCI_COMMAND_INVALIDATE) {
1040 cmd &= ~PCI_COMMAND_INVALIDATE;
1041 pci_write_config_word(dev, PCI_COMMAND, cmd);
1045 /**
1046 * pci_intx - enables/disables PCI INTx for device dev
1047 * @pdev: the PCI device to operate on
1048 * @enable: boolean: whether to enable or disable PCI INTx
1050 * Enables/disables PCI INTx for device dev
1051 */
1052 void
1053 pci_intx(struct pci_dev *pdev, int enable)
1055 u16 pci_command, new;
1057 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1059 if (enable) {
1060 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1061 } else {
1062 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1065 if (new != pci_command) {
1066 pci_write_config_word(pdev, PCI_COMMAND, new);
1070 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1071 /*
1072 * These can be overridden by arch-specific implementations
1073 */
1074 int
1075 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1077 if (!pci_dma_supported(dev, mask))
1078 return -EIO;
1080 dev->dma_mask = mask;
1082 return 0;
1085 int
1086 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1088 if (!pci_dma_supported(dev, mask))
1089 return -EIO;
1091 dev->dev.coherent_dma_mask = mask;
1093 return 0;
1095 #endif
1097 /**
1098 * pci_resource_bar - get position of the BAR associated with a resource
1099 * @dev: the PCI device
1100 * @resno: the resource number
1101 * @type: the BAR type to be filled in
1103 * Returns BAR position in config space, or 0 if the BAR is invalid.
1104 */
1105 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
1107 int reg;
1109 if (resno < PCI_ROM_RESOURCE) {
1110 *type = pci_bar_unknown;
1111 return PCI_BASE_ADDRESS_0 + 4 * resno;
1112 } else if (resno == PCI_ROM_RESOURCE) {
1113 *type = pci_bar_mem32;
1114 return dev->rom_base_reg;
1115 } else if (resno < PCI_BRIDGE_RESOURCES) {
1116 /* device specific resource */
1117 reg = pci_iov_resource_bar(dev, resno, type);
1118 if (reg)
1119 return reg;
1122 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
1123 return 0;
1126 static int __devinit pci_init(void)
1128 struct pci_dev *dev = NULL;
1130 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1131 pci_fixup_device(pci_fixup_final, dev);
1133 return 0;
1136 static int __devinit pci_setup(char *str)
1138 while (str) {
1139 char *k = strchr(str, ',');
1140 if (k)
1141 *k++ = 0;
1142 if (*str && (str = pcibios_setup(str)) && *str) {
1143 if (!strcmp(str, "nomsi")) {
1144 pci_no_msi();
1145 } else {
1146 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1147 str);
1150 str = k;
1152 return 1;
1155 device_initcall(pci_init);
1157 __setup("pci=", pci_setup);
1159 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1160 /* FIXME: Some boxes have multiple ISA bridges! */
1161 struct pci_dev *isa_bridge;
1162 EXPORT_SYMBOL(isa_bridge);
1163 #endif
1165 EXPORT_SYMBOL_GPL(pci_restore_bars);
1166 EXPORT_SYMBOL(pci_enable_device_bars);
1167 EXPORT_SYMBOL(pci_enable_device);
1168 EXPORT_SYMBOL(pci_disable_device);
1169 EXPORT_SYMBOL(pci_find_capability);
1170 EXPORT_SYMBOL(pci_bus_find_capability);
1171 EXPORT_SYMBOL(pci_release_regions);
1172 EXPORT_SYMBOL(pci_request_regions);
1173 EXPORT_SYMBOL(pci_release_region);
1174 EXPORT_SYMBOL(pci_request_region);
1175 EXPORT_SYMBOL(pci_set_master);
1176 EXPORT_SYMBOL(pci_set_mwi);
1177 EXPORT_SYMBOL(pci_clear_mwi);
1178 EXPORT_SYMBOL_GPL(pci_intx);
1179 EXPORT_SYMBOL(pci_set_dma_mask);
1180 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1181 EXPORT_SYMBOL(pci_assign_resource);
1182 EXPORT_SYMBOL(pci_find_parent_resource);
1184 EXPORT_SYMBOL(pci_set_power_state);
1185 EXPORT_SYMBOL(pci_save_state);
1186 EXPORT_SYMBOL(pci_restore_state);
1187 EXPORT_SYMBOL(pci_enable_wake);
1189 /* Quirk info */
1191 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1192 EXPORT_SYMBOL(pci_pci_problems);