ia64/linux-2.6.18-xen.hg

view include/asm-m68knommu/m5272sim.h @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
children
line source
1 /****************************************************************************/
3 /*
4 * m5272sim.h -- ColdFire 5272 System Integration Module support.
5 *
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
10 /****************************************************************************/
11 #ifndef m5272sim_h
12 #define m5272sim_h
13 /****************************************************************************/
16 /*
17 * Define the 5272 SIM register set addresses.
18 */
19 #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
20 #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
21 #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
22 #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
23 #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
25 #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
26 #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
27 #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
28 #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
30 #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
31 #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
32 #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
33 #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
35 #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
36 #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
37 #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
38 #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
40 #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
41 #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
42 #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
43 #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
44 #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
45 #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
46 #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
47 #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
48 #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
49 #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
50 #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
51 #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
52 #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
53 #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
54 #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
55 #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
57 #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
58 #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
59 #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
60 #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
61 #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
62 #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
63 #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
64 #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
66 #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
67 #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
68 #define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
69 #define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
70 #define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
71 #define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
72 #define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
73 #define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
74 #define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
77 /****************************************************************************/
78 #endif /* m5272sim_h */