ia64/linux-2.6.18-xen.hg

view drivers/net/tg3.h @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
children
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1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 */
9 #ifndef _T3_H
10 #define _T3_H
12 #define TG3_64BIT_REG_HIGH 0x00UL
13 #define TG3_64BIT_REG_LOW 0x04UL
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
18 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
19 #define BDINFO_FLAGS_DISABLED 0x00000002
20 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
21 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
22 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE 0x10UL
25 #define RX_COPY_THRESHOLD 256
27 #define RX_STD_MAX_SIZE 1536
28 #define RX_STD_MAX_SIZE_5705 512
29 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
31 /* First 256 bytes are a mirror of PCI config space. */
32 #define TG3PCI_VENDOR 0x00000000
33 #define TG3PCI_VENDOR_BROADCOM 0x14e4
34 #define TG3PCI_DEVICE 0x00000002
35 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
36 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
37 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
38 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
39 #define TG3PCI_COMMAND 0x00000004
40 #define TG3PCI_STATUS 0x00000006
41 #define TG3PCI_CCREVID 0x00000008
42 #define TG3PCI_CACHELINESZ 0x0000000c
43 #define TG3PCI_LATTIMER 0x0000000d
44 #define TG3PCI_HEADERTYPE 0x0000000e
45 #define TG3PCI_BIST 0x0000000f
46 #define TG3PCI_BASE0_LOW 0x00000010
47 #define TG3PCI_BASE0_HIGH 0x00000014
48 /* 0x18 --> 0x2c unused */
49 #define TG3PCI_SUBSYSVENID 0x0000002c
50 #define TG3PCI_SUBSYSID 0x0000002e
51 #define TG3PCI_ROMADDR 0x00000030
52 #define TG3PCI_CAPLIST 0x00000034
53 /* 0x35 --> 0x3c unused */
54 #define TG3PCI_IRQ_LINE 0x0000003c
55 #define TG3PCI_IRQ_PIN 0x0000003d
56 #define TG3PCI_MIN_GNT 0x0000003e
57 #define TG3PCI_MAX_LAT 0x0000003f
58 #define TG3PCI_X_CAPS 0x00000040
59 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
60 #define PCIX_CAPS_SPLIT_MASK 0x00700000
61 #define PCIX_CAPS_SPLIT_SHIFT 20
62 #define PCIX_CAPS_BURST_MASK 0x000c0000
63 #define PCIX_CAPS_BURST_SHIFT 18
64 #define PCIX_CAPS_MAX_BURST_CPIOB 2
65 #define TG3PCI_PM_CAP_PTR 0x00000041
66 #define TG3PCI_X_COMMAND 0x00000042
67 #define TG3PCI_X_STATUS 0x00000044
68 #define TG3PCI_PM_CAP_ID 0x00000048
69 #define TG3PCI_VPD_CAP_PTR 0x00000049
70 #define TG3PCI_PM_CAPS 0x0000004a
71 #define TG3PCI_PM_CTRL_STAT 0x0000004c
72 #define TG3PCI_BR_SUPP_EXT 0x0000004e
73 #define TG3PCI_PM_DATA 0x0000004f
74 #define TG3PCI_VPD_CAP_ID 0x00000050
75 #define TG3PCI_MSI_CAP_PTR 0x00000051
76 #define TG3PCI_VPD_ADDR_FLAG 0x00000052
77 #define VPD_ADDR_FLAG_WRITE 0x00008000
78 #define TG3PCI_VPD_DATA 0x00000054
79 #define TG3PCI_MSI_CAP_ID 0x00000058
80 #define TG3PCI_NXT_CAP_PTR 0x00000059
81 #define TG3PCI_MSI_CTRL 0x0000005a
82 #define TG3PCI_MSI_ADDR_LOW 0x0000005c
83 #define TG3PCI_MSI_ADDR_HIGH 0x00000060
84 #define TG3PCI_MSI_DATA 0x00000064
85 /* 0x66 --> 0x68 unused */
86 #define TG3PCI_MISC_HOST_CTRL 0x00000068
87 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
88 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
89 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
90 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
91 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
92 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
93 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
94 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
95 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
96 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
97 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
98 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
99 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
100 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
101 MISC_HOST_CTRL_CHIPREV_SHIFT)
102 #define CHIPREV_ID_5700_A0 0x7000
103 #define CHIPREV_ID_5700_A1 0x7001
104 #define CHIPREV_ID_5700_B0 0x7100
105 #define CHIPREV_ID_5700_B1 0x7101
106 #define CHIPREV_ID_5700_B3 0x7102
107 #define CHIPREV_ID_5700_ALTIMA 0x7104
108 #define CHIPREV_ID_5700_C0 0x7200
109 #define CHIPREV_ID_5701_A0 0x0000
110 #define CHIPREV_ID_5701_B0 0x0100
111 #define CHIPREV_ID_5701_B2 0x0102
112 #define CHIPREV_ID_5701_B5 0x0105
113 #define CHIPREV_ID_5703_A0 0x1000
114 #define CHIPREV_ID_5703_A1 0x1001
115 #define CHIPREV_ID_5703_A2 0x1002
116 #define CHIPREV_ID_5703_A3 0x1003
117 #define CHIPREV_ID_5704_A0 0x2000
118 #define CHIPREV_ID_5704_A1 0x2001
119 #define CHIPREV_ID_5704_A2 0x2002
120 #define CHIPREV_ID_5704_A3 0x2003
121 #define CHIPREV_ID_5705_A0 0x3000
122 #define CHIPREV_ID_5705_A1 0x3001
123 #define CHIPREV_ID_5705_A2 0x3002
124 #define CHIPREV_ID_5705_A3 0x3003
125 #define CHIPREV_ID_5750_A0 0x4000
126 #define CHIPREV_ID_5750_A1 0x4001
127 #define CHIPREV_ID_5750_A3 0x4003
128 #define CHIPREV_ID_5750_C2 0x4202
129 #define CHIPREV_ID_5752_A0_HW 0x5000
130 #define CHIPREV_ID_5752_A0 0x6000
131 #define CHIPREV_ID_5752_A1 0x6001
132 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
133 #define ASIC_REV_5700 0x07
134 #define ASIC_REV_5701 0x00
135 #define ASIC_REV_5703 0x01
136 #define ASIC_REV_5704 0x02
137 #define ASIC_REV_5705 0x03
138 #define ASIC_REV_5750 0x04
139 #define ASIC_REV_5752 0x06
140 #define ASIC_REV_5780 0x08
141 #define ASIC_REV_5714 0x09
142 #define ASIC_REV_5755 0x0a
143 #define ASIC_REV_5787 0x0b
144 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
145 #define CHIPREV_5700_AX 0x70
146 #define CHIPREV_5700_BX 0x71
147 #define CHIPREV_5700_CX 0x72
148 #define CHIPREV_5701_AX 0x00
149 #define CHIPREV_5703_AX 0x10
150 #define CHIPREV_5704_AX 0x20
151 #define CHIPREV_5704_BX 0x21
152 #define CHIPREV_5750_AX 0x40
153 #define CHIPREV_5750_BX 0x41
154 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
155 #define METAL_REV_A0 0x00
156 #define METAL_REV_A1 0x01
157 #define METAL_REV_B0 0x00
158 #define METAL_REV_B1 0x01
159 #define METAL_REV_B2 0x02
160 #define TG3PCI_DMA_RW_CTRL 0x0000006c
161 #define DMA_RWCTRL_MIN_DMA 0x000000ff
162 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
163 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
164 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
165 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
166 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
167 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
168 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
169 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
170 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
171 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
172 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
173 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
174 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
175 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
176 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
177 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
178 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
179 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
180 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
181 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
182 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
183 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
184 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
185 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
186 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
187 #define DMA_RWCTRL_ONE_DMA 0x00004000
188 #define DMA_RWCTRL_READ_WATER 0x00070000
189 #define DMA_RWCTRL_READ_WATER_SHIFT 16
190 #define DMA_RWCTRL_WRITE_WATER 0x00380000
191 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
192 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
193 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
194 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
195 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
196 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
197 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
198 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
199 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
200 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
201 #define TG3PCI_PCISTATE 0x00000070
202 #define PCISTATE_FORCE_RESET 0x00000001
203 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
204 #define PCISTATE_CONV_PCI_MODE 0x00000004
205 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
206 #define PCISTATE_BUS_32BIT 0x00000010
207 #define PCISTATE_ROM_ENABLE 0x00000020
208 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
209 #define PCISTATE_FLAT_VIEW 0x00000100
210 #define PCISTATE_RETRY_SAME_DMA 0x00002000
211 #define TG3PCI_CLOCK_CTRL 0x00000074
212 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
213 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
214 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
215 #define CLOCK_CTRL_ALTCLK 0x00001000
216 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
217 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
218 #define CLOCK_CTRL_625_CORE 0x00100000
219 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
220 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
221 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
222 #define TG3PCI_REG_BASE_ADDR 0x00000078
223 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
224 #define TG3PCI_REG_DATA 0x00000080
225 #define TG3PCI_MEM_WIN_DATA 0x00000084
226 #define TG3PCI_MODE_CTRL 0x00000088
227 #define TG3PCI_MISC_CFG 0x0000008c
228 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
229 /* 0x94 --> 0x98 unused */
230 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
231 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
232 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
233 /* 0xb0 --> 0xb8 unused */
234 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
235 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
236 #define DUAL_MAC_CTRL_ID 0x00000004
237 /* 0xbc --> 0x100 unused */
239 /* 0x100 --> 0x200 unused */
241 /* Mailbox registers */
242 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
243 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
244 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
245 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
246 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
247 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
248 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
249 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
250 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
251 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
252 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
253 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
254 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
255 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
256 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
257 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
263 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
264 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
265 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
266 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
267 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
268 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
269 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
270 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
271 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
272 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
273 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
279 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
280 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
281 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
282 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
283 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
284 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
285 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
286 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
287 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
288 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
289 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
295 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
296 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
297 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
298 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
299 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
300 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
301 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
302 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
303 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
304 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
305 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
307 /* MAC control registers */
308 #define MAC_MODE 0x00000400
309 #define MAC_MODE_RESET 0x00000001
310 #define MAC_MODE_HALF_DUPLEX 0x00000002
311 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
312 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
313 #define MAC_MODE_PORT_MODE_GMII 0x00000008
314 #define MAC_MODE_PORT_MODE_MII 0x00000004
315 #define MAC_MODE_PORT_MODE_NONE 0x00000000
316 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
317 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
318 #define MAC_MODE_TX_BURSTING 0x00000100
319 #define MAC_MODE_MAX_DEFER 0x00000200
320 #define MAC_MODE_LINK_POLARITY 0x00000400
321 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
322 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
323 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
324 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
325 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
326 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
327 #define MAC_MODE_SEND_CONFIGS 0x00020000
328 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
329 #define MAC_MODE_ACPI_ENABLE 0x00080000
330 #define MAC_MODE_MIP_ENABLE 0x00100000
331 #define MAC_MODE_TDE_ENABLE 0x00200000
332 #define MAC_MODE_RDE_ENABLE 0x00400000
333 #define MAC_MODE_FHDE_ENABLE 0x00800000
334 #define MAC_STATUS 0x00000404
335 #define MAC_STATUS_PCS_SYNCED 0x00000001
336 #define MAC_STATUS_SIGNAL_DET 0x00000002
337 #define MAC_STATUS_RCVD_CFG 0x00000004
338 #define MAC_STATUS_CFG_CHANGED 0x00000008
339 #define MAC_STATUS_SYNC_CHANGED 0x00000010
340 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
341 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
342 #define MAC_STATUS_MI_COMPLETION 0x00400000
343 #define MAC_STATUS_MI_INTERRUPT 0x00800000
344 #define MAC_STATUS_AP_ERROR 0x01000000
345 #define MAC_STATUS_ODI_ERROR 0x02000000
346 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
347 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
348 #define MAC_EVENT 0x00000408
349 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
350 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
351 #define MAC_EVENT_MI_COMPLETION 0x00400000
352 #define MAC_EVENT_MI_INTERRUPT 0x00800000
353 #define MAC_EVENT_AP_ERROR 0x01000000
354 #define MAC_EVENT_ODI_ERROR 0x02000000
355 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
356 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
357 #define MAC_LED_CTRL 0x0000040c
358 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
359 #define LED_CTRL_1000MBPS_ON 0x00000002
360 #define LED_CTRL_100MBPS_ON 0x00000004
361 #define LED_CTRL_10MBPS_ON 0x00000008
362 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
363 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
364 #define LED_CTRL_TRAFFIC_LED 0x00000040
365 #define LED_CTRL_1000MBPS_STATUS 0x00000080
366 #define LED_CTRL_100MBPS_STATUS 0x00000100
367 #define LED_CTRL_10MBPS_STATUS 0x00000200
368 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
369 #define LED_CTRL_MODE_MAC 0x00000000
370 #define LED_CTRL_MODE_PHY_1 0x00000800
371 #define LED_CTRL_MODE_PHY_2 0x00001000
372 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
373 #define LED_CTRL_MODE_SHARED 0x00004000
374 #define LED_CTRL_MODE_COMBO 0x00008000
375 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
376 #define LED_CTRL_BLINK_RATE_SHIFT 19
377 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
378 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
379 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
380 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
381 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
382 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
383 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
384 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
385 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
386 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
387 #define MAC_ACPI_MBUF_PTR 0x00000430
388 #define MAC_ACPI_LEN_OFFSET 0x00000434
389 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
390 #define ACPI_LENOFF_LEN_SHIFT 0
391 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
392 #define ACPI_LENOFF_OFF_SHIFT 16
393 #define MAC_TX_BACKOFF_SEED 0x00000438
394 #define TX_BACKOFF_SEED_MASK 0x000003ff
395 #define MAC_RX_MTU_SIZE 0x0000043c
396 #define RX_MTU_SIZE_MASK 0x0000ffff
397 #define MAC_PCS_TEST 0x00000440
398 #define PCS_TEST_PATTERN_MASK 0x000fffff
399 #define PCS_TEST_PATTERN_SHIFT 0
400 #define PCS_TEST_ENABLE 0x00100000
401 #define MAC_TX_AUTO_NEG 0x00000444
402 #define TX_AUTO_NEG_MASK 0x0000ffff
403 #define TX_AUTO_NEG_SHIFT 0
404 #define MAC_RX_AUTO_NEG 0x00000448
405 #define RX_AUTO_NEG_MASK 0x0000ffff
406 #define RX_AUTO_NEG_SHIFT 0
407 #define MAC_MI_COM 0x0000044c
408 #define MI_COM_CMD_MASK 0x0c000000
409 #define MI_COM_CMD_WRITE 0x04000000
410 #define MI_COM_CMD_READ 0x08000000
411 #define MI_COM_READ_FAILED 0x10000000
412 #define MI_COM_START 0x20000000
413 #define MI_COM_BUSY 0x20000000
414 #define MI_COM_PHY_ADDR_MASK 0x03e00000
415 #define MI_COM_PHY_ADDR_SHIFT 21
416 #define MI_COM_REG_ADDR_MASK 0x001f0000
417 #define MI_COM_REG_ADDR_SHIFT 16
418 #define MI_COM_DATA_MASK 0x0000ffff
419 #define MAC_MI_STAT 0x00000450
420 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
421 #define MAC_MI_MODE 0x00000454
422 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
423 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
424 #define MAC_MI_MODE_AUTO_POLL 0x00000010
425 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
426 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
427 #define MAC_AUTO_POLL_STATUS 0x00000458
428 #define MAC_AUTO_POLL_ERROR 0x00000001
429 #define MAC_TX_MODE 0x0000045c
430 #define TX_MODE_RESET 0x00000001
431 #define TX_MODE_ENABLE 0x00000002
432 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
433 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
434 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
435 #define MAC_TX_STATUS 0x00000460
436 #define TX_STATUS_XOFFED 0x00000001
437 #define TX_STATUS_SENT_XOFF 0x00000002
438 #define TX_STATUS_SENT_XON 0x00000004
439 #define TX_STATUS_LINK_UP 0x00000008
440 #define TX_STATUS_ODI_UNDERRUN 0x00000010
441 #define TX_STATUS_ODI_OVERRUN 0x00000020
442 #define MAC_TX_LENGTHS 0x00000464
443 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
444 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
445 #define TX_LENGTHS_IPG_MASK 0x00000f00
446 #define TX_LENGTHS_IPG_SHIFT 8
447 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
448 #define TX_LENGTHS_IPG_CRS_SHIFT 12
449 #define MAC_RX_MODE 0x00000468
450 #define RX_MODE_RESET 0x00000001
451 #define RX_MODE_ENABLE 0x00000002
452 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
453 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
454 #define RX_MODE_KEEP_PAUSE 0x00000010
455 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
456 #define RX_MODE_ACCEPT_RUNTS 0x00000040
457 #define RX_MODE_LEN_CHECK 0x00000080
458 #define RX_MODE_PROMISC 0x00000100
459 #define RX_MODE_NO_CRC_CHECK 0x00000200
460 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
461 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
462 #define MAC_RX_STATUS 0x0000046c
463 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
464 #define RX_STATUS_XOFF_RCVD 0x00000002
465 #define RX_STATUS_XON_RCVD 0x00000004
466 #define MAC_HASH_REG_0 0x00000470
467 #define MAC_HASH_REG_1 0x00000474
468 #define MAC_HASH_REG_2 0x00000478
469 #define MAC_HASH_REG_3 0x0000047c
470 #define MAC_RCV_RULE_0 0x00000480
471 #define MAC_RCV_VALUE_0 0x00000484
472 #define MAC_RCV_RULE_1 0x00000488
473 #define MAC_RCV_VALUE_1 0x0000048c
474 #define MAC_RCV_RULE_2 0x00000490
475 #define MAC_RCV_VALUE_2 0x00000494
476 #define MAC_RCV_RULE_3 0x00000498
477 #define MAC_RCV_VALUE_3 0x0000049c
478 #define MAC_RCV_RULE_4 0x000004a0
479 #define MAC_RCV_VALUE_4 0x000004a4
480 #define MAC_RCV_RULE_5 0x000004a8
481 #define MAC_RCV_VALUE_5 0x000004ac
482 #define MAC_RCV_RULE_6 0x000004b0
483 #define MAC_RCV_VALUE_6 0x000004b4
484 #define MAC_RCV_RULE_7 0x000004b8
485 #define MAC_RCV_VALUE_7 0x000004bc
486 #define MAC_RCV_RULE_8 0x000004c0
487 #define MAC_RCV_VALUE_8 0x000004c4
488 #define MAC_RCV_RULE_9 0x000004c8
489 #define MAC_RCV_VALUE_9 0x000004cc
490 #define MAC_RCV_RULE_10 0x000004d0
491 #define MAC_RCV_VALUE_10 0x000004d4
492 #define MAC_RCV_RULE_11 0x000004d8
493 #define MAC_RCV_VALUE_11 0x000004dc
494 #define MAC_RCV_RULE_12 0x000004e0
495 #define MAC_RCV_VALUE_12 0x000004e4
496 #define MAC_RCV_RULE_13 0x000004e8
497 #define MAC_RCV_VALUE_13 0x000004ec
498 #define MAC_RCV_RULE_14 0x000004f0
499 #define MAC_RCV_VALUE_14 0x000004f4
500 #define MAC_RCV_RULE_15 0x000004f8
501 #define MAC_RCV_VALUE_15 0x000004fc
502 #define RCV_RULE_DISABLE_MASK 0x7fffffff
503 #define MAC_RCV_RULE_CFG 0x00000500
504 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
505 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
506 /* 0x508 --> 0x520 unused */
507 #define MAC_HASHREGU_0 0x00000520
508 #define MAC_HASHREGU_1 0x00000524
509 #define MAC_HASHREGU_2 0x00000528
510 #define MAC_HASHREGU_3 0x0000052c
511 #define MAC_EXTADDR_0_HIGH 0x00000530
512 #define MAC_EXTADDR_0_LOW 0x00000534
513 #define MAC_EXTADDR_1_HIGH 0x00000538
514 #define MAC_EXTADDR_1_LOW 0x0000053c
515 #define MAC_EXTADDR_2_HIGH 0x00000540
516 #define MAC_EXTADDR_2_LOW 0x00000544
517 #define MAC_EXTADDR_3_HIGH 0x00000548
518 #define MAC_EXTADDR_3_LOW 0x0000054c
519 #define MAC_EXTADDR_4_HIGH 0x00000550
520 #define MAC_EXTADDR_4_LOW 0x00000554
521 #define MAC_EXTADDR_5_HIGH 0x00000558
522 #define MAC_EXTADDR_5_LOW 0x0000055c
523 #define MAC_EXTADDR_6_HIGH 0x00000560
524 #define MAC_EXTADDR_6_LOW 0x00000564
525 #define MAC_EXTADDR_7_HIGH 0x00000568
526 #define MAC_EXTADDR_7_LOW 0x0000056c
527 #define MAC_EXTADDR_8_HIGH 0x00000570
528 #define MAC_EXTADDR_8_LOW 0x00000574
529 #define MAC_EXTADDR_9_HIGH 0x00000578
530 #define MAC_EXTADDR_9_LOW 0x0000057c
531 #define MAC_EXTADDR_10_HIGH 0x00000580
532 #define MAC_EXTADDR_10_LOW 0x00000584
533 #define MAC_EXTADDR_11_HIGH 0x00000588
534 #define MAC_EXTADDR_11_LOW 0x0000058c
535 #define MAC_SERDES_CFG 0x00000590
536 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
537 #define MAC_SERDES_STAT 0x00000594
538 /* 0x598 --> 0x5b0 unused */
539 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
540 #define SERDES_RX_SIG_DETECT 0x00000400
541 #define SG_DIG_CTRL 0x000005b0
542 #define SG_DIG_USING_HW_AUTONEG 0x80000000
543 #define SG_DIG_SOFT_RESET 0x40000000
544 #define SG_DIG_DISABLE_LINKRDY 0x20000000
545 #define SG_DIG_CRC16_CLEAR_N 0x01000000
546 #define SG_DIG_EN10B 0x00800000
547 #define SG_DIG_CLEAR_STATUS 0x00400000
548 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
549 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
550 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
551 #define SG_DIG_SPEED_STATUS_SHIFT 18
552 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
553 #define SG_DIG_RESTART_AUTONEG 0x00010000
554 #define SG_DIG_FIBER_MODE 0x00008000
555 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
556 #define SG_DIG_PAUSE_MASK 0x00001800
557 #define SG_DIG_GBIC_ENABLE 0x00000400
558 #define SG_DIG_CHECK_END_ENABLE 0x00000200
559 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
560 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
561 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
562 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
563 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
564 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
565 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
566 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
567 #define SG_DIG_LOOPBACK 0x00000001
568 #define SG_DIG_STATUS 0x000005b4
569 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
570 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
571 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
572 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
573 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
574 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
575 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
576 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
577 #define SG_DIG_COMMA_DETECTOR 0x00000008
578 #define SG_DIG_MAC_ACK_STATUS 0x00000004
579 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
580 #define SG_DIG_AUTONEG_ERROR 0x00000001
581 /* 0x5b8 --> 0x600 unused */
582 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
583 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
584 /* 0x624 --> 0x800 unused */
585 #define MAC_TX_STATS_OCTETS 0x00000800
586 #define MAC_TX_STATS_RESV1 0x00000804
587 #define MAC_TX_STATS_COLLISIONS 0x00000808
588 #define MAC_TX_STATS_XON_SENT 0x0000080c
589 #define MAC_TX_STATS_XOFF_SENT 0x00000810
590 #define MAC_TX_STATS_RESV2 0x00000814
591 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
592 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
593 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
594 #define MAC_TX_STATS_DEFERRED 0x00000824
595 #define MAC_TX_STATS_RESV3 0x00000828
596 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
597 #define MAC_TX_STATS_LATE_COL 0x00000830
598 #define MAC_TX_STATS_RESV4_1 0x00000834
599 #define MAC_TX_STATS_RESV4_2 0x00000838
600 #define MAC_TX_STATS_RESV4_3 0x0000083c
601 #define MAC_TX_STATS_RESV4_4 0x00000840
602 #define MAC_TX_STATS_RESV4_5 0x00000844
603 #define MAC_TX_STATS_RESV4_6 0x00000848
604 #define MAC_TX_STATS_RESV4_7 0x0000084c
605 #define MAC_TX_STATS_RESV4_8 0x00000850
606 #define MAC_TX_STATS_RESV4_9 0x00000854
607 #define MAC_TX_STATS_RESV4_10 0x00000858
608 #define MAC_TX_STATS_RESV4_11 0x0000085c
609 #define MAC_TX_STATS_RESV4_12 0x00000860
610 #define MAC_TX_STATS_RESV4_13 0x00000864
611 #define MAC_TX_STATS_RESV4_14 0x00000868
612 #define MAC_TX_STATS_UCAST 0x0000086c
613 #define MAC_TX_STATS_MCAST 0x00000870
614 #define MAC_TX_STATS_BCAST 0x00000874
615 #define MAC_TX_STATS_RESV5_1 0x00000878
616 #define MAC_TX_STATS_RESV5_2 0x0000087c
617 #define MAC_RX_STATS_OCTETS 0x00000880
618 #define MAC_RX_STATS_RESV1 0x00000884
619 #define MAC_RX_STATS_FRAGMENTS 0x00000888
620 #define MAC_RX_STATS_UCAST 0x0000088c
621 #define MAC_RX_STATS_MCAST 0x00000890
622 #define MAC_RX_STATS_BCAST 0x00000894
623 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
624 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
625 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
626 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
627 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
628 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
629 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
630 #define MAC_RX_STATS_JABBERS 0x000008b4
631 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
632 /* 0x8bc --> 0xc00 unused */
634 /* Send data initiator control registers */
635 #define SNDDATAI_MODE 0x00000c00
636 #define SNDDATAI_MODE_RESET 0x00000001
637 #define SNDDATAI_MODE_ENABLE 0x00000002
638 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
639 #define SNDDATAI_STATUS 0x00000c04
640 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
641 #define SNDDATAI_STATSCTRL 0x00000c08
642 #define SNDDATAI_SCTRL_ENABLE 0x00000001
643 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
644 #define SNDDATAI_SCTRL_CLEAR 0x00000004
645 #define SNDDATAI_SCTRL_FLUSH 0x00000008
646 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
647 #define SNDDATAI_STATSENAB 0x00000c0c
648 #define SNDDATAI_STATSINCMASK 0x00000c10
649 /* 0xc14 --> 0xc80 unused */
650 #define SNDDATAI_COS_CNT_0 0x00000c80
651 #define SNDDATAI_COS_CNT_1 0x00000c84
652 #define SNDDATAI_COS_CNT_2 0x00000c88
653 #define SNDDATAI_COS_CNT_3 0x00000c8c
654 #define SNDDATAI_COS_CNT_4 0x00000c90
655 #define SNDDATAI_COS_CNT_5 0x00000c94
656 #define SNDDATAI_COS_CNT_6 0x00000c98
657 #define SNDDATAI_COS_CNT_7 0x00000c9c
658 #define SNDDATAI_COS_CNT_8 0x00000ca0
659 #define SNDDATAI_COS_CNT_9 0x00000ca4
660 #define SNDDATAI_COS_CNT_10 0x00000ca8
661 #define SNDDATAI_COS_CNT_11 0x00000cac
662 #define SNDDATAI_COS_CNT_12 0x00000cb0
663 #define SNDDATAI_COS_CNT_13 0x00000cb4
664 #define SNDDATAI_COS_CNT_14 0x00000cb8
665 #define SNDDATAI_COS_CNT_15 0x00000cbc
666 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
667 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
668 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
669 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
670 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
671 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
672 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
673 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
674 /* 0xce0 --> 0x1000 unused */
676 /* Send data completion control registers */
677 #define SNDDATAC_MODE 0x00001000
678 #define SNDDATAC_MODE_RESET 0x00000001
679 #define SNDDATAC_MODE_ENABLE 0x00000002
680 /* 0x1004 --> 0x1400 unused */
682 /* Send BD ring selector */
683 #define SNDBDS_MODE 0x00001400
684 #define SNDBDS_MODE_RESET 0x00000001
685 #define SNDBDS_MODE_ENABLE 0x00000002
686 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
687 #define SNDBDS_STATUS 0x00001404
688 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
689 #define SNDBDS_HWDIAG 0x00001408
690 /* 0x140c --> 0x1440 */
691 #define SNDBDS_SEL_CON_IDX_0 0x00001440
692 #define SNDBDS_SEL_CON_IDX_1 0x00001444
693 #define SNDBDS_SEL_CON_IDX_2 0x00001448
694 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
695 #define SNDBDS_SEL_CON_IDX_4 0x00001450
696 #define SNDBDS_SEL_CON_IDX_5 0x00001454
697 #define SNDBDS_SEL_CON_IDX_6 0x00001458
698 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
699 #define SNDBDS_SEL_CON_IDX_8 0x00001460
700 #define SNDBDS_SEL_CON_IDX_9 0x00001464
701 #define SNDBDS_SEL_CON_IDX_10 0x00001468
702 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
703 #define SNDBDS_SEL_CON_IDX_12 0x00001470
704 #define SNDBDS_SEL_CON_IDX_13 0x00001474
705 #define SNDBDS_SEL_CON_IDX_14 0x00001478
706 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
707 /* 0x1480 --> 0x1800 unused */
709 /* Send BD initiator control registers */
710 #define SNDBDI_MODE 0x00001800
711 #define SNDBDI_MODE_RESET 0x00000001
712 #define SNDBDI_MODE_ENABLE 0x00000002
713 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
714 #define SNDBDI_STATUS 0x00001804
715 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
716 #define SNDBDI_IN_PROD_IDX_0 0x00001808
717 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
718 #define SNDBDI_IN_PROD_IDX_2 0x00001810
719 #define SNDBDI_IN_PROD_IDX_3 0x00001814
720 #define SNDBDI_IN_PROD_IDX_4 0x00001818
721 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
722 #define SNDBDI_IN_PROD_IDX_6 0x00001820
723 #define SNDBDI_IN_PROD_IDX_7 0x00001824
724 #define SNDBDI_IN_PROD_IDX_8 0x00001828
725 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
726 #define SNDBDI_IN_PROD_IDX_10 0x00001830
727 #define SNDBDI_IN_PROD_IDX_11 0x00001834
728 #define SNDBDI_IN_PROD_IDX_12 0x00001838
729 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
730 #define SNDBDI_IN_PROD_IDX_14 0x00001840
731 #define SNDBDI_IN_PROD_IDX_15 0x00001844
732 /* 0x1848 --> 0x1c00 unused */
734 /* Send BD completion control registers */
735 #define SNDBDC_MODE 0x00001c00
736 #define SNDBDC_MODE_RESET 0x00000001
737 #define SNDBDC_MODE_ENABLE 0x00000002
738 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
739 /* 0x1c04 --> 0x2000 unused */
741 /* Receive list placement control registers */
742 #define RCVLPC_MODE 0x00002000
743 #define RCVLPC_MODE_RESET 0x00000001
744 #define RCVLPC_MODE_ENABLE 0x00000002
745 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
746 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
747 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
748 #define RCVLPC_STATUS 0x00002004
749 #define RCVLPC_STATUS_CLASS0 0x00000004
750 #define RCVLPC_STATUS_MAPOOR 0x00000008
751 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
752 #define RCVLPC_LOCK 0x00002008
753 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
754 #define RCVLPC_LOCK_REQ_SHIFT 0
755 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
756 #define RCVLPC_LOCK_GRANT_SHIFT 16
757 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
758 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
759 #define RCVLPC_CONFIG 0x00002010
760 #define RCVLPC_STATSCTRL 0x00002014
761 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
762 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
763 #define RCVLPC_STATS_ENABLE 0x00002018
764 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
765 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
766 #define RCVLPC_STATS_INCMASK 0x0000201c
767 /* 0x2020 --> 0x2100 unused */
768 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
769 #define SELLST_TAIL 0x00000004
770 #define SELLST_CONT 0x00000008
771 #define SELLST_UNUSED 0x0000000c
772 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
773 #define RCVLPC_DROP_FILTER_CNT 0x00002240
774 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
775 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
776 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
777 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
778 #define RCVLPC_IN_ERRORS_CNT 0x00002254
779 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
780 /* 0x225c --> 0x2400 unused */
782 /* Receive Data and Receive BD Initiator Control */
783 #define RCVDBDI_MODE 0x00002400
784 #define RCVDBDI_MODE_RESET 0x00000001
785 #define RCVDBDI_MODE_ENABLE 0x00000002
786 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
787 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
788 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
789 #define RCVDBDI_STATUS 0x00002404
790 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
791 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
792 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
793 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
794 /* 0x240c --> 0x2440 unused */
795 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
796 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
797 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
798 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
799 #define RCVDBDI_STD_CON_IDX 0x00002474
800 #define RCVDBDI_MINI_CON_IDX 0x00002478
801 /* 0x247c --> 0x2480 unused */
802 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
803 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
804 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
805 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
806 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
807 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
808 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
809 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
810 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
811 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
812 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
813 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
814 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
815 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
816 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
817 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
818 #define RCVDBDI_HWDIAG 0x000024c0
819 /* 0x24c4 --> 0x2800 unused */
821 /* Receive Data Completion Control */
822 #define RCVDCC_MODE 0x00002800
823 #define RCVDCC_MODE_RESET 0x00000001
824 #define RCVDCC_MODE_ENABLE 0x00000002
825 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
826 /* 0x2804 --> 0x2c00 unused */
828 /* Receive BD Initiator Control Registers */
829 #define RCVBDI_MODE 0x00002c00
830 #define RCVBDI_MODE_RESET 0x00000001
831 #define RCVBDI_MODE_ENABLE 0x00000002
832 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
833 #define RCVBDI_STATUS 0x00002c04
834 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
835 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
836 #define RCVBDI_STD_PROD_IDX 0x00002c0c
837 #define RCVBDI_MINI_PROD_IDX 0x00002c10
838 #define RCVBDI_MINI_THRESH 0x00002c14
839 #define RCVBDI_STD_THRESH 0x00002c18
840 #define RCVBDI_JUMBO_THRESH 0x00002c1c
841 /* 0x2c20 --> 0x3000 unused */
843 /* Receive BD Completion Control Registers */
844 #define RCVCC_MODE 0x00003000
845 #define RCVCC_MODE_RESET 0x00000001
846 #define RCVCC_MODE_ENABLE 0x00000002
847 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
848 #define RCVCC_STATUS 0x00003004
849 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
850 #define RCVCC_JUMP_PROD_IDX 0x00003008
851 #define RCVCC_STD_PROD_IDX 0x0000300c
852 #define RCVCC_MINI_PROD_IDX 0x00003010
853 /* 0x3014 --> 0x3400 unused */
855 /* Receive list selector control registers */
856 #define RCVLSC_MODE 0x00003400
857 #define RCVLSC_MODE_RESET 0x00000001
858 #define RCVLSC_MODE_ENABLE 0x00000002
859 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
860 #define RCVLSC_STATUS 0x00003404
861 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
862 /* 0x3408 --> 0x3800 unused */
864 /* Mbuf cluster free registers */
865 #define MBFREE_MODE 0x00003800
866 #define MBFREE_MODE_RESET 0x00000001
867 #define MBFREE_MODE_ENABLE 0x00000002
868 #define MBFREE_STATUS 0x00003804
869 /* 0x3808 --> 0x3c00 unused */
871 /* Host coalescing control registers */
872 #define HOSTCC_MODE 0x00003c00
873 #define HOSTCC_MODE_RESET 0x00000001
874 #define HOSTCC_MODE_ENABLE 0x00000002
875 #define HOSTCC_MODE_ATTN 0x00000004
876 #define HOSTCC_MODE_NOW 0x00000008
877 #define HOSTCC_MODE_FULL_STATUS 0x00000000
878 #define HOSTCC_MODE_64BYTE 0x00000080
879 #define HOSTCC_MODE_32BYTE 0x00000100
880 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
881 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
882 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
883 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
884 #define HOSTCC_STATUS 0x00003c04
885 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
886 #define HOSTCC_RXCOL_TICKS 0x00003c08
887 #define LOW_RXCOL_TICKS 0x00000032
888 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
889 #define DEFAULT_RXCOL_TICKS 0x00000048
890 #define HIGH_RXCOL_TICKS 0x00000096
891 #define MAX_RXCOL_TICKS 0x000003ff
892 #define HOSTCC_TXCOL_TICKS 0x00003c0c
893 #define LOW_TXCOL_TICKS 0x00000096
894 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
895 #define DEFAULT_TXCOL_TICKS 0x0000012c
896 #define HIGH_TXCOL_TICKS 0x00000145
897 #define MAX_TXCOL_TICKS 0x000003ff
898 #define HOSTCC_RXMAX_FRAMES 0x00003c10
899 #define LOW_RXMAX_FRAMES 0x00000005
900 #define DEFAULT_RXMAX_FRAMES 0x00000008
901 #define HIGH_RXMAX_FRAMES 0x00000012
902 #define MAX_RXMAX_FRAMES 0x000000ff
903 #define HOSTCC_TXMAX_FRAMES 0x00003c14
904 #define LOW_TXMAX_FRAMES 0x00000035
905 #define DEFAULT_TXMAX_FRAMES 0x0000004b
906 #define HIGH_TXMAX_FRAMES 0x00000052
907 #define MAX_TXMAX_FRAMES 0x000000ff
908 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
909 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
910 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
911 #define MAX_RXCOAL_TICK_INT 0x000003ff
912 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
913 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
914 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
915 #define MAX_TXCOAL_TICK_INT 0x000003ff
916 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
917 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
918 #define MAX_RXCOAL_MAXF_INT 0x000000ff
919 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
920 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
921 #define MAX_TXCOAL_MAXF_INT 0x000000ff
922 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
923 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
924 #define MAX_STAT_COAL_TICKS 0xd693d400
925 #define MIN_STAT_COAL_TICKS 0x00000064
926 /* 0x3c2c --> 0x3c30 unused */
927 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
928 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
929 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
930 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
931 #define HOSTCC_FLOW_ATTN 0x00003c48
932 /* 0x3c4c --> 0x3c50 unused */
933 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
934 #define HOSTCC_STD_CON_IDX 0x00003c54
935 #define HOSTCC_MINI_CON_IDX 0x00003c58
936 /* 0x3c5c --> 0x3c80 unused */
937 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
938 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
939 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
940 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
941 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
942 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
943 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
944 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
945 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
946 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
947 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
948 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
949 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
950 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
951 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
952 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
953 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
954 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
955 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
956 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
957 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
958 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
959 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
960 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
961 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
962 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
963 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
964 #define HOSTCC_SND_CON_IDX_11 0x00003cec
965 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
966 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
967 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
968 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
969 /* 0x3d00 --> 0x4000 unused */
971 /* Memory arbiter control registers */
972 #define MEMARB_MODE 0x00004000
973 #define MEMARB_MODE_RESET 0x00000001
974 #define MEMARB_MODE_ENABLE 0x00000002
975 #define MEMARB_STATUS 0x00004004
976 #define MEMARB_TRAP_ADDR_LOW 0x00004008
977 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
978 /* 0x4010 --> 0x4400 unused */
980 /* Buffer manager control registers */
981 #define BUFMGR_MODE 0x00004400
982 #define BUFMGR_MODE_RESET 0x00000001
983 #define BUFMGR_MODE_ENABLE 0x00000002
984 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
985 #define BUFMGR_MODE_BM_TEST 0x00000008
986 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
987 #define BUFMGR_STATUS 0x00004404
988 #define BUFMGR_STATUS_ERROR 0x00000004
989 #define BUFMGR_STATUS_MBLOW 0x00000010
990 #define BUFMGR_MB_POOL_ADDR 0x00004408
991 #define BUFMGR_MB_POOL_SIZE 0x0000440c
992 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
993 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
994 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
995 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
996 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
997 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
998 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
999 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1000 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1001 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1002 #define BUFMGR_MB_HIGH_WATER 0x00004418
1003 #define DEFAULT_MB_HIGH_WATER 0x00000060
1004 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1005 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1006 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1007 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1008 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1009 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1010 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1011 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1012 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1013 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1014 #define BUFMGR_DMA_LOW_WATER 0x00004434
1015 #define DEFAULT_DMA_LOW_WATER 0x00000005
1016 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1017 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1018 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1019 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1020 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1021 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1022 #define BUFMGR_HWDIAG_0 0x0000444c
1023 #define BUFMGR_HWDIAG_1 0x00004450
1024 #define BUFMGR_HWDIAG_2 0x00004454
1025 /* 0x4458 --> 0x4800 unused */
1027 /* Read DMA control registers */
1028 #define RDMAC_MODE 0x00004800
1029 #define RDMAC_MODE_RESET 0x00000001
1030 #define RDMAC_MODE_ENABLE 0x00000002
1031 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1032 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1033 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1034 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1035 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1036 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1037 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1038 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1039 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1040 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1041 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1042 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1043 #define RDMAC_STATUS 0x00004804
1044 #define RDMAC_STATUS_TGTABORT 0x00000004
1045 #define RDMAC_STATUS_MSTABORT 0x00000008
1046 #define RDMAC_STATUS_PARITYERR 0x00000010
1047 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1048 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1049 #define RDMAC_STATUS_FIFOURUN 0x00000080
1050 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1051 #define RDMAC_STATUS_LNGREAD 0x00000200
1052 /* 0x4808 --> 0x4c00 unused */
1054 /* Write DMA control registers */
1055 #define WDMAC_MODE 0x00004c00
1056 #define WDMAC_MODE_RESET 0x00000001
1057 #define WDMAC_MODE_ENABLE 0x00000002
1058 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1059 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1060 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1061 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1062 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1063 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1064 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1065 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1066 #define WDMAC_MODE_RX_ACCEL 0x00000400
1067 #define WDMAC_STATUS 0x00004c04
1068 #define WDMAC_STATUS_TGTABORT 0x00000004
1069 #define WDMAC_STATUS_MSTABORT 0x00000008
1070 #define WDMAC_STATUS_PARITYERR 0x00000010
1071 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1072 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1073 #define WDMAC_STATUS_FIFOURUN 0x00000080
1074 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1075 #define WDMAC_STATUS_LNGREAD 0x00000200
1076 /* 0x4c08 --> 0x5000 unused */
1078 /* Per-cpu register offsets (arm9) */
1079 #define CPU_MODE 0x00000000
1080 #define CPU_MODE_RESET 0x00000001
1081 #define CPU_MODE_HALT 0x00000400
1082 #define CPU_STATE 0x00000004
1083 #define CPU_EVTMASK 0x00000008
1084 /* 0xc --> 0x1c reserved */
1085 #define CPU_PC 0x0000001c
1086 #define CPU_INSN 0x00000020
1087 #define CPU_SPAD_UFLOW 0x00000024
1088 #define CPU_WDOG_CLEAR 0x00000028
1089 #define CPU_WDOG_VECTOR 0x0000002c
1090 #define CPU_WDOG_PC 0x00000030
1091 #define CPU_HW_BP 0x00000034
1092 /* 0x38 --> 0x44 unused */
1093 #define CPU_WDOG_SAVED_STATE 0x00000044
1094 #define CPU_LAST_BRANCH_ADDR 0x00000048
1095 #define CPU_SPAD_UFLOW_SET 0x0000004c
1096 /* 0x50 --> 0x200 unused */
1097 #define CPU_R0 0x00000200
1098 #define CPU_R1 0x00000204
1099 #define CPU_R2 0x00000208
1100 #define CPU_R3 0x0000020c
1101 #define CPU_R4 0x00000210
1102 #define CPU_R5 0x00000214
1103 #define CPU_R6 0x00000218
1104 #define CPU_R7 0x0000021c
1105 #define CPU_R8 0x00000220
1106 #define CPU_R9 0x00000224
1107 #define CPU_R10 0x00000228
1108 #define CPU_R11 0x0000022c
1109 #define CPU_R12 0x00000230
1110 #define CPU_R13 0x00000234
1111 #define CPU_R14 0x00000238
1112 #define CPU_R15 0x0000023c
1113 #define CPU_R16 0x00000240
1114 #define CPU_R17 0x00000244
1115 #define CPU_R18 0x00000248
1116 #define CPU_R19 0x0000024c
1117 #define CPU_R20 0x00000250
1118 #define CPU_R21 0x00000254
1119 #define CPU_R22 0x00000258
1120 #define CPU_R23 0x0000025c
1121 #define CPU_R24 0x00000260
1122 #define CPU_R25 0x00000264
1123 #define CPU_R26 0x00000268
1124 #define CPU_R27 0x0000026c
1125 #define CPU_R28 0x00000270
1126 #define CPU_R29 0x00000274
1127 #define CPU_R30 0x00000278
1128 #define CPU_R31 0x0000027c
1129 /* 0x280 --> 0x400 unused */
1131 #define RX_CPU_BASE 0x00005000
1132 #define RX_CPU_MODE 0x00005000
1133 #define RX_CPU_STATE 0x00005004
1134 #define RX_CPU_PGMCTR 0x0000501c
1135 #define RX_CPU_HWBKPT 0x00005034
1136 #define TX_CPU_BASE 0x00005400
1137 #define TX_CPU_MODE 0x00005400
1138 #define TX_CPU_STATE 0x00005404
1139 #define TX_CPU_PGMCTR 0x0000541c
1141 /* Mailboxes */
1142 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1143 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1144 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1145 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1146 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1147 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1148 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1149 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1150 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1151 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1152 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1153 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1154 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1155 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1156 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1157 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1158 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1159 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1160 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1161 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1162 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1163 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1164 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1165 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1166 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1167 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1168 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1169 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1170 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1171 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1172 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1173 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1174 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1175 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1176 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1177 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1178 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1179 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1180 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1181 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1182 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1183 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1184 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1185 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1186 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1187 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1188 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1189 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1190 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1191 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1192 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1193 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1194 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1195 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1196 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1197 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1198 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1199 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1200 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1201 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1202 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1203 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1204 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1205 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1206 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1207 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1208 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1209 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1210 /* 0x5a10 --> 0x5c00 */
1212 /* Flow Through queues */
1213 #define FTQ_RESET 0x00005c00
1214 /* 0x5c04 --> 0x5c10 unused */
1215 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1216 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1217 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1218 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1219 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1220 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1221 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1222 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1223 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1224 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1225 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1226 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1227 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1228 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1229 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1230 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1231 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1232 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1233 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1234 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1235 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1236 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1237 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1238 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1239 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1240 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1241 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1242 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1243 #define FTQ_SWTYPE1_CTL 0x00005c80
1244 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1245 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1246 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1247 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1248 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1249 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1250 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1251 #define FTQ_HOST_COAL_CTL 0x00005ca0
1252 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1253 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1254 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1255 #define FTQ_MAC_TX_CTL 0x00005cb0
1256 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1257 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1258 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1259 #define FTQ_MB_FREE_CTL 0x00005cc0
1260 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1261 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1262 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1263 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1264 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1265 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1266 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1267 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1268 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1269 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1270 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1271 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1272 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1273 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1274 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1275 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1276 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1277 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1278 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1279 #define FTQ_SWTYPE2_CTL 0x00005d10
1280 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1281 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1282 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1283 /* 0x5d20 --> 0x6000 unused */
1285 /* Message signaled interrupt registers */
1286 #define MSGINT_MODE 0x00006000
1287 #define MSGINT_MODE_RESET 0x00000001
1288 #define MSGINT_MODE_ENABLE 0x00000002
1289 #define MSGINT_STATUS 0x00006004
1290 #define MSGINT_FIFO 0x00006008
1291 /* 0x600c --> 0x6400 unused */
1293 /* DMA completion registers */
1294 #define DMAC_MODE 0x00006400
1295 #define DMAC_MODE_RESET 0x00000001
1296 #define DMAC_MODE_ENABLE 0x00000002
1297 /* 0x6404 --> 0x6800 unused */
1299 /* GRC registers */
1300 #define GRC_MODE 0x00006800
1301 #define GRC_MODE_UPD_ON_COAL 0x00000001
1302 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1303 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1304 #define GRC_MODE_BSWAP_DATA 0x00000010
1305 #define GRC_MODE_WSWAP_DATA 0x00000020
1306 #define GRC_MODE_SPLITHDR 0x00000100
1307 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1308 #define GRC_MODE_INCL_CRC 0x00000400
1309 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1310 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1311 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1312 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1313 #define GRC_MODE_HOST_STACKUP 0x00010000
1314 #define GRC_MODE_HOST_SENDBDS 0x00020000
1315 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1316 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1317 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1318 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1319 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1320 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1321 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1322 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1323 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1324 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1325 #define GRC_MISC_CFG 0x00006804
1326 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1327 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1328 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1329 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1330 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1331 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1332 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1333 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1334 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1335 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1336 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1337 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1338 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1339 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1340 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1341 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1342 #define GRC_LOCAL_CTRL 0x00006808
1343 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1344 #define GRC_LCLCTRL_CLEARINT 0x00000002
1345 #define GRC_LCLCTRL_SETINT 0x00000004
1346 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1347 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1348 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1349 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1350 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1351 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1352 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1353 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1354 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1355 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1356 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1357 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1358 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1359 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1360 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1361 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1362 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1363 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1364 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1365 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1366 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1367 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1368 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1369 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1370 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1371 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1372 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1373 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1374 #define GRC_TIMER 0x0000680c
1375 #define GRC_RX_CPU_EVENT 0x00006810
1376 #define GRC_RX_TIMER_REF 0x00006814
1377 #define GRC_RX_CPU_SEM 0x00006818
1378 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1379 #define GRC_TX_CPU_EVENT 0x00006820
1380 #define GRC_TX_TIMER_REF 0x00006824
1381 #define GRC_TX_CPU_SEM 0x00006828
1382 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1383 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1384 #define GRC_EEPROM_ADDR 0x00006838
1385 #define EEPROM_ADDR_WRITE 0x00000000
1386 #define EEPROM_ADDR_READ 0x80000000
1387 #define EEPROM_ADDR_COMPLETE 0x40000000
1388 #define EEPROM_ADDR_FSM_RESET 0x20000000
1389 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1390 #define EEPROM_ADDR_DEVID_SHIFT 26
1391 #define EEPROM_ADDR_START 0x02000000
1392 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1393 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1394 #define EEPROM_ADDR_ADDR_SHIFT 0
1395 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1396 #define EEPROM_CHIP_SIZE (64 * 1024)
1397 #define GRC_EEPROM_DATA 0x0000683c
1398 #define GRC_EEPROM_CTRL 0x00006840
1399 #define GRC_MDI_CTRL 0x00006844
1400 #define GRC_SEEPROM_DELAY 0x00006848
1401 /* 0x684c --> 0x6c00 unused */
1402 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1404 /* 0x6c00 --> 0x7000 unused */
1406 /* NVRAM Control registers */
1407 #define NVRAM_CMD 0x00007000
1408 #define NVRAM_CMD_RESET 0x00000001
1409 #define NVRAM_CMD_DONE 0x00000008
1410 #define NVRAM_CMD_GO 0x00000010
1411 #define NVRAM_CMD_WR 0x00000020
1412 #define NVRAM_CMD_RD 0x00000000
1413 #define NVRAM_CMD_ERASE 0x00000040
1414 #define NVRAM_CMD_FIRST 0x00000080
1415 #define NVRAM_CMD_LAST 0x00000100
1416 #define NVRAM_CMD_WREN 0x00010000
1417 #define NVRAM_CMD_WRDI 0x00020000
1418 #define NVRAM_STAT 0x00007004
1419 #define NVRAM_WRDATA 0x00007008
1420 #define NVRAM_ADDR 0x0000700c
1421 #define NVRAM_ADDR_MSK 0x00ffffff
1422 #define NVRAM_RDDATA 0x00007010
1423 #define NVRAM_CFG1 0x00007014
1424 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1425 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1426 #define NVRAM_CFG1_PASS_THRU 0x00000004
1427 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1428 #define NVRAM_CFG1_BIT_BANG 0x00000008
1429 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1430 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1431 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1432 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1433 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1434 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1435 #define FLASH_VENDOR_ST 0x03000001
1436 #define FLASH_VENDOR_SAIFUN 0x01000003
1437 #define FLASH_VENDOR_SST_SMALL 0x00000001
1438 #define FLASH_VENDOR_SST_LARGE 0x02000001
1439 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1440 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1441 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1442 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1443 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1444 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1445 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1446 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1447 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1448 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1449 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1450 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1451 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1452 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1453 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1454 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1455 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1456 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1457 #define FLASH_5752PAGE_SIZE_256 0x00000000
1458 #define FLASH_5752PAGE_SIZE_512 0x10000000
1459 #define FLASH_5752PAGE_SIZE_1K 0x20000000
1460 #define FLASH_5752PAGE_SIZE_2K 0x30000000
1461 #define FLASH_5752PAGE_SIZE_4K 0x40000000
1462 #define FLASH_5752PAGE_SIZE_264 0x50000000
1463 #define NVRAM_CFG2 0x00007018
1464 #define NVRAM_CFG3 0x0000701c
1465 #define NVRAM_SWARB 0x00007020
1466 #define SWARB_REQ_SET0 0x00000001
1467 #define SWARB_REQ_SET1 0x00000002
1468 #define SWARB_REQ_SET2 0x00000004
1469 #define SWARB_REQ_SET3 0x00000008
1470 #define SWARB_REQ_CLR0 0x00000010
1471 #define SWARB_REQ_CLR1 0x00000020
1472 #define SWARB_REQ_CLR2 0x00000040
1473 #define SWARB_REQ_CLR3 0x00000080
1474 #define SWARB_GNT0 0x00000100
1475 #define SWARB_GNT1 0x00000200
1476 #define SWARB_GNT2 0x00000400
1477 #define SWARB_GNT3 0x00000800
1478 #define SWARB_REQ0 0x00001000
1479 #define SWARB_REQ1 0x00002000
1480 #define SWARB_REQ2 0x00004000
1481 #define SWARB_REQ3 0x00008000
1482 #define NVRAM_ACCESS 0x00007024
1483 #define ACCESS_ENABLE 0x00000001
1484 #define ACCESS_WR_ENABLE 0x00000002
1485 #define NVRAM_WRITE1 0x00007028
1486 /* 0x702c --> 0x7400 unused */
1488 /* 0x7400 --> 0x8000 unused */
1490 #define TG3_EEPROM_MAGIC 0x669955aa
1492 /* 32K Window into NIC internal memory */
1493 #define NIC_SRAM_WIN_BASE 0x00008000
1495 /* Offsets into first 32k of NIC internal memory. */
1496 #define NIC_SRAM_PAGE_ZERO 0x00000000
1497 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1498 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1499 #define NIC_SRAM_STATS_BLK 0x00000300
1500 #define NIC_SRAM_STATUS_BLK 0x00000b00
1502 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1503 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1504 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1506 #define NIC_SRAM_DATA_SIG 0x00000b54
1507 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1509 #define NIC_SRAM_DATA_CFG 0x00000b58
1510 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1511 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1512 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1513 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1514 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1515 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1516 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1517 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1518 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1519 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1520 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1521 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1522 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1523 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
1525 #define NIC_SRAM_DATA_VER 0x00000b5c
1526 #define NIC_SRAM_DATA_VER_SHIFT 16
1528 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1529 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1530 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1532 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1533 #define FWCMD_NICDRV_ALIVE 0x00000001
1534 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1535 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1536 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1537 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1538 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1539 #define FWCMD_NICDRV_ALIVE2 0x0000000d
1540 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1541 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1542 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1543 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1544 #define DRV_STATE_START 0x00000001
1545 #define DRV_STATE_START_DONE 0x80000001
1546 #define DRV_STATE_UNLOAD 0x00000002
1547 #define DRV_STATE_UNLOAD_DONE 0x80000002
1548 #define DRV_STATE_WOL 0x00000003
1549 #define DRV_STATE_SUSPEND 0x00000004
1551 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1553 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1554 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1556 #define NIC_SRAM_WOL_MBOX 0x00000d30
1557 #define WOL_SIGNATURE 0x474c0000
1558 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
1559 #define WOL_DRV_WOL 0x00000002
1560 #define WOL_SET_MAGIC_PKT 0x00000004
1562 #define NIC_SRAM_DATA_CFG_2 0x00000d38
1564 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
1565 #define SHASTA_EXT_LED_LEGACY 0x00000000
1566 #define SHASTA_EXT_LED_SHARED 0x00008000
1567 #define SHASTA_EXT_LED_MAC 0x00010000
1568 #define SHASTA_EXT_LED_COMBO 0x00018000
1570 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1572 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1573 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1574 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1575 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1576 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1577 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1578 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1579 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1580 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1581 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1583 /* Currently this is fixed. */
1584 #define PHY_ADDR 0x01
1586 /* Tigon3 specific PHY MII registers. */
1587 #define TG3_BMCR_SPEED1000 0x0040
1589 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1590 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1591 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1592 #define MII_TG3_CTRL_AS_MASTER 0x0800
1593 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1595 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1596 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1597 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1598 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1599 #define MII_TG3_EXT_CTRL_TBI 0x8000
1601 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1602 #define MII_TG3_EXT_STAT_LPASS 0x0100
1604 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1606 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1608 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1610 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1611 #define MII_TG3_AUX_STAT_LPASS 0x0004
1612 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1613 #define MII_TG3_AUX_STAT_10HALF 0x0100
1614 #define MII_TG3_AUX_STAT_10FULL 0x0200
1615 #define MII_TG3_AUX_STAT_100HALF 0x0300
1616 #define MII_TG3_AUX_STAT_100_4 0x0400
1617 #define MII_TG3_AUX_STAT_100FULL 0x0500
1618 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1619 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1621 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1622 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1624 /* ISTAT/IMASK event bits */
1625 #define MII_TG3_INT_LINKCHG 0x0002
1626 #define MII_TG3_INT_SPEEDCHG 0x0004
1627 #define MII_TG3_INT_DUPLEXCHG 0x0008
1628 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1630 /* There are two ways to manage the TX descriptors on the tigon3.
1631 * Either the descriptors are in host DMA'able memory, or they
1632 * exist only in the cards on-chip SRAM. All 16 send bds are under
1633 * the same mode, they may not be configured individually.
1635 * This driver always uses host memory TX descriptors.
1637 * To use host memory TX descriptors:
1638 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1639 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1640 * 2) Allocate DMA'able memory.
1641 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1642 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1643 * obtained in step 2
1644 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1645 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1646 * of TX descriptors. Leave flags field clear.
1647 * 4) Access TX descriptors via host memory. The chip
1648 * will refetch into local SRAM as needed when producer
1649 * index mailboxes are updated.
1651 * To use on-chip TX descriptors:
1652 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1653 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1654 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1655 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1656 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1657 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1658 * 3) Access TX descriptors directly in on-chip SRAM
1659 * using normal {read,write}l(). (and not using
1660 * pointer dereferencing of ioremap()'d memory like
1661 * the broken Broadcom driver does)
1663 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1664 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1665 */
1666 struct tg3_tx_buffer_desc {
1667 u32 addr_hi;
1668 u32 addr_lo;
1670 u32 len_flags;
1671 #define TXD_FLAG_TCPUDP_CSUM 0x0001
1672 #define TXD_FLAG_IP_CSUM 0x0002
1673 #define TXD_FLAG_END 0x0004
1674 #define TXD_FLAG_IP_FRAG 0x0008
1675 #define TXD_FLAG_IP_FRAG_END 0x0010
1676 #define TXD_FLAG_VLAN 0x0040
1677 #define TXD_FLAG_COAL_NOW 0x0080
1678 #define TXD_FLAG_CPU_PRE_DMA 0x0100
1679 #define TXD_FLAG_CPU_POST_DMA 0x0200
1680 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1681 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1682 #define TXD_FLAG_NO_CRC 0x8000
1683 #define TXD_LEN_SHIFT 16
1685 u32 vlan_tag;
1686 #define TXD_VLAN_TAG_SHIFT 0
1687 #define TXD_MSS_SHIFT 16
1688 };
1690 #define TXD_ADDR 0x00UL /* 64-bit */
1691 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1692 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1693 #define TXD_SIZE 0x10UL
1695 struct tg3_rx_buffer_desc {
1696 u32 addr_hi;
1697 u32 addr_lo;
1699 u32 idx_len;
1700 #define RXD_IDX_MASK 0xffff0000
1701 #define RXD_IDX_SHIFT 16
1702 #define RXD_LEN_MASK 0x0000ffff
1703 #define RXD_LEN_SHIFT 0
1705 u32 type_flags;
1706 #define RXD_TYPE_SHIFT 16
1707 #define RXD_FLAGS_SHIFT 0
1709 #define RXD_FLAG_END 0x0004
1710 #define RXD_FLAG_MINI 0x0800
1711 #define RXD_FLAG_JUMBO 0x0020
1712 #define RXD_FLAG_VLAN 0x0040
1713 #define RXD_FLAG_ERROR 0x0400
1714 #define RXD_FLAG_IP_CSUM 0x1000
1715 #define RXD_FLAG_TCPUDP_CSUM 0x2000
1716 #define RXD_FLAG_IS_TCP 0x4000
1718 u32 ip_tcp_csum;
1719 #define RXD_IPCSUM_MASK 0xffff0000
1720 #define RXD_IPCSUM_SHIFT 16
1721 #define RXD_TCPCSUM_MASK 0x0000ffff
1722 #define RXD_TCPCSUM_SHIFT 0
1724 u32 err_vlan;
1726 #define RXD_VLAN_MASK 0x0000ffff
1728 #define RXD_ERR_BAD_CRC 0x00010000
1729 #define RXD_ERR_COLLISION 0x00020000
1730 #define RXD_ERR_LINK_LOST 0x00040000
1731 #define RXD_ERR_PHY_DECODE 0x00080000
1732 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1733 #define RXD_ERR_MAC_ABRT 0x00200000
1734 #define RXD_ERR_TOO_SMALL 0x00400000
1735 #define RXD_ERR_NO_RESOURCES 0x00800000
1736 #define RXD_ERR_HUGE_FRAME 0x01000000
1737 #define RXD_ERR_MASK 0xffff0000
1739 u32 reserved;
1740 u32 opaque;
1741 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1742 #define RXD_OPAQUE_INDEX_SHIFT 0
1743 #define RXD_OPAQUE_RING_STD 0x00010000
1744 #define RXD_OPAQUE_RING_JUMBO 0x00020000
1745 #define RXD_OPAQUE_RING_MINI 0x00040000
1746 #define RXD_OPAQUE_RING_MASK 0x00070000
1747 };
1749 struct tg3_ext_rx_buffer_desc {
1750 struct {
1751 u32 addr_hi;
1752 u32 addr_lo;
1753 } addrlist[3];
1754 u32 len2_len1;
1755 u32 resv_len3;
1756 struct tg3_rx_buffer_desc std;
1757 };
1759 /* We only use this when testing out the DMA engine
1760 * at probe time. This is the internal format of buffer
1761 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1762 */
1763 struct tg3_internal_buffer_desc {
1764 u32 addr_hi;
1765 u32 addr_lo;
1766 u32 nic_mbuf;
1767 /* XXX FIX THIS */
1768 #ifdef __BIG_ENDIAN
1769 u16 cqid_sqid;
1770 u16 len;
1771 #else
1772 u16 len;
1773 u16 cqid_sqid;
1774 #endif
1775 u32 flags;
1776 u32 __cookie1;
1777 u32 __cookie2;
1778 u32 __cookie3;
1779 };
1781 #define TG3_HW_STATUS_SIZE 0x50
1782 struct tg3_hw_status {
1783 u32 status;
1784 #define SD_STATUS_UPDATED 0x00000001
1785 #define SD_STATUS_LINK_CHG 0x00000002
1786 #define SD_STATUS_ERROR 0x00000004
1788 u32 status_tag;
1790 #ifdef __BIG_ENDIAN
1791 u16 rx_consumer;
1792 u16 rx_jumbo_consumer;
1793 #else
1794 u16 rx_jumbo_consumer;
1795 u16 rx_consumer;
1796 #endif
1798 #ifdef __BIG_ENDIAN
1799 u16 reserved;
1800 u16 rx_mini_consumer;
1801 #else
1802 u16 rx_mini_consumer;
1803 u16 reserved;
1804 #endif
1805 struct {
1806 #ifdef __BIG_ENDIAN
1807 u16 tx_consumer;
1808 u16 rx_producer;
1809 #else
1810 u16 rx_producer;
1811 u16 tx_consumer;
1812 #endif
1813 } idx[16];
1814 };
1816 typedef struct {
1817 u32 high, low;
1818 } tg3_stat64_t;
1820 struct tg3_hw_stats {
1821 u8 __reserved0[0x400-0x300];
1823 /* Statistics maintained by Receive MAC. */
1824 tg3_stat64_t rx_octets;
1825 u64 __reserved1;
1826 tg3_stat64_t rx_fragments;
1827 tg3_stat64_t rx_ucast_packets;
1828 tg3_stat64_t rx_mcast_packets;
1829 tg3_stat64_t rx_bcast_packets;
1830 tg3_stat64_t rx_fcs_errors;
1831 tg3_stat64_t rx_align_errors;
1832 tg3_stat64_t rx_xon_pause_rcvd;
1833 tg3_stat64_t rx_xoff_pause_rcvd;
1834 tg3_stat64_t rx_mac_ctrl_rcvd;
1835 tg3_stat64_t rx_xoff_entered;
1836 tg3_stat64_t rx_frame_too_long_errors;
1837 tg3_stat64_t rx_jabbers;
1838 tg3_stat64_t rx_undersize_packets;
1839 tg3_stat64_t rx_in_length_errors;
1840 tg3_stat64_t rx_out_length_errors;
1841 tg3_stat64_t rx_64_or_less_octet_packets;
1842 tg3_stat64_t rx_65_to_127_octet_packets;
1843 tg3_stat64_t rx_128_to_255_octet_packets;
1844 tg3_stat64_t rx_256_to_511_octet_packets;
1845 tg3_stat64_t rx_512_to_1023_octet_packets;
1846 tg3_stat64_t rx_1024_to_1522_octet_packets;
1847 tg3_stat64_t rx_1523_to_2047_octet_packets;
1848 tg3_stat64_t rx_2048_to_4095_octet_packets;
1849 tg3_stat64_t rx_4096_to_8191_octet_packets;
1850 tg3_stat64_t rx_8192_to_9022_octet_packets;
1852 u64 __unused0[37];
1854 /* Statistics maintained by Transmit MAC. */
1855 tg3_stat64_t tx_octets;
1856 u64 __reserved2;
1857 tg3_stat64_t tx_collisions;
1858 tg3_stat64_t tx_xon_sent;
1859 tg3_stat64_t tx_xoff_sent;
1860 tg3_stat64_t tx_flow_control;
1861 tg3_stat64_t tx_mac_errors;
1862 tg3_stat64_t tx_single_collisions;
1863 tg3_stat64_t tx_mult_collisions;
1864 tg3_stat64_t tx_deferred;
1865 u64 __reserved3;
1866 tg3_stat64_t tx_excessive_collisions;
1867 tg3_stat64_t tx_late_collisions;
1868 tg3_stat64_t tx_collide_2times;
1869 tg3_stat64_t tx_collide_3times;
1870 tg3_stat64_t tx_collide_4times;
1871 tg3_stat64_t tx_collide_5times;
1872 tg3_stat64_t tx_collide_6times;
1873 tg3_stat64_t tx_collide_7times;
1874 tg3_stat64_t tx_collide_8times;
1875 tg3_stat64_t tx_collide_9times;
1876 tg3_stat64_t tx_collide_10times;
1877 tg3_stat64_t tx_collide_11times;
1878 tg3_stat64_t tx_collide_12times;
1879 tg3_stat64_t tx_collide_13times;
1880 tg3_stat64_t tx_collide_14times;
1881 tg3_stat64_t tx_collide_15times;
1882 tg3_stat64_t tx_ucast_packets;
1883 tg3_stat64_t tx_mcast_packets;
1884 tg3_stat64_t tx_bcast_packets;
1885 tg3_stat64_t tx_carrier_sense_errors;
1886 tg3_stat64_t tx_discards;
1887 tg3_stat64_t tx_errors;
1889 u64 __unused1[31];
1891 /* Statistics maintained by Receive List Placement. */
1892 tg3_stat64_t COS_rx_packets[16];
1893 tg3_stat64_t COS_rx_filter_dropped;
1894 tg3_stat64_t dma_writeq_full;
1895 tg3_stat64_t dma_write_prioq_full;
1896 tg3_stat64_t rxbds_empty;
1897 tg3_stat64_t rx_discards;
1898 tg3_stat64_t rx_errors;
1899 tg3_stat64_t rx_threshold_hit;
1901 u64 __unused2[9];
1903 /* Statistics maintained by Send Data Initiator. */
1904 tg3_stat64_t COS_out_packets[16];
1905 tg3_stat64_t dma_readq_full;
1906 tg3_stat64_t dma_read_prioq_full;
1907 tg3_stat64_t tx_comp_queue_full;
1909 /* Statistics maintained by Host Coalescing. */
1910 tg3_stat64_t ring_set_send_prod_index;
1911 tg3_stat64_t ring_status_update;
1912 tg3_stat64_t nic_irqs;
1913 tg3_stat64_t nic_avoided_irqs;
1914 tg3_stat64_t nic_tx_threshold_hit;
1916 u8 __reserved4[0xb00-0x9c0];
1917 };
1919 /* 'mapping' is superfluous as the chip does not write into
1920 * the tx/rx post rings so we could just fetch it from there.
1921 * But the cache behavior is better how we are doing it now.
1922 */
1923 struct ring_info {
1924 struct sk_buff *skb;
1925 DECLARE_PCI_UNMAP_ADDR(mapping)
1926 };
1928 struct tx_ring_info {
1929 struct sk_buff *skb;
1930 DECLARE_PCI_UNMAP_ADDR(mapping)
1931 u32 prev_vlan_tag;
1932 };
1934 struct tg3_config_info {
1935 u32 flags;
1936 };
1938 struct tg3_link_config {
1939 /* Describes what we're trying to get. */
1940 u32 advertising;
1941 u16 speed;
1942 u8 duplex;
1943 u8 autoneg;
1945 /* Describes what we actually have. */
1946 u16 active_speed;
1947 u8 active_duplex;
1948 #define SPEED_INVALID 0xffff
1949 #define DUPLEX_INVALID 0xff
1950 #define AUTONEG_INVALID 0xff
1952 /* When we go in and out of low power mode we need
1953 * to swap with this state.
1954 */
1955 int phy_is_low_power;
1956 u16 orig_speed;
1957 u8 orig_duplex;
1958 u8 orig_autoneg;
1959 };
1961 struct tg3_bufmgr_config {
1962 u32 mbuf_read_dma_low_water;
1963 u32 mbuf_mac_rx_low_water;
1964 u32 mbuf_high_water;
1966 u32 mbuf_read_dma_low_water_jumbo;
1967 u32 mbuf_mac_rx_low_water_jumbo;
1968 u32 mbuf_high_water_jumbo;
1970 u32 dma_low_water;
1971 u32 dma_high_water;
1972 };
1974 struct tg3_ethtool_stats {
1975 /* Statistics maintained by Receive MAC. */
1976 u64 rx_octets;
1977 u64 rx_fragments;
1978 u64 rx_ucast_packets;
1979 u64 rx_mcast_packets;
1980 u64 rx_bcast_packets;
1981 u64 rx_fcs_errors;
1982 u64 rx_align_errors;
1983 u64 rx_xon_pause_rcvd;
1984 u64 rx_xoff_pause_rcvd;
1985 u64 rx_mac_ctrl_rcvd;
1986 u64 rx_xoff_entered;
1987 u64 rx_frame_too_long_errors;
1988 u64 rx_jabbers;
1989 u64 rx_undersize_packets;
1990 u64 rx_in_length_errors;
1991 u64 rx_out_length_errors;
1992 u64 rx_64_or_less_octet_packets;
1993 u64 rx_65_to_127_octet_packets;
1994 u64 rx_128_to_255_octet_packets;
1995 u64 rx_256_to_511_octet_packets;
1996 u64 rx_512_to_1023_octet_packets;
1997 u64 rx_1024_to_1522_octet_packets;
1998 u64 rx_1523_to_2047_octet_packets;
1999 u64 rx_2048_to_4095_octet_packets;
2000 u64 rx_4096_to_8191_octet_packets;
2001 u64 rx_8192_to_9022_octet_packets;
2003 /* Statistics maintained by Transmit MAC. */
2004 u64 tx_octets;
2005 u64 tx_collisions;
2006 u64 tx_xon_sent;
2007 u64 tx_xoff_sent;
2008 u64 tx_flow_control;
2009 u64 tx_mac_errors;
2010 u64 tx_single_collisions;
2011 u64 tx_mult_collisions;
2012 u64 tx_deferred;
2013 u64 tx_excessive_collisions;
2014 u64 tx_late_collisions;
2015 u64 tx_collide_2times;
2016 u64 tx_collide_3times;
2017 u64 tx_collide_4times;
2018 u64 tx_collide_5times;
2019 u64 tx_collide_6times;
2020 u64 tx_collide_7times;
2021 u64 tx_collide_8times;
2022 u64 tx_collide_9times;
2023 u64 tx_collide_10times;
2024 u64 tx_collide_11times;
2025 u64 tx_collide_12times;
2026 u64 tx_collide_13times;
2027 u64 tx_collide_14times;
2028 u64 tx_collide_15times;
2029 u64 tx_ucast_packets;
2030 u64 tx_mcast_packets;
2031 u64 tx_bcast_packets;
2032 u64 tx_carrier_sense_errors;
2033 u64 tx_discards;
2034 u64 tx_errors;
2036 /* Statistics maintained by Receive List Placement. */
2037 u64 dma_writeq_full;
2038 u64 dma_write_prioq_full;
2039 u64 rxbds_empty;
2040 u64 rx_discards;
2041 u64 rx_errors;
2042 u64 rx_threshold_hit;
2044 /* Statistics maintained by Send Data Initiator. */
2045 u64 dma_readq_full;
2046 u64 dma_read_prioq_full;
2047 u64 tx_comp_queue_full;
2049 /* Statistics maintained by Host Coalescing. */
2050 u64 ring_set_send_prod_index;
2051 u64 ring_status_update;
2052 u64 nic_irqs;
2053 u64 nic_avoided_irqs;
2054 u64 nic_tx_threshold_hit;
2055 };
2057 struct tg3 {
2058 /* begin "general, frequently-used members" cacheline section */
2060 /* If the IRQ handler (which runs lockless) needs to be
2061 * quiesced, the following bitmask state is used. The
2062 * SYNC flag is set by non-IRQ context code to initiate
2063 * the quiescence.
2065 * When the IRQ handler notices that SYNC is set, it
2066 * disables interrupts and returns.
2068 * When all outstanding IRQ handlers have returned after
2069 * the SYNC flag has been set, the setter can be assured
2070 * that interrupts will no longer get run.
2072 * In this way all SMP driver locks are never acquired
2073 * in hw IRQ context, only sw IRQ context or lower.
2074 */
2075 unsigned int irq_sync;
2077 /* SMP locking strategy:
2079 * lock: Held during reset, PHY access, timer, and when
2080 * updating tg3_flags and tg3_flags2.
2082 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2083 * netif_tx_lock when it needs to call
2084 * netif_wake_queue.
2086 * Both of these locks are to be held with BH safety.
2088 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2089 * are running lockless, it is necessary to completely
2090 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2091 * before reconfiguring the device.
2093 * indirect_lock: Held when accessing registers indirectly
2094 * with IRQ disabling.
2095 */
2096 spinlock_t lock;
2097 spinlock_t indirect_lock;
2099 u32 (*read32) (struct tg3 *, u32);
2100 void (*write32) (struct tg3 *, u32, u32);
2101 u32 (*read32_mbox) (struct tg3 *, u32);
2102 void (*write32_mbox) (struct tg3 *, u32,
2103 u32);
2104 void __iomem *regs;
2105 struct net_device *dev;
2106 struct pci_dev *pdev;
2108 struct tg3_hw_status *hw_status;
2109 dma_addr_t status_mapping;
2110 u32 last_tag;
2112 u32 msg_enable;
2114 /* begin "tx thread" cacheline section */
2115 void (*write32_tx_mbox) (struct tg3 *, u32,
2116 u32);
2117 u32 tx_prod;
2118 u32 tx_cons;
2119 u32 tx_pending;
2121 struct tg3_tx_buffer_desc *tx_ring;
2122 struct tx_ring_info *tx_buffers;
2123 dma_addr_t tx_desc_mapping;
2125 /* begin "rx thread" cacheline section */
2126 void (*write32_rx_mbox) (struct tg3 *, u32,
2127 u32);
2128 u32 rx_rcb_ptr;
2129 u32 rx_std_ptr;
2130 u32 rx_jumbo_ptr;
2131 u32 rx_pending;
2132 u32 rx_jumbo_pending;
2133 #if TG3_VLAN_TAG_USED
2134 struct vlan_group *vlgrp;
2135 #endif
2137 struct tg3_rx_buffer_desc *rx_std;
2138 struct ring_info *rx_std_buffers;
2139 dma_addr_t rx_std_mapping;
2140 u32 rx_std_max_post;
2142 struct tg3_rx_buffer_desc *rx_jumbo;
2143 struct ring_info *rx_jumbo_buffers;
2144 dma_addr_t rx_jumbo_mapping;
2146 struct tg3_rx_buffer_desc *rx_rcb;
2147 dma_addr_t rx_rcb_mapping;
2149 u32 rx_pkt_buf_sz;
2151 /* begin "everything else" cacheline(s) section */
2152 struct net_device_stats net_stats;
2153 struct net_device_stats net_stats_prev;
2154 struct tg3_ethtool_stats estats;
2155 struct tg3_ethtool_stats estats_prev;
2157 unsigned long phy_crc_errors;
2159 u32 rx_offset;
2160 u32 tg3_flags;
2161 #define TG3_FLAG_TAGGED_STATUS 0x00000001
2162 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2163 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
2164 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2165 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2166 #define TG3_FLAG_ENABLE_ASF 0x00000020
2167 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
2168 #define TG3_FLAG_POLL_SERDES 0x00000080
2169 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2170 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2171 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2172 #define TG3_FLAG_WOL_ENABLE 0x00000800
2173 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2174 #define TG3_FLAG_NVRAM 0x00002000
2175 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2176 #define TG3_FLAG_RX_PAUSE 0x00008000
2177 #define TG3_FLAG_TX_PAUSE 0x00010000
2178 #define TG3_FLAG_PCIX_MODE 0x00020000
2179 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2180 #define TG3_FLAG_PCI_32BIT 0x00080000
2181 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2182 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2183 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2184 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2185 #define TG3_FLAG_10_100_ONLY 0x01000000
2186 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2187 #define TG3_FLAG_IN_RESET_TASK 0x04000000
2188 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
2189 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
2190 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
2191 #define TG3_FLAG_SPLIT_MODE 0x40000000
2192 #define TG3_FLAG_INIT_COMPLETE 0x80000000
2193 u32 tg3_flags2;
2194 #define TG3_FLG2_RESTART_TIMER 0x00000001
2195 #define TG3_FLG2_HW_TSO_1_BUG 0x00000002
2196 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2197 #define TG3_FLG2_IS_5788 0x00000008
2198 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
2199 #define TG3_FLG2_TSO_CAPABLE 0x00000020
2200 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
2201 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2202 #define TG3_FLG2_PHY_BER_BUG 0x00000100
2203 #define TG3_FLG2_PCI_EXPRESS 0x00000200
2204 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2205 #define TG3_FLG2_HW_AUTONEG 0x00000800
2206 #define TG3_FLG2_PHY_JUST_INITTED 0x00001000
2207 #define TG3_FLG2_PHY_SERDES 0x00002000
2208 #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2209 #define TG3_FLG2_FLASH 0x00008000
2210 #define TG3_FLG2_HW_TSO_1 0x00010000
2211 #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2212 #define TG3_FLG2_5705_PLUS 0x00040000
2213 #define TG3_FLG2_5750_PLUS 0x00080000
2214 #define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2215 #define TG3_FLG2_USING_MSI 0x00200000
2216 #define TG3_FLG2_JUMBO_CAPABLE 0x00400000
2217 #define TG3_FLG2_MII_SERDES 0x00800000
2218 #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2219 TG3_FLG2_MII_SERDES)
2220 #define TG3_FLG2_PARALLEL_DETECT 0x01000000
2221 #define TG3_FLG2_ICH_WORKAROUND 0x02000000
2222 #define TG3_FLG2_5780_CLASS 0x04000000
2223 #define TG3_FLG2_HW_TSO_2 0x08000000
2224 #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2225 #define TG3_FLG2_1SHOT_MSI 0x10000000
2226 #define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2227 #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2229 u32 split_mode_max_reqs;
2230 #define SPLIT_MODE_5704_MAX_REQ 3
2232 struct timer_list timer;
2233 u16 timer_counter;
2234 u16 timer_multiplier;
2235 u32 timer_offset;
2236 u16 asf_counter;
2237 u16 asf_multiplier;
2239 struct tg3_link_config link_config;
2240 struct tg3_bufmgr_config bufmgr_config;
2242 /* cache h/w values, often passed straight to h/w */
2243 u32 rx_mode;
2244 u32 tx_mode;
2245 u32 mac_mode;
2246 u32 mi_mode;
2247 u32 misc_host_ctrl;
2248 u32 grc_mode;
2249 u32 grc_local_ctrl;
2250 u32 dma_rwctrl;
2251 u32 coalesce_mode;
2253 /* PCI block */
2254 u16 pci_chip_rev_id;
2255 u8 pci_cacheline_sz;
2256 u8 pci_lat_timer;
2257 u8 pci_hdr_type;
2258 u8 pci_bist;
2260 int pm_cap;
2261 int msi_cap;
2263 /* PHY info */
2264 u32 phy_id;
2265 #define PHY_ID_MASK 0xfffffff0
2266 #define PHY_ID_BCM5400 0x60008040
2267 #define PHY_ID_BCM5401 0x60008050
2268 #define PHY_ID_BCM5411 0x60008070
2269 #define PHY_ID_BCM5701 0x60008110
2270 #define PHY_ID_BCM5703 0x60008160
2271 #define PHY_ID_BCM5704 0x60008190
2272 #define PHY_ID_BCM5705 0x600081a0
2273 #define PHY_ID_BCM5750 0x60008180
2274 #define PHY_ID_BCM5752 0x60008100
2275 #define PHY_ID_BCM5714 0x60008340
2276 #define PHY_ID_BCM5780 0x60008350
2277 #define PHY_ID_BCM5755 0xbc050cc0
2278 #define PHY_ID_BCM5787 0xbc050ce0
2279 #define PHY_ID_BCM8002 0x60010140
2280 #define PHY_ID_INVALID 0xffffffff
2281 #define PHY_ID_REV_MASK 0x0000000f
2282 #define PHY_REV_BCM5401_B0 0x1
2283 #define PHY_REV_BCM5401_B2 0x3
2284 #define PHY_REV_BCM5401_C0 0x6
2285 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2287 u32 led_ctrl;
2289 char board_part_number[24];
2290 char fw_ver[16];
2291 u32 nic_sram_data_cfg;
2292 u32 pci_clock_ctrl;
2293 struct pci_dev *pdev_peer;
2295 /* This macro assumes the passed PHY ID is already masked
2296 * with PHY_ID_MASK.
2297 */
2298 #define KNOWN_PHY_ID(X) \
2299 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2300 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2301 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2302 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2303 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2304 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2305 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
2307 struct tg3_hw_stats *hw_stats;
2308 dma_addr_t stats_mapping;
2309 struct work_struct reset_task;
2311 int nvram_lock_cnt;
2312 u32 nvram_size;
2313 u32 nvram_pagesize;
2314 u32 nvram_jedecnum;
2316 #define JEDEC_ATMEL 0x1f
2317 #define JEDEC_ST 0x20
2318 #define JEDEC_SAIFUN 0x4f
2319 #define JEDEC_SST 0xbf
2321 #define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
2322 #define ATMEL_AT24C64_PAGE_SIZE (32)
2324 #define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
2325 #define ATMEL_AT24C512_PAGE_SIZE (128)
2327 #define ATMEL_AT45DB0X1B_PAGE_POS 9
2328 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2330 #define ATMEL_AT25F512_PAGE_SIZE 256
2332 #define ST_M45PEX0_PAGE_SIZE 256
2334 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
2336 #define SST_25VF0X0_PAGE_SIZE 4098
2338 struct ethtool_coalesce coal;
2339 };
2341 #endif /* !(_T3_H) */