ia64/linux-2.6.18-xen.hg

view drivers/mtd/maps/scb2_flash.c @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
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1 /*
2 * MTD map driver for BIOS Flash on Intel SCB2 boards
3 * $Id: scb2_flash.c,v 1.12 2005/03/18 14:04:35 gleixner Exp $
4 * Copyright (C) 2002 Sun Microsystems, Inc.
5 * Tim Hockin <thockin@sun.com>
6 *
7 * A few notes on this MTD map:
8 *
9 * This was developed with a small number of SCB2 boards to test on.
10 * Hopefully, Intel has not introducted too many unaccounted variables in the
11 * making of this board.
12 *
13 * The BIOS marks its own memory region as 'reserved' in the e820 map. We
14 * try to request it here, but if it fails, we carry on anyway.
15 *
16 * This is how the chip is attached, so said the schematic:
17 * * a 4 MiB (32 Mib) 16 bit chip
18 * * a 1 MiB memory region
19 * * A20 and A21 pulled up
20 * * D8-D15 ignored
21 * What this means is that, while we are addressing bytes linearly, we are
22 * really addressing words, and discarding the other byte. This means that
23 * the chip MUST BE at least 2 MiB. This also means that every block is
24 * actually half as big as the chip reports. It also means that accesses of
25 * logical address 0 hit higher-address sections of the chip, not physical 0.
26 * One can only hope that these 4MiB x16 chips were a lot cheaper than 1MiB x8
27 * chips.
28 *
29 * This driver assumes the chip is not write-protected by an external signal.
30 * As of the this writing, that is true, but may change, just to spite me.
31 *
32 * The actual BIOS layout has been mostly reverse engineered. Intel BIOS
33 * updates for this board include 10 related (*.bio - &.bi9) binary files and
34 * another separate (*.bbo) binary file. The 10 files are 64k of data + a
35 * small header. If the headers are stripped off, the 10 64k files can be
36 * concatenated into a 640k image. This is your BIOS image, proper. The
37 * separate .bbo file also has a small header. It is the 'Boot Block'
38 * recovery BIOS. Once the header is stripped, no further prep is needed.
39 * As best I can tell, the BIOS is arranged as such:
40 * offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc?
41 * offset 0x50000 to 0xeffff (640k): BIOS proper
42 * offset 0xf0000 ty 0xfffff (64k): Boot Block region
43 *
44 * Intel's BIOS update program flashes the BIOS and Boot Block in separate
45 * steps. Probably a wise thing to do.
46 */
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/kernel.h>
51 #include <linux/init.h>
52 #include <asm/io.h>
53 #include <linux/mtd/mtd.h>
54 #include <linux/mtd/map.h>
55 #include <linux/mtd/cfi.h>
56 #include <linux/pci.h>
57 #include <linux/pci_ids.h>
59 #define MODNAME "scb2_flash"
60 #define SCB2_ADDR 0xfff00000
61 #define SCB2_WINDOW 0x00100000
64 static void __iomem *scb2_ioaddr;
65 static struct mtd_info *scb2_mtd;
66 static struct map_info scb2_map = {
67 .name = "SCB2 BIOS Flash",
68 .size = 0,
69 .bankwidth = 1,
70 };
71 static int region_fail;
73 static int __devinit
74 scb2_fixup_mtd(struct mtd_info *mtd)
75 {
76 int i;
77 int done = 0;
78 struct map_info *map = mtd->priv;
79 struct cfi_private *cfi = map->fldrv_priv;
81 /* barf if this doesn't look right */
82 if (cfi->cfiq->InterfaceDesc != 1) {
83 printk(KERN_ERR MODNAME ": unsupported InterfaceDesc: %#x\n",
84 cfi->cfiq->InterfaceDesc);
85 return -1;
86 }
88 /* I wasn't here. I didn't see. dwmw2. */
90 /* the chip is sometimes bigger than the map - what a waste */
91 mtd->size = map->size;
93 /*
94 * We only REALLY get half the chip, due to the way it is
95 * wired up - D8-D15 are tossed away. We read linear bytes,
96 * but in reality we are getting 1/2 of each 16-bit read,
97 * which LOOKS linear to us. Because CFI code accounts for
98 * things like lock/unlock/erase by eraseregions, we need to
99 * fudge them to reflect this. Erases go like this:
100 * * send an erase to an address
101 * * the chip samples the address and erases the block
102 * * add the block erasesize to the address and repeat
103 * -- the problem is that addresses are 16-bit addressable
104 * -- we end up erasing every-other block
105 */
106 mtd->erasesize /= 2;
107 for (i = 0; i < mtd->numeraseregions; i++) {
108 struct mtd_erase_region_info *region = &mtd->eraseregions[i];
109 region->erasesize /= 2;
110 }
112 /*
113 * If the chip is bigger than the map, it is wired with the high
114 * address lines pulled up. This makes us access the top portion of
115 * the chip, so all our erase-region info is wrong. Start cutting from
116 * the bottom.
117 */
118 for (i = 0; !done && i < mtd->numeraseregions; i++) {
119 struct mtd_erase_region_info *region = &mtd->eraseregions[i];
121 if (region->numblocks * region->erasesize > mtd->size) {
122 region->numblocks = (mtd->size / region->erasesize);
123 done = 1;
124 } else {
125 region->numblocks = 0;
126 }
127 region->offset = 0;
128 }
130 return 0;
131 }
133 /* CSB5's 'Function Control Register' has bits for decoding @ >= 0xffc00000 */
134 #define CSB5_FCR 0x41
135 #define CSB5_FCR_DECODE_ALL 0x0e
136 static int __devinit
137 scb2_flash_probe(struct pci_dev *dev, const struct pci_device_id *ent)
138 {
139 u8 reg;
141 /* enable decoding of the flash region in the south bridge */
142 pci_read_config_byte(dev, CSB5_FCR, &reg);
143 pci_write_config_byte(dev, CSB5_FCR, reg | CSB5_FCR_DECODE_ALL);
145 if (!request_mem_region(SCB2_ADDR, SCB2_WINDOW, scb2_map.name)) {
146 /*
147 * The BIOS seems to mark the flash region as 'reserved'
148 * in the e820 map. Warn and go about our business.
149 */
150 printk(KERN_WARNING MODNAME
151 ": warning - can't reserve rom window, continuing\n");
152 region_fail = 1;
153 }
155 /* remap the IO window (w/o caching) */
156 scb2_ioaddr = ioremap_nocache(SCB2_ADDR, SCB2_WINDOW);
157 if (!scb2_ioaddr) {
158 printk(KERN_ERR MODNAME ": Failed to ioremap window!\n");
159 if (!region_fail)
160 release_mem_region(SCB2_ADDR, SCB2_WINDOW);
161 return -ENOMEM;
162 }
164 scb2_map.phys = SCB2_ADDR;
165 scb2_map.virt = scb2_ioaddr;
166 scb2_map.size = SCB2_WINDOW;
168 simple_map_init(&scb2_map);
170 /* try to find a chip */
171 scb2_mtd = do_map_probe("cfi_probe", &scb2_map);
173 if (!scb2_mtd) {
174 printk(KERN_ERR MODNAME ": flash probe failed!\n");
175 iounmap(scb2_ioaddr);
176 if (!region_fail)
177 release_mem_region(SCB2_ADDR, SCB2_WINDOW);
178 return -ENODEV;
179 }
181 scb2_mtd->owner = THIS_MODULE;
182 if (scb2_fixup_mtd(scb2_mtd) < 0) {
183 del_mtd_device(scb2_mtd);
184 map_destroy(scb2_mtd);
185 iounmap(scb2_ioaddr);
186 if (!region_fail)
187 release_mem_region(SCB2_ADDR, SCB2_WINDOW);
188 return -ENODEV;
189 }
191 printk(KERN_NOTICE MODNAME ": chip size 0x%x at offset 0x%x\n",
192 scb2_mtd->size, SCB2_WINDOW - scb2_mtd->size);
194 add_mtd_device(scb2_mtd);
196 return 0;
197 }
199 static void __devexit
200 scb2_flash_remove(struct pci_dev *dev)
201 {
202 if (!scb2_mtd)
203 return;
205 /* disable flash writes */
206 if (scb2_mtd->lock)
207 scb2_mtd->lock(scb2_mtd, 0, scb2_mtd->size);
209 del_mtd_device(scb2_mtd);
210 map_destroy(scb2_mtd);
212 iounmap(scb2_ioaddr);
213 scb2_ioaddr = NULL;
215 if (!region_fail)
216 release_mem_region(SCB2_ADDR, SCB2_WINDOW);
217 pci_set_drvdata(dev, NULL);
218 }
220 static struct pci_device_id scb2_flash_pci_ids[] = {
221 {
222 .vendor = PCI_VENDOR_ID_SERVERWORKS,
223 .device = PCI_DEVICE_ID_SERVERWORKS_CSB5,
224 .subvendor = PCI_ANY_ID,
225 .subdevice = PCI_ANY_ID
226 },
227 { 0, }
228 };
230 static struct pci_driver scb2_flash_driver = {
231 .name = "Intel SCB2 BIOS Flash",
232 .id_table = scb2_flash_pci_ids,
233 .probe = scb2_flash_probe,
234 .remove = __devexit_p(scb2_flash_remove),
235 };
237 static int __init
238 scb2_flash_init(void)
239 {
240 return pci_register_driver(&scb2_flash_driver);
241 }
243 static void __exit
244 scb2_flash_exit(void)
245 {
246 pci_unregister_driver(&scb2_flash_driver);
247 }
249 module_init(scb2_flash_init);
250 module_exit(scb2_flash_exit);
252 MODULE_LICENSE("GPL");
253 MODULE_AUTHOR("Tim Hockin <thockin@sun.com>");
254 MODULE_DESCRIPTION("MTD map driver for Intel SCB2 BIOS Flash");
255 MODULE_DEVICE_TABLE(pci, scb2_flash_pci_ids);