ia64/linux-2.6.18-xen.hg

view arch/v850/kernel/v850e_cache.c @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
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1 /*
2 * arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
3 *
4 * Copyright (C) 2003 NEC Electronics Corporation
5 * Copyright (C) 2003 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
14 /* This file implements cache control for the rather simple cache used on
15 some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
16 CPU. V850E2 processors have their own (better) cache
17 implementation. */
19 #include <asm/entry.h>
20 #include <asm/cacheflush.h>
21 #include <asm/v850e_cache.h>
23 #define WAIT_UNTIL_CLEAR(value) while (value) {}
25 /* Set caching params via the BHC and DCC registers. */
26 void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
27 {
28 unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
29 register u16 bhc_val asm ("r6") = bhc;
31 /* Read the instruction cache control register (ICC) and confirm
32 that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
33 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
34 V850E_CACHE_ICC = icc;
36 #ifdef V850E_CACHE_DCC
37 /* Configure data-cache. */
38 V850E_CACHE_DCC = dcc;
39 #endif /* V850E_CACHE_DCC */
41 /* Configure caching for various memory regions by writing the BHC
42 register. The documentation says that an instruction _cannot_
43 enable/disable caching for the memory region in which the
44 instruction itself exists; to work around this, we store
45 appropriate instructions into the on-chip RAM area (which is never
46 cached), and briefly jump there to do the work. */
47 #ifdef V850E_CACHE_WRITE_IBS
48 *r0_ram++ = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
49 #endif
50 *r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
51 *r0_ram = 0x5640006b; /* jmp [r11] */
53 asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
54 :: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
55 }
57 static void clear_icache (void)
58 {
59 /* 1. Read the instruction cache control register (ICC) and confirm
60 that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
61 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
63 /* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
64 cleared. Bit 13 of the ICC register is always cleared. */
65 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
67 /* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
68 when clearing way 0 and way 1 at the same time:
69 (a) Set the TCLR0 and TCLR1 bits.
70 (b) Read the TCLR0 and TCLR1 bits to confirm that these bits
71 are cleared.
72 (c) Perform (a) and (b) above again. */
73 V850E_CACHE_ICC |= 0x3;
74 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
76 #ifdef V850E_CACHE_REPEAT_ICC_WRITE
77 /* Do it again. */
78 V850E_CACHE_ICC |= 0x3;
79 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
80 #endif
81 }
83 #ifdef V850E_CACHE_DCC
84 /* Flush or clear (or both) the data cache, depending on the value of FLAGS;
85 the procedure is the same for both, just the control bits used differ (and
86 both may be performed simultaneously). */
87 static void dcache_op (unsigned short flags)
88 {
89 /* 1. Read the data cache control register (DCC) and confirm that bits
90 0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared. */
91 WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
93 /* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
94 depending on the way for which tags are to be cleared. */
95 V850E_CACHE_DCC &= ~0xC000;
97 /* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
98 the way for which tags are to be cleared.
99 ...
100 Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
101 on the way to be data flushed. */
102 V850E_CACHE_DCC |= flags;
104 /* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
105 on the way for which tags were cleared [flushed] and confirm
106 that that bit is cleared. */
107 WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
108 }
109 #endif /* V850E_CACHE_DCC */
111 /* Flushes the contents of the dcache to memory. */
112 static inline void flush_dcache (void)
113 {
114 #ifdef V850E_CACHE_DCC
115 /* We only need to do something if in write-back mode. */
116 if (V850E_CACHE_DCC & 0x0400)
117 dcache_op (0x30);
118 #endif /* V850E_CACHE_DCC */
119 }
121 /* Flushes the contents of the dcache to memory, and then clears it. */
122 static inline void clear_dcache (void)
123 {
124 #ifdef V850E_CACHE_DCC
125 /* We only need to do something if the dcache is enabled. */
126 if (V850E_CACHE_DCC & 0x0C00)
127 dcache_op (0x33);
128 #endif /* V850E_CACHE_DCC */
129 }
131 /* Clears the dcache without flushing to memory first. */
132 static inline void clear_dcache_no_flush (void)
133 {
134 #ifdef V850E_CACHE_DCC
135 /* We only need to do something if the dcache is enabled. */
136 if (V850E_CACHE_DCC & 0x0C00)
137 dcache_op (0x3);
138 #endif /* V850E_CACHE_DCC */
139 }
141 static inline void cache_exec_after_store (void)
142 {
143 flush_dcache ();
144 clear_icache ();
145 }
148 /* Exported functions. */
150 void flush_icache (void)
151 {
152 cache_exec_after_store ();
153 }
155 void flush_icache_range (unsigned long start, unsigned long end)
156 {
157 cache_exec_after_store ();
158 }
160 void flush_icache_page (struct vm_area_struct *vma, struct page *page)
161 {
162 cache_exec_after_store ();
163 }
165 void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
166 unsigned long adr, int len)
167 {
168 cache_exec_after_store ();
169 }
171 void flush_cache_sigtramp (unsigned long addr)
172 {
173 cache_exec_after_store ();
174 }