ia64/linux-2.6.18-xen.hg

view arch/x86_64/kernel/io_apic-xen.c @ 661:7886619f623e

linux/pci-msi: translate Xen-provided PIRQs (take 2)

Previously, the kernel depended upon Xen's NR_IRQS to be no larger
than the kernel's NR_PIRQS.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Sep 08 13:13:35 2008 +0100 (2008-09-08)
parents ad374a7a9f3e
children 509d67fe5120
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #ifdef CONFIG_ACPI
33 #include <acpi/acpi_bus.h>
34 #endif
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/proto.h>
40 #include <asm/mach_apic.h>
41 #include <asm/acpi.h>
42 #include <asm/dma.h>
43 #include <asm/nmi.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 int disable_timer_pin_1 __initdata;
53 #ifndef CONFIG_XEN
54 int timer_over_8254 __initdata = 0;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 #endif
60 static DEFINE_SPINLOCK(ioapic_lock);
61 static DEFINE_SPINLOCK(vector_lock);
63 /*
64 * # of IRQ routing registers
65 */
66 int nr_ioapic_registers[MAX_IO_APICS];
68 /*
69 * Rough estimation of how many shared IRQs there are, can
70 * be changed anytime.
71 */
72 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
73 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75 /*
76 * This is performance-critical, we want to do it O(1)
77 *
78 * the indexing order of this array favors 1:1 mappings
79 * between pins and IRQs.
80 */
82 static struct irq_pin_list {
83 short apic, pin, next;
84 } irq_2_pin[PIN_MAP_SIZE];
86 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
87 #ifdef CONFIG_PCI_MSI
88 #define vector_to_irq(vector) \
89 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #else
91 #define vector_to_irq(vector) (vector)
92 #endif
94 #ifdef CONFIG_XEN
96 #include <xen/interface/xen.h>
97 #include <xen/interface/physdev.h>
98 #include <xen/evtchn.h>
100 /* Fake i8259 */
101 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
102 #define disable_8259A_irq(_irq) ((void)0)
103 #define i8259A_irq_pending(_irq) (0)
105 unsigned long io_apic_irqs;
107 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
108 {
109 struct physdev_apic apic_op;
110 int ret;
112 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
113 apic_op.reg = reg;
114 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
115 if (ret)
116 return ret;
117 return apic_op.value;
118 }
120 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
121 {
122 struct physdev_apic apic_op;
124 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
125 apic_op.reg = reg;
126 apic_op.value = value;
127 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
128 }
130 #define io_apic_read(a,r) xen_io_apic_read(a,r)
131 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
133 #define clear_IO_APIC() ((void)0)
135 #else
137 #ifdef CONFIG_SMP
138 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
139 {
140 unsigned long flags;
141 unsigned int dest;
142 cpumask_t tmp;
144 cpus_and(tmp, mask, cpu_online_map);
145 if (cpus_empty(tmp))
146 tmp = TARGET_CPUS;
148 cpus_and(mask, tmp, CPU_MASK_ALL);
150 dest = cpu_mask_to_apicid(mask);
152 /*
153 * Only the high 8 bits are valid.
154 */
155 dest = SET_APIC_LOGICAL_ID(dest);
157 spin_lock_irqsave(&ioapic_lock, flags);
158 __DO_ACTION(1, = dest, )
159 set_irq_info(irq, mask);
160 spin_unlock_irqrestore(&ioapic_lock, flags);
161 }
162 #endif
164 #endif /* !CONFIG_XEN */
166 /*
167 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
168 * shared ISA-space IRQs, so we have to support them. We are super
169 * fast in the common case, and fast for shared ISA-space IRQs.
170 */
171 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
172 {
173 static int first_free_entry = NR_IRQS;
174 struct irq_pin_list *entry = irq_2_pin + irq;
176 BUG_ON(irq >= NR_IRQS);
177 while (entry->next)
178 entry = irq_2_pin + entry->next;
180 if (entry->pin != -1) {
181 entry->next = first_free_entry;
182 entry = irq_2_pin + entry->next;
183 if (++first_free_entry >= PIN_MAP_SIZE)
184 panic("io_apic.c: ran out of irq_2_pin entries!");
185 }
186 entry->apic = apic;
187 entry->pin = pin;
188 }
190 #ifndef CONFIG_XEN
191 #define __DO_ACTION(R, ACTION, FINAL) \
192 \
193 { \
194 int pin; \
195 struct irq_pin_list *entry = irq_2_pin + irq; \
196 \
197 BUG_ON(irq >= NR_IRQS); \
198 for (;;) { \
199 unsigned int reg; \
200 pin = entry->pin; \
201 if (pin == -1) \
202 break; \
203 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
204 reg ACTION; \
205 io_apic_modify(entry->apic, reg); \
206 if (!entry->next) \
207 break; \
208 entry = irq_2_pin + entry->next; \
209 } \
210 FINAL; \
211 }
213 #define DO_ACTION(name,R,ACTION, FINAL) \
214 \
215 static void name##_IO_APIC_irq (unsigned int irq) \
216 __DO_ACTION(R, ACTION, FINAL)
218 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
219 /* mask = 1 */
220 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
221 /* mask = 0 */
223 static void mask_IO_APIC_irq (unsigned int irq)
224 {
225 unsigned long flags;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 __mask_IO_APIC_irq(irq);
229 spin_unlock_irqrestore(&ioapic_lock, flags);
230 }
232 static void unmask_IO_APIC_irq (unsigned int irq)
233 {
234 unsigned long flags;
236 spin_lock_irqsave(&ioapic_lock, flags);
237 __unmask_IO_APIC_irq(irq);
238 spin_unlock_irqrestore(&ioapic_lock, flags);
239 }
241 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
242 {
243 struct IO_APIC_route_entry entry;
244 unsigned long flags;
246 /* Check delivery_mode to be sure we're not clearing an SMI pin */
247 spin_lock_irqsave(&ioapic_lock, flags);
248 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
249 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
250 spin_unlock_irqrestore(&ioapic_lock, flags);
251 if (entry.delivery_mode == dest_SMI)
252 return;
253 /*
254 * Disable it in the IO-APIC irq-routing table:
255 */
256 memset(&entry, 0, sizeof(entry));
257 entry.mask = 1;
258 spin_lock_irqsave(&ioapic_lock, flags);
259 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
260 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
261 spin_unlock_irqrestore(&ioapic_lock, flags);
262 }
264 static void clear_IO_APIC (void)
265 {
266 int apic, pin;
268 for (apic = 0; apic < nr_ioapics; apic++)
269 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
270 clear_IO_APIC_pin(apic, pin);
271 }
273 #endif /* !CONFIG_XEN */
275 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
277 /*
278 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
279 * specific CPU-side IRQs.
280 */
282 #define MAX_PIRQS 8
283 static int pirq_entries [MAX_PIRQS];
284 static int pirqs_enabled;
285 int skip_ioapic_setup;
286 int ioapic_force;
288 /* dummy parsing: see setup.c */
290 static int __init disable_ioapic_setup(char *str)
291 {
292 skip_ioapic_setup = 1;
293 return 1;
294 }
296 static int __init enable_ioapic_setup(char *str)
297 {
298 ioapic_force = 1;
299 skip_ioapic_setup = 0;
300 return 1;
301 }
303 __setup("noapic", disable_ioapic_setup);
304 __setup("apic", enable_ioapic_setup);
306 #ifndef CONFIG_XEN
307 static int __init setup_disable_8254_timer(char *s)
308 {
309 timer_over_8254 = -1;
310 return 1;
311 }
312 static int __init setup_enable_8254_timer(char *s)
313 {
314 timer_over_8254 = 2;
315 return 1;
316 }
318 __setup("disable_8254_timer", setup_disable_8254_timer);
319 __setup("enable_8254_timer", setup_enable_8254_timer);
320 #endif /* !CONFIG_XEN */
322 #include <asm/pci-direct.h>
323 #include <linux/pci_ids.h>
324 #include <linux/pci.h>
327 #ifdef CONFIG_ACPI
329 static int nvidia_hpet_detected __initdata;
331 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
332 {
333 nvidia_hpet_detected = 1;
334 return 0;
335 }
336 #endif
338 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
339 off. Check for an Nvidia or VIA PCI bridge and turn it off.
340 Use pci direct infrastructure because this runs before the PCI subsystem.
342 Can be overwritten with "apic"
344 And another hack to disable the IOMMU on VIA chipsets.
346 ... and others. Really should move this somewhere else.
348 Kludge-O-Rama. */
349 void __init check_ioapic(void)
350 {
351 int num,slot,func;
352 /* Poor man's PCI discovery */
353 for (num = 0; num < 32; num++) {
354 for (slot = 0; slot < 32; slot++) {
355 for (func = 0; func < 8; func++) {
356 u32 class;
357 u32 vendor;
358 u8 type;
359 class = read_pci_config(num,slot,func,
360 PCI_CLASS_REVISION);
361 if (class == 0xffffffff)
362 break;
364 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
365 continue;
367 vendor = read_pci_config(num, slot, func,
368 PCI_VENDOR_ID);
369 vendor &= 0xffff;
370 switch (vendor) {
371 case PCI_VENDOR_ID_VIA:
372 #ifdef CONFIG_IOMMU
373 if ((end_pfn > MAX_DMA32_PFN ||
374 force_iommu) &&
375 !iommu_aperture_allowed) {
376 printk(KERN_INFO
377 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
378 iommu_aperture_disabled = 1;
379 }
380 #endif
381 return;
382 case PCI_VENDOR_ID_NVIDIA:
383 #ifdef CONFIG_ACPI
384 /*
385 * All timer overrides on Nvidia are
386 * wrong unless HPET is enabled.
387 */
388 nvidia_hpet_detected = 0;
389 acpi_table_parse(ACPI_HPET,
390 nvidia_hpet_check);
391 if (nvidia_hpet_detected == 0) {
392 acpi_skip_timer_override = 1;
393 printk(KERN_INFO "Nvidia board "
394 "detected. Ignoring ACPI "
395 "timer override.\n");
396 }
397 #endif
398 /* RED-PEN skip them on mptables too? */
399 return;
400 case PCI_VENDOR_ID_ATI:
402 /* This should be actually default, but
403 for 2.6.16 let's do it for ATI only where
404 it's really needed. */
405 #ifndef CONFIG_XEN
406 if (timer_over_8254 == 1) {
407 timer_over_8254 = 0;
408 printk(KERN_INFO
409 "ATI board detected. Disabling timer routing over 8254.\n");
410 }
411 #endif
412 return;
413 }
416 /* No multi-function device? */
417 type = read_pci_config_byte(num,slot,func,
418 PCI_HEADER_TYPE);
419 if (!(type & 0x80))
420 break;
421 }
422 }
423 }
424 }
426 static int __init ioapic_pirq_setup(char *str)
427 {
428 int i, max;
429 int ints[MAX_PIRQS+1];
431 get_options(str, ARRAY_SIZE(ints), ints);
433 for (i = 0; i < MAX_PIRQS; i++)
434 pirq_entries[i] = -1;
436 pirqs_enabled = 1;
437 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
438 max = MAX_PIRQS;
439 if (ints[0] < MAX_PIRQS)
440 max = ints[0];
442 for (i = 0; i < max; i++) {
443 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
444 /*
445 * PIRQs are mapped upside down, usually.
446 */
447 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
448 }
449 return 1;
450 }
452 __setup("pirq=", ioapic_pirq_setup);
454 /*
455 * Find the IRQ entry number of a certain pin.
456 */
457 static int find_irq_entry(int apic, int pin, int type)
458 {
459 int i;
461 for (i = 0; i < mp_irq_entries; i++)
462 if (mp_irqs[i].mpc_irqtype == type &&
463 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
464 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
465 mp_irqs[i].mpc_dstirq == pin)
466 return i;
468 return -1;
469 }
471 #ifndef CONFIG_XEN
472 /*
473 * Find the pin to which IRQ[irq] (ISA) is connected
474 */
475 static int __init find_isa_irq_pin(int irq, int type)
476 {
477 int i;
479 for (i = 0; i < mp_irq_entries; i++) {
480 int lbus = mp_irqs[i].mpc_srcbus;
482 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
483 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
484 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
485 (mp_irqs[i].mpc_irqtype == type) &&
486 (mp_irqs[i].mpc_srcbusirq == irq))
488 return mp_irqs[i].mpc_dstirq;
489 }
490 return -1;
491 }
493 static int __init find_isa_irq_apic(int irq, int type)
494 {
495 int i;
497 for (i = 0; i < mp_irq_entries; i++) {
498 int lbus = mp_irqs[i].mpc_srcbus;
500 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
501 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
502 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
503 (mp_irqs[i].mpc_irqtype == type) &&
504 (mp_irqs[i].mpc_srcbusirq == irq))
505 break;
506 }
507 if (i < mp_irq_entries) {
508 int apic;
509 for(apic = 0; apic < nr_ioapics; apic++) {
510 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
511 return apic;
512 }
513 }
515 return -1;
516 }
517 #endif
519 /*
520 * Find a specific PCI IRQ entry.
521 * Not an __init, possibly needed by modules
522 */
523 static int pin_2_irq(int idx, int apic, int pin);
525 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
526 {
527 int apic, i, best_guess = -1;
529 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
530 bus, slot, pin);
531 if (mp_bus_id_to_pci_bus[bus] == -1) {
532 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
533 return -1;
534 }
535 for (i = 0; i < mp_irq_entries; i++) {
536 int lbus = mp_irqs[i].mpc_srcbus;
538 for (apic = 0; apic < nr_ioapics; apic++)
539 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
540 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
541 break;
543 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
544 !mp_irqs[i].mpc_irqtype &&
545 (bus == lbus) &&
546 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
547 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
549 if (!(apic || IO_APIC_IRQ(irq)))
550 continue;
552 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
553 return irq;
554 /*
555 * Use the first all-but-pin matching entry as a
556 * best-guess fuzzy result for broken mptables.
557 */
558 if (best_guess < 0)
559 best_guess = irq;
560 }
561 }
562 BUG_ON(best_guess >= NR_IRQS);
563 return best_guess;
564 }
566 /*
567 * EISA Edge/Level control register, ELCR
568 */
569 static int EISA_ELCR(unsigned int irq)
570 {
571 if (irq < 16) {
572 unsigned int port = 0x4d0 + (irq >> 3);
573 return (inb(port) >> (irq & 7)) & 1;
574 }
575 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
576 return 0;
577 }
579 /* EISA interrupts are always polarity zero and can be edge or level
580 * trigger depending on the ELCR value. If an interrupt is listed as
581 * EISA conforming in the MP table, that means its trigger type must
582 * be read in from the ELCR */
584 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
585 #define default_EISA_polarity(idx) (0)
587 /* ISA interrupts are always polarity zero edge triggered,
588 * when listed as conforming in the MP table. */
590 #define default_ISA_trigger(idx) (0)
591 #define default_ISA_polarity(idx) (0)
593 /* PCI interrupts are always polarity one level triggered,
594 * when listed as conforming in the MP table. */
596 #define default_PCI_trigger(idx) (1)
597 #define default_PCI_polarity(idx) (1)
599 /* MCA interrupts are always polarity zero level triggered,
600 * when listed as conforming in the MP table. */
602 #define default_MCA_trigger(idx) (1)
603 #define default_MCA_polarity(idx) (0)
605 static int __init MPBIOS_polarity(int idx)
606 {
607 int bus = mp_irqs[idx].mpc_srcbus;
608 int polarity;
610 /*
611 * Determine IRQ line polarity (high active or low active):
612 */
613 switch (mp_irqs[idx].mpc_irqflag & 3)
614 {
615 case 0: /* conforms, ie. bus-type dependent polarity */
616 {
617 switch (mp_bus_id_to_type[bus])
618 {
619 case MP_BUS_ISA: /* ISA pin */
620 {
621 polarity = default_ISA_polarity(idx);
622 break;
623 }
624 case MP_BUS_EISA: /* EISA pin */
625 {
626 polarity = default_EISA_polarity(idx);
627 break;
628 }
629 case MP_BUS_PCI: /* PCI pin */
630 {
631 polarity = default_PCI_polarity(idx);
632 break;
633 }
634 case MP_BUS_MCA: /* MCA pin */
635 {
636 polarity = default_MCA_polarity(idx);
637 break;
638 }
639 default:
640 {
641 printk(KERN_WARNING "broken BIOS!!\n");
642 polarity = 1;
643 break;
644 }
645 }
646 break;
647 }
648 case 1: /* high active */
649 {
650 polarity = 0;
651 break;
652 }
653 case 2: /* reserved */
654 {
655 printk(KERN_WARNING "broken BIOS!!\n");
656 polarity = 1;
657 break;
658 }
659 case 3: /* low active */
660 {
661 polarity = 1;
662 break;
663 }
664 default: /* invalid */
665 {
666 printk(KERN_WARNING "broken BIOS!!\n");
667 polarity = 1;
668 break;
669 }
670 }
671 return polarity;
672 }
674 static int MPBIOS_trigger(int idx)
675 {
676 int bus = mp_irqs[idx].mpc_srcbus;
677 int trigger;
679 /*
680 * Determine IRQ trigger mode (edge or level sensitive):
681 */
682 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
683 {
684 case 0: /* conforms, ie. bus-type dependent */
685 {
686 switch (mp_bus_id_to_type[bus])
687 {
688 case MP_BUS_ISA: /* ISA pin */
689 {
690 trigger = default_ISA_trigger(idx);
691 break;
692 }
693 case MP_BUS_EISA: /* EISA pin */
694 {
695 trigger = default_EISA_trigger(idx);
696 break;
697 }
698 case MP_BUS_PCI: /* PCI pin */
699 {
700 trigger = default_PCI_trigger(idx);
701 break;
702 }
703 case MP_BUS_MCA: /* MCA pin */
704 {
705 trigger = default_MCA_trigger(idx);
706 break;
707 }
708 default:
709 {
710 printk(KERN_WARNING "broken BIOS!!\n");
711 trigger = 1;
712 break;
713 }
714 }
715 break;
716 }
717 case 1: /* edge */
718 {
719 trigger = 0;
720 break;
721 }
722 case 2: /* reserved */
723 {
724 printk(KERN_WARNING "broken BIOS!!\n");
725 trigger = 1;
726 break;
727 }
728 case 3: /* level */
729 {
730 trigger = 1;
731 break;
732 }
733 default: /* invalid */
734 {
735 printk(KERN_WARNING "broken BIOS!!\n");
736 trigger = 0;
737 break;
738 }
739 }
740 return trigger;
741 }
743 static inline int irq_polarity(int idx)
744 {
745 return MPBIOS_polarity(idx);
746 }
748 static inline int irq_trigger(int idx)
749 {
750 return MPBIOS_trigger(idx);
751 }
753 static int next_irq = 16;
755 /*
756 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
757 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
758 * from ACPI, which can reach 800 in large boxen.
759 *
760 * Compact the sparse GSI space into a sequential IRQ series and reuse
761 * vectors if possible.
762 */
763 int gsi_irq_sharing(int gsi)
764 {
765 int i, tries, vector;
767 BUG_ON(gsi >= NR_IRQ_VECTORS);
769 if (platform_legacy_irq(gsi))
770 return gsi;
772 if (gsi_2_irq[gsi] != 0xFF)
773 return (int)gsi_2_irq[gsi];
775 tries = NR_IRQS;
776 try_again:
777 vector = assign_irq_vector(gsi);
779 /*
780 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
781 * use of vector and if found, return that IRQ. However, we never want
782 * to share legacy IRQs, which usually have a different trigger mode
783 * than PCI.
784 */
785 for (i = 0; i < NR_IRQS; i++)
786 if (IO_APIC_VECTOR(i) == vector)
787 break;
788 if (platform_legacy_irq(i)) {
789 if (--tries >= 0) {
790 IO_APIC_VECTOR(i) = 0;
791 goto try_again;
792 }
793 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
794 }
795 if (i < NR_IRQS) {
796 gsi_2_irq[gsi] = i;
797 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
798 gsi, vector, i);
799 return i;
800 }
802 i = next_irq++;
803 BUG_ON(i >= NR_IRQS);
804 gsi_2_irq[gsi] = i;
805 IO_APIC_VECTOR(i) = vector;
806 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
807 gsi, vector, i);
808 return i;
809 }
811 static int pin_2_irq(int idx, int apic, int pin)
812 {
813 int irq, i;
814 int bus = mp_irqs[idx].mpc_srcbus;
816 /*
817 * Debugging check, we are in big trouble if this message pops up!
818 */
819 if (mp_irqs[idx].mpc_dstirq != pin)
820 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
822 switch (mp_bus_id_to_type[bus])
823 {
824 case MP_BUS_ISA: /* ISA pin */
825 case MP_BUS_EISA:
826 case MP_BUS_MCA:
827 {
828 irq = mp_irqs[idx].mpc_srcbusirq;
829 break;
830 }
831 case MP_BUS_PCI: /* PCI pin */
832 {
833 /*
834 * PCI IRQs are mapped in order
835 */
836 i = irq = 0;
837 while (i < apic)
838 irq += nr_ioapic_registers[i++];
839 irq += pin;
840 irq = gsi_irq_sharing(irq);
841 break;
842 }
843 default:
844 {
845 printk(KERN_ERR "unknown bus type %d.\n",bus);
846 irq = 0;
847 break;
848 }
849 }
850 BUG_ON(irq >= NR_IRQS);
852 /*
853 * PCI IRQ command line redirection. Yes, limits are hardcoded.
854 */
855 if ((pin >= 16) && (pin <= 23)) {
856 if (pirq_entries[pin-16] != -1) {
857 if (!pirq_entries[pin-16]) {
858 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
859 } else {
860 irq = pirq_entries[pin-16];
861 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
862 pin-16, irq);
863 }
864 }
865 }
866 BUG_ON(irq >= NR_IRQS);
867 return irq;
868 }
870 static inline int IO_APIC_irq_trigger(int irq)
871 {
872 int apic, idx, pin;
874 for (apic = 0; apic < nr_ioapics; apic++) {
875 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
876 idx = find_irq_entry(apic,pin,mp_INT);
877 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
878 return irq_trigger(idx);
879 }
880 }
881 /*
882 * nonexistent IRQs are edge default
883 */
884 return 0;
885 }
887 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
888 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
890 int assign_irq_vector(int irq)
891 {
892 unsigned long flags;
893 int vector;
894 struct physdev_irq irq_op;
896 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
898 spin_lock_irqsave(&vector_lock, flags);
900 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
901 spin_unlock_irqrestore(&vector_lock, flags);
902 return IO_APIC_VECTOR(irq);
903 }
905 irq_op.irq = irq;
906 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
907 spin_unlock_irqrestore(&vector_lock, flags);
908 return -ENOSPC;
909 }
911 vector = irq_op.vector;
912 vector_irq[vector] = irq;
913 if (irq != AUTO_ASSIGN)
914 IO_APIC_VECTOR(irq) = vector;
916 spin_unlock_irqrestore(&vector_lock, flags);
918 return vector;
919 }
921 extern void (*interrupt[NR_IRQS])(void);
922 #ifndef CONFIG_XEN
923 static struct hw_interrupt_type ioapic_level_type;
924 static struct hw_interrupt_type ioapic_edge_type;
926 #define IOAPIC_AUTO -1
927 #define IOAPIC_EDGE 0
928 #define IOAPIC_LEVEL 1
930 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
931 {
932 unsigned idx;
934 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
936 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
937 trigger == IOAPIC_LEVEL)
938 irq_desc[idx].chip = &ioapic_level_type;
939 else
940 irq_desc[idx].chip = &ioapic_edge_type;
941 set_intr_gate(vector, interrupt[idx]);
942 }
943 #else
944 #define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
945 #endif /* !CONFIG_XEN */
947 static void __init setup_IO_APIC_irqs(void)
948 {
949 struct IO_APIC_route_entry entry;
950 int apic, pin, idx, irq, first_notcon = 1, vector;
951 unsigned long flags;
953 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
955 for (apic = 0; apic < nr_ioapics; apic++) {
956 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
958 /*
959 * add it to the IO-APIC irq-routing table:
960 */
961 memset(&entry,0,sizeof(entry));
963 entry.delivery_mode = INT_DELIVERY_MODE;
964 entry.dest_mode = INT_DEST_MODE;
965 entry.mask = 0; /* enable IRQ */
966 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
968 idx = find_irq_entry(apic,pin,mp_INT);
969 if (idx == -1) {
970 if (first_notcon) {
971 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
972 first_notcon = 0;
973 } else
974 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
975 continue;
976 }
978 entry.trigger = irq_trigger(idx);
979 entry.polarity = irq_polarity(idx);
981 if (irq_trigger(idx)) {
982 entry.trigger = 1;
983 entry.mask = 1;
984 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
985 }
987 irq = pin_2_irq(idx, apic, pin);
988 add_pin_to_irq(irq, apic, pin);
990 if (/* !apic && */ !IO_APIC_IRQ(irq))
991 continue;
993 if (IO_APIC_IRQ(irq)) {
994 vector = assign_irq_vector(irq);
995 entry.vector = vector;
997 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
998 if (!apic && (irq < 16))
999 disable_8259A_irq(irq);
1001 spin_lock_irqsave(&ioapic_lock, flags);
1002 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1003 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1004 set_native_irq_info(irq, TARGET_CPUS);
1005 spin_unlock_irqrestore(&ioapic_lock, flags);
1009 if (!first_notcon)
1010 apic_printk(APIC_VERBOSE," not connected.\n");
1013 #ifndef CONFIG_XEN
1014 /*
1015 * Set up the 8259A-master output pin as broadcast to all
1016 * CPUs.
1017 */
1018 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1020 struct IO_APIC_route_entry entry;
1021 unsigned long flags;
1023 memset(&entry,0,sizeof(entry));
1025 disable_8259A_irq(0);
1027 /* mask LVT0 */
1028 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1030 /*
1031 * We use logical delivery to get the timer IRQ
1032 * to the first CPU.
1033 */
1034 entry.dest_mode = INT_DEST_MODE;
1035 entry.mask = 0; /* unmask IRQ now */
1036 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1037 entry.delivery_mode = INT_DELIVERY_MODE;
1038 entry.polarity = 0;
1039 entry.trigger = 0;
1040 entry.vector = vector;
1042 /*
1043 * The timer IRQ doesn't have to know that behind the
1044 * scene we have a 8259A-master in AEOI mode ...
1045 */
1046 irq_desc[0].chip = &ioapic_edge_type;
1048 /*
1049 * Add it to the IO-APIC irq-routing table:
1050 */
1051 spin_lock_irqsave(&ioapic_lock, flags);
1052 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1053 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1054 spin_unlock_irqrestore(&ioapic_lock, flags);
1056 enable_8259A_irq(0);
1059 void __init UNEXPECTED_IO_APIC(void)
1063 void __apicdebuginit print_IO_APIC(void)
1065 int apic, i;
1066 union IO_APIC_reg_00 reg_00;
1067 union IO_APIC_reg_01 reg_01;
1068 union IO_APIC_reg_02 reg_02;
1069 unsigned long flags;
1071 if (apic_verbosity == APIC_QUIET)
1072 return;
1074 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1075 for (i = 0; i < nr_ioapics; i++)
1076 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1077 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1079 /*
1080 * We are a bit conservative about what we expect. We have to
1081 * know about every hardware change ASAP.
1082 */
1083 printk(KERN_INFO "testing the IO APIC.......................\n");
1085 for (apic = 0; apic < nr_ioapics; apic++) {
1087 spin_lock_irqsave(&ioapic_lock, flags);
1088 reg_00.raw = io_apic_read(apic, 0);
1089 reg_01.raw = io_apic_read(apic, 1);
1090 if (reg_01.bits.version >= 0x10)
1091 reg_02.raw = io_apic_read(apic, 2);
1092 spin_unlock_irqrestore(&ioapic_lock, flags);
1094 printk("\n");
1095 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1096 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1097 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1098 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1099 UNEXPECTED_IO_APIC();
1101 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1102 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1103 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1104 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1105 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1106 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1107 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1108 (reg_01.bits.entries != 0x2E) &&
1109 (reg_01.bits.entries != 0x3F) &&
1110 (reg_01.bits.entries != 0x03)
1112 UNEXPECTED_IO_APIC();
1114 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1115 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1116 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1117 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1118 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1119 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1120 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1121 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1123 UNEXPECTED_IO_APIC();
1124 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1125 UNEXPECTED_IO_APIC();
1127 if (reg_01.bits.version >= 0x10) {
1128 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1129 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1130 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1131 UNEXPECTED_IO_APIC();
1134 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1136 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1137 " Stat Dest Deli Vect: \n");
1139 for (i = 0; i <= reg_01.bits.entries; i++) {
1140 struct IO_APIC_route_entry entry;
1142 spin_lock_irqsave(&ioapic_lock, flags);
1143 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1144 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1145 spin_unlock_irqrestore(&ioapic_lock, flags);
1147 printk(KERN_DEBUG " %02x %03X %02X ",
1148 i,
1149 entry.dest.logical.logical_dest,
1150 entry.dest.physical.physical_dest
1151 );
1153 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1154 entry.mask,
1155 entry.trigger,
1156 entry.irr,
1157 entry.polarity,
1158 entry.delivery_status,
1159 entry.dest_mode,
1160 entry.delivery_mode,
1161 entry.vector
1162 );
1165 if (use_pci_vector())
1166 printk(KERN_INFO "Using vector-based indexing\n");
1167 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1168 for (i = 0; i < NR_IRQS; i++) {
1169 struct irq_pin_list *entry = irq_2_pin + i;
1170 if (entry->pin < 0)
1171 continue;
1172 if (use_pci_vector() && !platform_legacy_irq(i))
1173 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1174 else
1175 printk(KERN_DEBUG "IRQ%d ", i);
1176 for (;;) {
1177 printk("-> %d:%d", entry->apic, entry->pin);
1178 if (!entry->next)
1179 break;
1180 entry = irq_2_pin + entry->next;
1182 printk("\n");
1185 printk(KERN_INFO ".................................... done.\n");
1187 return;
1190 static __apicdebuginit void print_APIC_bitfield (int base)
1192 unsigned int v;
1193 int i, j;
1195 if (apic_verbosity == APIC_QUIET)
1196 return;
1198 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1199 for (i = 0; i < 8; i++) {
1200 v = apic_read(base + i*0x10);
1201 for (j = 0; j < 32; j++) {
1202 if (v & (1<<j))
1203 printk("1");
1204 else
1205 printk("0");
1207 printk("\n");
1211 void __apicdebuginit print_local_APIC(void * dummy)
1213 unsigned int v, ver, maxlvt;
1215 if (apic_verbosity == APIC_QUIET)
1216 return;
1218 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1219 smp_processor_id(), hard_smp_processor_id());
1220 v = apic_read(APIC_ID);
1221 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1222 v = apic_read(APIC_LVR);
1223 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1224 ver = GET_APIC_VERSION(v);
1225 maxlvt = get_maxlvt();
1227 v = apic_read(APIC_TASKPRI);
1228 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1230 v = apic_read(APIC_ARBPRI);
1231 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1232 v & APIC_ARBPRI_MASK);
1233 v = apic_read(APIC_PROCPRI);
1234 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1236 v = apic_read(APIC_EOI);
1237 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1238 v = apic_read(APIC_RRR);
1239 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1240 v = apic_read(APIC_LDR);
1241 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1242 v = apic_read(APIC_DFR);
1243 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1244 v = apic_read(APIC_SPIV);
1245 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1247 printk(KERN_DEBUG "... APIC ISR field:\n");
1248 print_APIC_bitfield(APIC_ISR);
1249 printk(KERN_DEBUG "... APIC TMR field:\n");
1250 print_APIC_bitfield(APIC_TMR);
1251 printk(KERN_DEBUG "... APIC IRR field:\n");
1252 print_APIC_bitfield(APIC_IRR);
1254 v = apic_read(APIC_ESR);
1255 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1257 v = apic_read(APIC_ICR);
1258 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1259 v = apic_read(APIC_ICR2);
1260 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1262 v = apic_read(APIC_LVTT);
1263 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1265 if (maxlvt > 3) { /* PC is LVT#4. */
1266 v = apic_read(APIC_LVTPC);
1267 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1269 v = apic_read(APIC_LVT0);
1270 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1271 v = apic_read(APIC_LVT1);
1272 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1274 if (maxlvt > 2) { /* ERR is LVT#3. */
1275 v = apic_read(APIC_LVTERR);
1276 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1279 v = apic_read(APIC_TMICT);
1280 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1281 v = apic_read(APIC_TMCCT);
1282 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1283 v = apic_read(APIC_TDCR);
1284 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1285 printk("\n");
1288 void print_all_local_APICs (void)
1290 on_each_cpu(print_local_APIC, NULL, 1, 1);
1293 void __apicdebuginit print_PIC(void)
1295 unsigned int v;
1296 unsigned long flags;
1298 if (apic_verbosity == APIC_QUIET)
1299 return;
1301 printk(KERN_DEBUG "\nprinting PIC contents\n");
1303 spin_lock_irqsave(&i8259A_lock, flags);
1305 v = inb(0xa1) << 8 | inb(0x21);
1306 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1308 v = inb(0xa0) << 8 | inb(0x20);
1309 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1311 outb(0x0b,0xa0);
1312 outb(0x0b,0x20);
1313 v = inb(0xa0) << 8 | inb(0x20);
1314 outb(0x0a,0xa0);
1315 outb(0x0a,0x20);
1317 spin_unlock_irqrestore(&i8259A_lock, flags);
1319 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1321 v = inb(0x4d1) << 8 | inb(0x4d0);
1322 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1324 #endif /* !CONFIG_XEN */
1326 static void __init enable_IO_APIC(void)
1328 union IO_APIC_reg_01 reg_01;
1329 #ifndef CONFIG_XEN
1330 int i8259_apic, i8259_pin;
1331 #endif
1332 int i, apic;
1333 unsigned long flags;
1335 for (i = 0; i < PIN_MAP_SIZE; i++) {
1336 irq_2_pin[i].pin = -1;
1337 irq_2_pin[i].next = 0;
1339 if (!pirqs_enabled)
1340 for (i = 0; i < MAX_PIRQS; i++)
1341 pirq_entries[i] = -1;
1343 /*
1344 * The number of IO-APIC IRQ registers (== #pins):
1345 */
1346 for (apic = 0; apic < nr_ioapics; apic++) {
1347 spin_lock_irqsave(&ioapic_lock, flags);
1348 reg_01.raw = io_apic_read(apic, 1);
1349 spin_unlock_irqrestore(&ioapic_lock, flags);
1350 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1352 #ifndef CONFIG_XEN
1353 for(apic = 0; apic < nr_ioapics; apic++) {
1354 int pin;
1355 /* See if any of the pins is in ExtINT mode */
1356 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1357 struct IO_APIC_route_entry entry;
1358 spin_lock_irqsave(&ioapic_lock, flags);
1359 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1360 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1361 spin_unlock_irqrestore(&ioapic_lock, flags);
1364 /* If the interrupt line is enabled and in ExtInt mode
1365 * I have found the pin where the i8259 is connected.
1366 */
1367 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1368 ioapic_i8259.apic = apic;
1369 ioapic_i8259.pin = pin;
1370 goto found_i8259;
1374 found_i8259:
1375 /* Look to see what if the MP table has reported the ExtINT */
1376 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1377 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1378 /* Trust the MP table if nothing is setup in the hardware */
1379 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1380 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1381 ioapic_i8259.pin = i8259_pin;
1382 ioapic_i8259.apic = i8259_apic;
1384 /* Complain if the MP table and the hardware disagree */
1385 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1386 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1388 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1390 #endif
1392 /*
1393 * Do not trust the IO-APIC being empty at bootup
1394 */
1395 clear_IO_APIC();
1398 /*
1399 * Not an __init, needed by the reboot code
1400 */
1401 void disable_IO_APIC(void)
1403 /*
1404 * Clear the IO-APIC before rebooting:
1405 */
1406 clear_IO_APIC();
1408 #ifndef CONFIG_XEN
1409 /*
1410 * If the i8259 is routed through an IOAPIC
1411 * Put that IOAPIC in virtual wire mode
1412 * so legacy interrupts can be delivered.
1413 */
1414 if (ioapic_i8259.pin != -1) {
1415 struct IO_APIC_route_entry entry;
1416 unsigned long flags;
1418 memset(&entry, 0, sizeof(entry));
1419 entry.mask = 0; /* Enabled */
1420 entry.trigger = 0; /* Edge */
1421 entry.irr = 0;
1422 entry.polarity = 0; /* High */
1423 entry.delivery_status = 0;
1424 entry.dest_mode = 0; /* Physical */
1425 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1426 entry.vector = 0;
1427 entry.dest.physical.physical_dest =
1428 GET_APIC_ID(apic_read(APIC_ID));
1430 /*
1431 * Add it to the IO-APIC irq-routing table:
1432 */
1433 spin_lock_irqsave(&ioapic_lock, flags);
1434 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1435 *(((int *)&entry)+1));
1436 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1437 *(((int *)&entry)+0));
1438 spin_unlock_irqrestore(&ioapic_lock, flags);
1441 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1442 #endif
1445 /*
1446 * function to set the IO-APIC physical IDs based on the
1447 * values stored in the MPC table.
1449 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1450 */
1452 #ifndef CONFIG_XEN
1453 static void __init setup_ioapic_ids_from_mpc (void)
1455 union IO_APIC_reg_00 reg_00;
1456 int apic;
1457 int i;
1458 unsigned char old_id;
1459 unsigned long flags;
1461 /*
1462 * Set the IOAPIC ID to the value stored in the MPC table.
1463 */
1464 for (apic = 0; apic < nr_ioapics; apic++) {
1466 /* Read the register 0 value */
1467 spin_lock_irqsave(&ioapic_lock, flags);
1468 reg_00.raw = io_apic_read(apic, 0);
1469 spin_unlock_irqrestore(&ioapic_lock, flags);
1471 old_id = mp_ioapics[apic].mpc_apicid;
1474 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1477 /*
1478 * We need to adjust the IRQ routing table
1479 * if the ID changed.
1480 */
1481 if (old_id != mp_ioapics[apic].mpc_apicid)
1482 for (i = 0; i < mp_irq_entries; i++)
1483 if (mp_irqs[i].mpc_dstapic == old_id)
1484 mp_irqs[i].mpc_dstapic
1485 = mp_ioapics[apic].mpc_apicid;
1487 /*
1488 * Read the right value from the MPC table and
1489 * write it into the ID register.
1490 */
1491 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1492 mp_ioapics[apic].mpc_apicid);
1494 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1495 spin_lock_irqsave(&ioapic_lock, flags);
1496 io_apic_write(apic, 0, reg_00.raw);
1497 spin_unlock_irqrestore(&ioapic_lock, flags);
1499 /*
1500 * Sanity check
1501 */
1502 spin_lock_irqsave(&ioapic_lock, flags);
1503 reg_00.raw = io_apic_read(apic, 0);
1504 spin_unlock_irqrestore(&ioapic_lock, flags);
1505 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1506 printk("could not set ID!\n");
1507 else
1508 apic_printk(APIC_VERBOSE," ok.\n");
1511 #else
1512 static void __init setup_ioapic_ids_from_mpc(void) { }
1513 #endif
1515 /*
1516 * There is a nasty bug in some older SMP boards, their mptable lies
1517 * about the timer IRQ. We do the following to work around the situation:
1519 * - timer IRQ defaults to IO-APIC IRQ
1520 * - if this function detects that timer IRQs are defunct, then we fall
1521 * back to ISA timer IRQs
1522 */
1523 #ifndef CONFIG_XEN
1524 static int __init timer_irq_works(void)
1526 unsigned long t1 = jiffies;
1528 local_irq_enable();
1529 /* Let ten ticks pass... */
1530 mdelay((10 * 1000) / HZ);
1532 /*
1533 * Expect a few ticks at least, to be sure some possible
1534 * glue logic does not lock up after one or two first
1535 * ticks in a non-ExtINT mode. Also the local APIC
1536 * might have cached one ExtINT interrupt. Finally, at
1537 * least one tick may be lost due to delays.
1538 */
1540 /* jiffies wrap? */
1541 if (jiffies - t1 > 4)
1542 return 1;
1543 return 0;
1546 /*
1547 * In the SMP+IOAPIC case it might happen that there are an unspecified
1548 * number of pending IRQ events unhandled. These cases are very rare,
1549 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1550 * better to do it this way as thus we do not have to be aware of
1551 * 'pending' interrupts in the IRQ path, except at this point.
1552 */
1553 /*
1554 * Edge triggered needs to resend any interrupt
1555 * that was delayed but this is now handled in the device
1556 * independent code.
1557 */
1559 /*
1560 * Starting up a edge-triggered IO-APIC interrupt is
1561 * nasty - we need to make sure that we get the edge.
1562 * If it is already asserted for some reason, we need
1563 * return 1 to indicate that is was pending.
1565 * This is not complete - we should be able to fake
1566 * an edge even if it isn't on the 8259A...
1567 */
1569 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1571 int was_pending = 0;
1572 unsigned long flags;
1574 spin_lock_irqsave(&ioapic_lock, flags);
1575 if (irq < 16) {
1576 disable_8259A_irq(irq);
1577 if (i8259A_irq_pending(irq))
1578 was_pending = 1;
1580 __unmask_IO_APIC_irq(irq);
1581 spin_unlock_irqrestore(&ioapic_lock, flags);
1583 return was_pending;
1586 /*
1587 * Once we have recorded IRQ_PENDING already, we can mask the
1588 * interrupt for real. This prevents IRQ storms from unhandled
1589 * devices.
1590 */
1591 static void ack_edge_ioapic_irq(unsigned int irq)
1593 move_irq(irq);
1594 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1595 == (IRQ_PENDING | IRQ_DISABLED))
1596 mask_IO_APIC_irq(irq);
1597 ack_APIC_irq();
1600 /*
1601 * Level triggered interrupts can just be masked,
1602 * and shutting down and starting up the interrupt
1603 * is the same as enabling and disabling them -- except
1604 * with a startup need to return a "was pending" value.
1606 * Level triggered interrupts are special because we
1607 * do not touch any IO-APIC register while handling
1608 * them. We ack the APIC in the end-IRQ handler, not
1609 * in the start-IRQ-handler. Protection against reentrance
1610 * from the same interrupt is still provided, both by the
1611 * generic IRQ layer and by the fact that an unacked local
1612 * APIC does not accept IRQs.
1613 */
1614 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1616 unmask_IO_APIC_irq(irq);
1618 return 0; /* don't check for pending */
1621 static void end_level_ioapic_irq (unsigned int irq)
1623 move_irq(irq);
1624 ack_APIC_irq();
1627 #ifdef CONFIG_PCI_MSI
1628 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1630 int irq = vector_to_irq(vector);
1632 return startup_edge_ioapic_irq(irq);
1635 static void ack_edge_ioapic_vector(unsigned int vector)
1637 int irq = vector_to_irq(vector);
1639 move_native_irq(vector);
1640 ack_edge_ioapic_irq(irq);
1643 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1645 int irq = vector_to_irq(vector);
1647 return startup_level_ioapic_irq (irq);
1650 static void end_level_ioapic_vector (unsigned int vector)
1652 int irq = vector_to_irq(vector);
1654 move_native_irq(vector);
1655 end_level_ioapic_irq(irq);
1658 static void mask_IO_APIC_vector (unsigned int vector)
1660 int irq = vector_to_irq(vector);
1662 mask_IO_APIC_irq(irq);
1665 static void unmask_IO_APIC_vector (unsigned int vector)
1667 int irq = vector_to_irq(vector);
1669 unmask_IO_APIC_irq(irq);
1672 #ifdef CONFIG_SMP
1673 static void set_ioapic_affinity_vector (unsigned int vector,
1674 cpumask_t cpu_mask)
1676 int irq = vector_to_irq(vector);
1678 set_native_irq_info(vector, cpu_mask);
1679 set_ioapic_affinity_irq(irq, cpu_mask);
1681 #endif // CONFIG_SMP
1682 #endif // CONFIG_PCI_MSI
1684 static int ioapic_retrigger(unsigned int irq)
1686 send_IPI_self(IO_APIC_VECTOR(irq));
1688 return 1;
1691 /*
1692 * Level and edge triggered IO-APIC interrupts need different handling,
1693 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1694 * handled with the level-triggered descriptor, but that one has slightly
1695 * more overhead. Level-triggered interrupts cannot be handled with the
1696 * edge-triggered handler, without risking IRQ storms and other ugly
1697 * races.
1698 */
1700 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1701 .typename = "IO-APIC-edge",
1702 .startup = startup_edge_ioapic,
1703 .shutdown = shutdown_edge_ioapic,
1704 .enable = enable_edge_ioapic,
1705 .disable = disable_edge_ioapic,
1706 .ack = ack_edge_ioapic,
1707 .end = end_edge_ioapic,
1708 #ifdef CONFIG_SMP
1709 .set_affinity = set_ioapic_affinity,
1710 #endif
1711 .retrigger = ioapic_retrigger,
1712 };
1714 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1715 .typename = "IO-APIC-level",
1716 .startup = startup_level_ioapic,
1717 .shutdown = shutdown_level_ioapic,
1718 .enable = enable_level_ioapic,
1719 .disable = disable_level_ioapic,
1720 .ack = mask_and_ack_level_ioapic,
1721 .end = end_level_ioapic,
1722 #ifdef CONFIG_SMP
1723 .set_affinity = set_ioapic_affinity,
1724 #endif
1725 .retrigger = ioapic_retrigger,
1726 };
1727 #endif /* !CONFIG_XEN */
1729 static inline void init_IO_APIC_traps(void)
1731 int irq;
1733 /*
1734 * NOTE! The local APIC isn't very good at handling
1735 * multiple interrupts at the same interrupt level.
1736 * As the interrupt level is determined by taking the
1737 * vector number and shifting that right by 4, we
1738 * want to spread these out a bit so that they don't
1739 * all fall in the same interrupt level.
1741 * Also, we've got to be careful not to trash gate
1742 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1743 */
1744 for (irq = 0; irq < NR_IRQS ; irq++) {
1745 int tmp = irq;
1746 if (use_pci_vector()) {
1747 if (!platform_legacy_irq(tmp))
1748 if ((tmp = vector_to_irq(tmp)) == -1)
1749 continue;
1751 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1752 /*
1753 * Hmm.. We don't have an entry for this,
1754 * so default to an old-fashioned 8259
1755 * interrupt if we can..
1756 */
1757 if (irq < 16)
1758 make_8259A_irq(irq);
1759 #ifndef CONFIG_XEN
1760 else
1761 /* Strange. Oh, well.. */
1762 irq_desc[irq].chip = &no_irq_type;
1763 #endif
1768 #ifndef CONFIG_XEN
1769 static void enable_lapic_irq (unsigned int irq)
1771 unsigned long v;
1773 v = apic_read(APIC_LVT0);
1774 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1777 static void disable_lapic_irq (unsigned int irq)
1779 unsigned long v;
1781 v = apic_read(APIC_LVT0);
1782 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1785 static void ack_lapic_irq (unsigned int irq)
1787 ack_APIC_irq();
1790 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1792 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1793 .typename = "local-APIC-edge",
1794 .startup = NULL, /* startup_irq() not used for IRQ0 */
1795 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1796 .enable = enable_lapic_irq,
1797 .disable = disable_lapic_irq,
1798 .ack = ack_lapic_irq,
1799 .end = end_lapic_irq,
1800 };
1802 static void setup_nmi (void)
1804 /*
1805 * Dirty trick to enable the NMI watchdog ...
1806 * We put the 8259A master into AEOI mode and
1807 * unmask on all local APICs LVT0 as NMI.
1809 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1810 * is from Maciej W. Rozycki - so we do not have to EOI from
1811 * the NMI handler or the timer interrupt.
1812 */
1813 printk(KERN_INFO "activating NMI Watchdog ...");
1815 enable_NMI_through_LVT0(NULL);
1817 printk(" done.\n");
1820 /*
1821 * This looks a bit hackish but it's about the only one way of sending
1822 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1823 * not support the ExtINT mode, unfortunately. We need to send these
1824 * cycles as some i82489DX-based boards have glue logic that keeps the
1825 * 8259A interrupt line asserted until INTA. --macro
1826 */
1827 static inline void unlock_ExtINT_logic(void)
1829 int apic, pin, i;
1830 struct IO_APIC_route_entry entry0, entry1;
1831 unsigned char save_control, save_freq_select;
1832 unsigned long flags;
1834 pin = find_isa_irq_pin(8, mp_INT);
1835 apic = find_isa_irq_apic(8, mp_INT);
1836 if (pin == -1)
1837 return;
1839 spin_lock_irqsave(&ioapic_lock, flags);
1840 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1841 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1842 spin_unlock_irqrestore(&ioapic_lock, flags);
1843 clear_IO_APIC_pin(apic, pin);
1845 memset(&entry1, 0, sizeof(entry1));
1847 entry1.dest_mode = 0; /* physical delivery */
1848 entry1.mask = 0; /* unmask IRQ now */
1849 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1850 entry1.delivery_mode = dest_ExtINT;
1851 entry1.polarity = entry0.polarity;
1852 entry1.trigger = 0;
1853 entry1.vector = 0;
1855 spin_lock_irqsave(&ioapic_lock, flags);
1856 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1857 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1858 spin_unlock_irqrestore(&ioapic_lock, flags);
1860 save_control = CMOS_READ(RTC_CONTROL);
1861 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1862 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1863 RTC_FREQ_SELECT);
1864 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1866 i = 100;
1867 while (i-- > 0) {
1868 mdelay(10);
1869 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1870 i -= 10;
1873 CMOS_WRITE(save_control, RTC_CONTROL);
1874 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1875 clear_IO_APIC_pin(apic, pin);
1877 spin_lock_irqsave(&ioapic_lock, flags);
1878 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1879 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1880 spin_unlock_irqrestore(&ioapic_lock, flags);
1883 int timer_uses_ioapic_pin_0;
1885 /*
1886 * This code may look a bit paranoid, but it's supposed to cooperate with
1887 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1888 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1889 * fanatically on his truly buggy board.
1891 * FIXME: really need to revamp this for modern platforms only.
1892 */
1893 static inline void check_timer(void)
1895 int apic1, pin1, apic2, pin2;
1896 int vector;
1898 /*
1899 * get/set the timer IRQ vector:
1900 */
1901 disable_8259A_irq(0);
1902 vector = assign_irq_vector(0);
1903 set_intr_gate(vector, interrupt[0]);
1905 /*
1906 * Subtle, code in do_timer_interrupt() expects an AEOI
1907 * mode for the 8259A whenever interrupts are routed
1908 * through I/O APICs. Also IRQ0 has to be enabled in
1909 * the 8259A which implies the virtual wire has to be
1910 * disabled in the local APIC.
1911 */
1912 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1913 init_8259A(1);
1914 if (timer_over_8254 > 0)
1915 enable_8259A_irq(0);
1917 pin1 = find_isa_irq_pin(0, mp_INT);
1918 apic1 = find_isa_irq_apic(0, mp_INT);
1919 pin2 = ioapic_i8259.pin;
1920 apic2 = ioapic_i8259.apic;
1922 if (pin1 == 0)
1923 timer_uses_ioapic_pin_0 = 1;
1925 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1926 vector, apic1, pin1, apic2, pin2);
1928 if (pin1 != -1) {
1929 /*
1930 * Ok, does IRQ0 through the IOAPIC work?
1931 */
1932 unmask_IO_APIC_irq(0);
1933 if (!no_timer_check && timer_irq_works()) {
1934 nmi_watchdog_default();
1935 if (nmi_watchdog == NMI_IO_APIC) {
1936 disable_8259A_irq(0);
1937 setup_nmi();
1938 enable_8259A_irq(0);
1940 if (disable_timer_pin_1 > 0)
1941 clear_IO_APIC_pin(0, pin1);
1942 return;
1944 clear_IO_APIC_pin(apic1, pin1);
1945 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1946 "connected to IO-APIC\n");
1949 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1950 "through the 8259A ... ");
1951 if (pin2 != -1) {
1952 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1953 apic2, pin2);
1954 /*
1955 * legacy devices should be connected to IO APIC #0
1956 */
1957 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1958 if (timer_irq_works()) {
1959 apic_printk(APIC_VERBOSE," works.\n");
1960 nmi_watchdog_default();
1961 if (nmi_watchdog == NMI_IO_APIC) {
1962 setup_nmi();
1964 return;
1966 /*
1967 * Cleanup, just in case ...
1968 */
1969 clear_IO_APIC_pin(apic2, pin2);
1971 apic_printk(APIC_VERBOSE," failed.\n");
1973 if (nmi_watchdog == NMI_IO_APIC) {
1974 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1975 nmi_watchdog = 0;
1978 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1980 disable_8259A_irq(0);
1981 irq_desc[0].chip = &lapic_irq_type;
1982 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1983 enable_8259A_irq(0);
1985 if (timer_irq_works()) {
1986 apic_printk(APIC_VERBOSE," works.\n");
1987 return;
1989 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1990 apic_printk(APIC_VERBOSE," failed.\n");
1992 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1994 init_8259A(0);
1995 make_8259A_irq(0);
1996 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1998 unlock_ExtINT_logic();
2000 if (timer_irq_works()) {
2001 apic_printk(APIC_VERBOSE," works.\n");
2002 return;
2004 apic_printk(APIC_VERBOSE," failed :(.\n");
2005 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2007 #else
2008 #define check_timer() ((void)0)
2009 int timer_uses_ioapic_pin_0 = 0;
2010 #endif /* !CONFIG_XEN */
2012 static int __init notimercheck(char *s)
2014 no_timer_check = 1;
2015 return 1;
2017 __setup("no_timer_check", notimercheck);
2019 /*
2021 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2022 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2023 * Linux doesn't really care, as it's not actually used
2024 * for any interrupt handling anyway.
2025 */
2026 #define PIC_IRQS (1<<2)
2028 void __init setup_IO_APIC(void)
2030 enable_IO_APIC();
2032 if (acpi_ioapic)
2033 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2034 else
2035 io_apic_irqs = ~PIC_IRQS;
2037 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2039 /*
2040 * Set up the IO-APIC IRQ routing table.
2041 */
2042 if (!acpi_ioapic)
2043 setup_ioapic_ids_from_mpc();
2044 #ifndef CONFIG_XEN
2045 sync_Arb_IDs();
2046 #endif /* !CONFIG_XEN */
2047 setup_IO_APIC_irqs();
2048 init_IO_APIC_traps();
2049 check_timer();
2050 if (!acpi_ioapic)
2051 print_IO_APIC();
2054 struct sysfs_ioapic_data {
2055 struct sys_device dev;
2056 struct IO_APIC_route_entry entry[0];
2057 };
2058 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2060 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2062 struct IO_APIC_route_entry *entry;
2063 struct sysfs_ioapic_data *data;
2064 unsigned long flags;
2065 int i;
2067 data = container_of(dev, struct sysfs_ioapic_data, dev);
2068 entry = data->entry;
2069 spin_lock_irqsave(&ioapic_lock, flags);
2070 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2071 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2072 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2074 spin_unlock_irqrestore(&ioapic_lock, flags);
2076 return 0;
2079 static int ioapic_resume(struct sys_device *dev)
2081 struct IO_APIC_route_entry *entry;
2082 struct sysfs_ioapic_data *data;
2083 unsigned long flags;
2084 union IO_APIC_reg_00 reg_00;
2085 int i;
2087 data = container_of(dev, struct sysfs_ioapic_data, dev);
2088 entry = data->entry;
2090 spin_lock_irqsave(&ioapic_lock, flags);
2091 reg_00.raw = io_apic_read(dev->id, 0);
2092 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2093 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2094 io_apic_write(dev->id, 0, reg_00.raw);
2096 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2097 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2098 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2100 spin_unlock_irqrestore(&ioapic_lock, flags);
2102 return 0;
2105 static struct sysdev_class ioapic_sysdev_class = {
2106 set_kset_name("ioapic"),
2107 .suspend = ioapic_suspend,
2108 .resume = ioapic_resume,
2109 };
2111 static int __init ioapic_init_sysfs(void)
2113 struct sys_device * dev;
2114 int i, size, error = 0;
2116 error = sysdev_class_register(&ioapic_sysdev_class);
2117 if (error)
2118 return error;
2120 for (i = 0; i < nr_ioapics; i++ ) {
2121 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2122 * sizeof(struct IO_APIC_route_entry);
2123 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2124 if (!mp_ioapic_data[i]) {
2125 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2126 continue;
2128 memset(mp_ioapic_data[i], 0, size);
2129 dev = &mp_ioapic_data[i]->dev;
2130 dev->id = i;
2131 dev->cls = &ioapic_sysdev_class;
2132 error = sysdev_register(dev);
2133 if (error) {
2134 kfree(mp_ioapic_data[i]);
2135 mp_ioapic_data[i] = NULL;
2136 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2137 continue;
2141 return 0;
2144 device_initcall(ioapic_init_sysfs);
2146 /* --------------------------------------------------------------------------
2147 ACPI-based IOAPIC Configuration
2148 -------------------------------------------------------------------------- */
2150 #ifdef CONFIG_ACPI
2152 #define IO_APIC_MAX_ID 0xFE
2154 int __init io_apic_get_version (int ioapic)
2156 union IO_APIC_reg_01 reg_01;
2157 unsigned long flags;
2159 spin_lock_irqsave(&ioapic_lock, flags);
2160 reg_01.raw = io_apic_read(ioapic, 1);
2161 spin_unlock_irqrestore(&ioapic_lock, flags);
2163 return reg_01.bits.version;
2167 int __init io_apic_get_redir_entries (int ioapic)
2169 union IO_APIC_reg_01 reg_01;
2170 unsigned long flags;
2172 spin_lock_irqsave(&ioapic_lock, flags);
2173 reg_01.raw = io_apic_read(ioapic, 1);
2174 spin_unlock_irqrestore(&ioapic_lock, flags);
2176 return reg_01.bits.entries;
2180 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2182 struct IO_APIC_route_entry entry;
2183 unsigned long flags;
2185 if (!IO_APIC_IRQ(irq)) {
2186 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2187 ioapic);
2188 return -EINVAL;
2191 /*
2192 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2193 * Note that we mask (disable) IRQs now -- these get enabled when the
2194 * corresponding device driver registers for this IRQ.
2195 */
2197 memset(&entry,0,sizeof(entry));
2199 entry.delivery_mode = INT_DELIVERY_MODE;
2200 entry.dest_mode = INT_DEST_MODE;
2201 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2202 entry.trigger = edge_level;
2203 entry.polarity = active_high_low;
2204 entry.mask = 1; /* Disabled (masked) */
2206 irq = gsi_irq_sharing(irq);
2207 /*
2208 * IRQs < 16 are already in the irq_2_pin[] map
2209 */
2210 if (irq >= 16)
2211 add_pin_to_irq(irq, ioapic, pin);
2213 entry.vector = assign_irq_vector(irq);
2215 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2216 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2217 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2218 edge_level, active_high_low);
2220 ioapic_register_intr(irq, entry.vector, edge_level);
2222 if (!ioapic && (irq < 16))
2223 disable_8259A_irq(irq);
2225 spin_lock_irqsave(&ioapic_lock, flags);
2226 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2227 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2228 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2229 spin_unlock_irqrestore(&ioapic_lock, flags);
2231 return 0;
2234 #endif /* CONFIG_ACPI */
2237 #ifndef CONFIG_XEN
2238 /*
2239 * This function currently is only a helper for the i386 smp boot process where
2240 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2241 * so mask in all cases should simply be TARGET_CPUS
2242 */
2243 #ifdef CONFIG_SMP
2244 void __init setup_ioapic_dest(void)
2246 int pin, ioapic, irq, irq_entry;
2248 if (skip_ioapic_setup == 1)
2249 return;
2251 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2252 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2253 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2254 if (irq_entry == -1)
2255 continue;
2256 irq = pin_2_irq(irq_entry, ioapic, pin);
2257 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2262 #endif
2263 #endif /* !CONFIG_XEN */