ia64/linux-2.6.18-xen.hg

view arch/i386/kernel/io_apic-xen.c @ 661:7886619f623e

linux/pci-msi: translate Xen-provided PIRQs (take 2)

Previously, the kernel depended upon Xen's NR_IRQS to be no larger
than the kernel's NR_PIRQS.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Sep 08 13:13:35 2008 +0100 (2008-09-08)
parents ad374a7a9f3e
children 509d67fe5120
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
35 #include <asm/io.h>
36 #include <asm/smp.h>
37 #include <asm/desc.h>
38 #include <asm/timer.h>
39 #include <asm/i8259.h>
40 #include <asm/nmi.h>
42 #include <mach_apic.h>
44 #include "io_ports.h"
46 #ifdef CONFIG_XEN
48 #include <xen/interface/xen.h>
49 #include <xen/interface/physdev.h>
50 #include <xen/evtchn.h>
52 /* Fake i8259 */
53 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
54 #define disable_8259A_irq(_irq) ((void)0)
55 #define i8259A_irq_pending(_irq) (0)
57 unsigned long io_apic_irqs;
59 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
60 {
61 struct physdev_apic apic_op;
62 int ret;
64 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
65 apic_op.reg = reg;
66 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
67 if (ret)
68 return ret;
69 return apic_op.value;
70 }
72 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
73 {
74 struct physdev_apic apic_op;
76 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
77 apic_op.reg = reg;
78 apic_op.value = value;
79 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
80 }
82 #define io_apic_read(a,r) xen_io_apic_read(a,r)
83 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
85 #endif /* CONFIG_XEN */
87 int (*ioapic_renumber_irq)(int ioapic, int irq);
88 atomic_t irq_mis_count;
90 /* Where if anywhere is the i8259 connect in external int mode */
91 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
93 static DEFINE_SPINLOCK(ioapic_lock);
94 static DEFINE_SPINLOCK(vector_lock);
96 int timer_over_8254 __initdata = 1;
98 /*
99 * Is the SiS APIC rmw bug present ?
100 * -1 = don't know, 0 = no, 1 = yes
101 */
102 int sis_apic_bug = -1;
104 /*
105 * # of IRQ routing registers
106 */
107 int nr_ioapic_registers[MAX_IO_APICS];
109 int disable_timer_pin_1 __initdata;
111 /*
112 * Rough estimation of how many shared IRQs there are, can
113 * be changed anytime.
114 */
115 #define MAX_PLUS_SHARED_IRQS NR_IRQS
116 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
118 /*
119 * This is performance-critical, we want to do it O(1)
120 *
121 * the indexing order of this array favors 1:1 mappings
122 * between pins and IRQs.
123 */
125 static struct irq_pin_list {
126 int apic, pin, next;
127 } irq_2_pin[PIN_MAP_SIZE];
129 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
130 #ifdef CONFIG_PCI_MSI
131 #define vector_to_irq(vector) \
132 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
133 #else
134 #define vector_to_irq(vector) (vector)
135 #endif
137 /*
138 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
139 * shared ISA-space IRQs, so we have to support them. We are super
140 * fast in the common case, and fast for shared ISA-space IRQs.
141 */
142 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
143 {
144 static int first_free_entry = NR_IRQS;
145 struct irq_pin_list *entry = irq_2_pin + irq;
147 while (entry->next)
148 entry = irq_2_pin + entry->next;
150 if (entry->pin != -1) {
151 entry->next = first_free_entry;
152 entry = irq_2_pin + entry->next;
153 if (++first_free_entry >= PIN_MAP_SIZE)
154 panic("io_apic.c: whoops");
155 }
156 entry->apic = apic;
157 entry->pin = pin;
158 }
160 #ifdef CONFIG_XEN
161 #define clear_IO_APIC() ((void)0)
162 #else
163 /*
164 * Reroute an IRQ to a different pin.
165 */
166 static void __init replace_pin_at_irq(unsigned int irq,
167 int oldapic, int oldpin,
168 int newapic, int newpin)
169 {
170 struct irq_pin_list *entry = irq_2_pin + irq;
172 while (1) {
173 if (entry->apic == oldapic && entry->pin == oldpin) {
174 entry->apic = newapic;
175 entry->pin = newpin;
176 }
177 if (!entry->next)
178 break;
179 entry = irq_2_pin + entry->next;
180 }
181 }
183 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
184 {
185 struct irq_pin_list *entry = irq_2_pin + irq;
186 unsigned int pin, reg;
188 for (;;) {
189 pin = entry->pin;
190 if (pin == -1)
191 break;
192 reg = io_apic_read(entry->apic, 0x10 + pin*2);
193 reg &= ~disable;
194 reg |= enable;
195 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
196 if (!entry->next)
197 break;
198 entry = irq_2_pin + entry->next;
199 }
200 }
202 /* mask = 1 */
203 static void __mask_IO_APIC_irq (unsigned int irq)
204 {
205 __modify_IO_APIC_irq(irq, 0x00010000, 0);
206 }
208 /* mask = 0 */
209 static void __unmask_IO_APIC_irq (unsigned int irq)
210 {
211 __modify_IO_APIC_irq(irq, 0, 0x00010000);
212 }
214 /* mask = 1, trigger = 0 */
215 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
216 {
217 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
218 }
220 /* mask = 0, trigger = 1 */
221 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
222 {
223 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
224 }
226 static void mask_IO_APIC_irq (unsigned int irq)
227 {
228 unsigned long flags;
230 spin_lock_irqsave(&ioapic_lock, flags);
231 __mask_IO_APIC_irq(irq);
232 spin_unlock_irqrestore(&ioapic_lock, flags);
233 }
235 static void unmask_IO_APIC_irq (unsigned int irq)
236 {
237 unsigned long flags;
239 spin_lock_irqsave(&ioapic_lock, flags);
240 __unmask_IO_APIC_irq(irq);
241 spin_unlock_irqrestore(&ioapic_lock, flags);
242 }
244 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
245 {
246 struct IO_APIC_route_entry entry;
247 unsigned long flags;
249 /* Check delivery_mode to be sure we're not clearing an SMI pin */
250 spin_lock_irqsave(&ioapic_lock, flags);
251 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
252 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
253 spin_unlock_irqrestore(&ioapic_lock, flags);
254 if (entry.delivery_mode == dest_SMI)
255 return;
257 /*
258 * Disable it in the IO-APIC irq-routing table:
259 */
260 memset(&entry, 0, sizeof(entry));
261 entry.mask = 1;
262 spin_lock_irqsave(&ioapic_lock, flags);
263 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
264 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
265 spin_unlock_irqrestore(&ioapic_lock, flags);
266 }
268 static void clear_IO_APIC (void)
269 {
270 int apic, pin;
272 for (apic = 0; apic < nr_ioapics; apic++)
273 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
274 clear_IO_APIC_pin(apic, pin);
275 }
277 #ifdef CONFIG_SMP
278 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
279 {
280 unsigned long flags;
281 int pin;
282 struct irq_pin_list *entry = irq_2_pin + irq;
283 unsigned int apicid_value;
284 cpumask_t tmp;
286 cpus_and(tmp, cpumask, cpu_online_map);
287 if (cpus_empty(tmp))
288 tmp = TARGET_CPUS;
290 cpus_and(cpumask, tmp, CPU_MASK_ALL);
292 apicid_value = cpu_mask_to_apicid(cpumask);
293 /* Prepare to do the io_apic_write */
294 apicid_value = apicid_value << 24;
295 spin_lock_irqsave(&ioapic_lock, flags);
296 for (;;) {
297 pin = entry->pin;
298 if (pin == -1)
299 break;
300 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
301 if (!entry->next)
302 break;
303 entry = irq_2_pin + entry->next;
304 }
305 set_irq_info(irq, cpumask);
306 spin_unlock_irqrestore(&ioapic_lock, flags);
307 }
309 #if defined(CONFIG_IRQBALANCE)
310 # include <asm/processor.h> /* kernel_thread() */
311 # include <linux/kernel_stat.h> /* kstat */
312 # include <linux/slab.h> /* kmalloc() */
313 # include <linux/timer.h> /* time_after() */
315 #ifdef CONFIG_BALANCED_IRQ_DEBUG
316 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
317 # define Dprintk(x...) do { TDprintk(x); } while (0)
318 # else
319 # define TDprintk(x...)
320 # define Dprintk(x...)
321 # endif
323 #define IRQBALANCE_CHECK_ARCH -999
324 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
325 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
326 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
327 #define BALANCED_IRQ_LESS_DELTA (HZ)
329 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
330 static int physical_balance __read_mostly;
331 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
333 static struct irq_cpu_info {
334 unsigned long * last_irq;
335 unsigned long * irq_delta;
336 unsigned long irq;
337 } irq_cpu_data[NR_CPUS];
339 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
340 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
341 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
343 #define IDLE_ENOUGH(cpu,now) \
344 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
346 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
348 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
350 static cpumask_t balance_irq_affinity[NR_IRQS] = {
351 [0 ... NR_IRQS-1] = CPU_MASK_ALL
352 };
354 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
355 {
356 balance_irq_affinity[irq] = mask;
357 }
359 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
360 unsigned long now, int direction)
361 {
362 int search_idle = 1;
363 int cpu = curr_cpu;
365 goto inside;
367 do {
368 if (unlikely(cpu == curr_cpu))
369 search_idle = 0;
370 inside:
371 if (direction == 1) {
372 cpu++;
373 if (cpu >= NR_CPUS)
374 cpu = 0;
375 } else {
376 cpu--;
377 if (cpu == -1)
378 cpu = NR_CPUS-1;
379 }
380 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
381 (search_idle && !IDLE_ENOUGH(cpu,now)));
383 return cpu;
384 }
386 static inline void balance_irq(int cpu, int irq)
387 {
388 unsigned long now = jiffies;
389 cpumask_t allowed_mask;
390 unsigned int new_cpu;
392 if (irqbalance_disabled)
393 return;
395 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
396 new_cpu = move(cpu, allowed_mask, now, 1);
397 if (cpu != new_cpu) {
398 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
399 }
400 }
402 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
403 {
404 int i, j;
405 Dprintk("Rotating IRQs among CPUs.\n");
406 for_each_online_cpu(i) {
407 for (j = 0; j < NR_IRQS; j++) {
408 if (!irq_desc[j].action)
409 continue;
410 /* Is it a significant load ? */
411 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
412 useful_load_threshold)
413 continue;
414 balance_irq(i, j);
415 }
416 }
417 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
418 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
419 return;
420 }
422 static void do_irq_balance(void)
423 {
424 int i, j;
425 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
426 unsigned long move_this_load = 0;
427 int max_loaded = 0, min_loaded = 0;
428 int load;
429 unsigned long useful_load_threshold = balanced_irq_interval + 10;
430 int selected_irq;
431 int tmp_loaded, first_attempt = 1;
432 unsigned long tmp_cpu_irq;
433 unsigned long imbalance = 0;
434 cpumask_t allowed_mask, target_cpu_mask, tmp;
436 for_each_possible_cpu(i) {
437 int package_index;
438 CPU_IRQ(i) = 0;
439 if (!cpu_online(i))
440 continue;
441 package_index = CPU_TO_PACKAGEINDEX(i);
442 for (j = 0; j < NR_IRQS; j++) {
443 unsigned long value_now, delta;
444 /* Is this an active IRQ? */
445 if (!irq_desc[j].action)
446 continue;
447 if ( package_index == i )
448 IRQ_DELTA(package_index,j) = 0;
449 /* Determine the total count per processor per IRQ */
450 value_now = (unsigned long) kstat_cpu(i).irqs[j];
452 /* Determine the activity per processor per IRQ */
453 delta = value_now - LAST_CPU_IRQ(i,j);
455 /* Update last_cpu_irq[][] for the next time */
456 LAST_CPU_IRQ(i,j) = value_now;
458 /* Ignore IRQs whose rate is less than the clock */
459 if (delta < useful_load_threshold)
460 continue;
461 /* update the load for the processor or package total */
462 IRQ_DELTA(package_index,j) += delta;
464 /* Keep track of the higher numbered sibling as well */
465 if (i != package_index)
466 CPU_IRQ(i) += delta;
467 /*
468 * We have sibling A and sibling B in the package
469 *
470 * cpu_irq[A] = load for cpu A + load for cpu B
471 * cpu_irq[B] = load for cpu B
472 */
473 CPU_IRQ(package_index) += delta;
474 }
475 }
476 /* Find the least loaded processor package */
477 for_each_online_cpu(i) {
478 if (i != CPU_TO_PACKAGEINDEX(i))
479 continue;
480 if (min_cpu_irq > CPU_IRQ(i)) {
481 min_cpu_irq = CPU_IRQ(i);
482 min_loaded = i;
483 }
484 }
485 max_cpu_irq = ULONG_MAX;
487 tryanothercpu:
488 /* Look for heaviest loaded processor.
489 * We may come back to get the next heaviest loaded processor.
490 * Skip processors with trivial loads.
491 */
492 tmp_cpu_irq = 0;
493 tmp_loaded = -1;
494 for_each_online_cpu(i) {
495 if (i != CPU_TO_PACKAGEINDEX(i))
496 continue;
497 if (max_cpu_irq <= CPU_IRQ(i))
498 continue;
499 if (tmp_cpu_irq < CPU_IRQ(i)) {
500 tmp_cpu_irq = CPU_IRQ(i);
501 tmp_loaded = i;
502 }
503 }
505 if (tmp_loaded == -1) {
506 /* In the case of small number of heavy interrupt sources,
507 * loading some of the cpus too much. We use Ingo's original
508 * approach to rotate them around.
509 */
510 if (!first_attempt && imbalance >= useful_load_threshold) {
511 rotate_irqs_among_cpus(useful_load_threshold);
512 return;
513 }
514 goto not_worth_the_effort;
515 }
517 first_attempt = 0; /* heaviest search */
518 max_cpu_irq = tmp_cpu_irq; /* load */
519 max_loaded = tmp_loaded; /* processor */
520 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
522 Dprintk("max_loaded cpu = %d\n", max_loaded);
523 Dprintk("min_loaded cpu = %d\n", min_loaded);
524 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
525 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
526 Dprintk("load imbalance = %lu\n", imbalance);
528 /* if imbalance is less than approx 10% of max load, then
529 * observe diminishing returns action. - quit
530 */
531 if (imbalance < (max_cpu_irq >> 3)) {
532 Dprintk("Imbalance too trivial\n");
533 goto not_worth_the_effort;
534 }
536 tryanotherirq:
537 /* if we select an IRQ to move that can't go where we want, then
538 * see if there is another one to try.
539 */
540 move_this_load = 0;
541 selected_irq = -1;
542 for (j = 0; j < NR_IRQS; j++) {
543 /* Is this an active IRQ? */
544 if (!irq_desc[j].action)
545 continue;
546 if (imbalance <= IRQ_DELTA(max_loaded,j))
547 continue;
548 /* Try to find the IRQ that is closest to the imbalance
549 * without going over.
550 */
551 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
552 move_this_load = IRQ_DELTA(max_loaded,j);
553 selected_irq = j;
554 }
555 }
556 if (selected_irq == -1) {
557 goto tryanothercpu;
558 }
560 imbalance = move_this_load;
562 /* For physical_balance case, we accumlated both load
563 * values in the one of the siblings cpu_irq[],
564 * to use the same code for physical and logical processors
565 * as much as possible.
566 *
567 * NOTE: the cpu_irq[] array holds the sum of the load for
568 * sibling A and sibling B in the slot for the lowest numbered
569 * sibling (A), _AND_ the load for sibling B in the slot for
570 * the higher numbered sibling.
571 *
572 * We seek the least loaded sibling by making the comparison
573 * (A+B)/2 vs B
574 */
575 load = CPU_IRQ(min_loaded) >> 1;
576 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
577 if (load > CPU_IRQ(j)) {
578 /* This won't change cpu_sibling_map[min_loaded] */
579 load = CPU_IRQ(j);
580 min_loaded = j;
581 }
582 }
584 cpus_and(allowed_mask,
585 cpu_online_map,
586 balance_irq_affinity[selected_irq]);
587 target_cpu_mask = cpumask_of_cpu(min_loaded);
588 cpus_and(tmp, target_cpu_mask, allowed_mask);
590 if (!cpus_empty(tmp)) {
592 Dprintk("irq = %d moved to cpu = %d\n",
593 selected_irq, min_loaded);
594 /* mark for change destination */
595 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
597 /* Since we made a change, come back sooner to
598 * check for more variation.
599 */
600 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
601 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
602 return;
603 }
604 goto tryanotherirq;
606 not_worth_the_effort:
607 /*
608 * if we did not find an IRQ to move, then adjust the time interval
609 * upward
610 */
611 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
612 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
613 Dprintk("IRQ worth rotating not found\n");
614 return;
615 }
617 static int balanced_irq(void *unused)
618 {
619 int i;
620 unsigned long prev_balance_time = jiffies;
621 long time_remaining = balanced_irq_interval;
623 daemonize("kirqd");
625 /* push everything to CPU 0 to give us a starting point. */
626 for (i = 0 ; i < NR_IRQS ; i++) {
627 irq_desc[i].pending_mask = cpumask_of_cpu(0);
628 set_pending_irq(i, cpumask_of_cpu(0));
629 }
631 for ( ; ; ) {
632 time_remaining = schedule_timeout_interruptible(time_remaining);
633 try_to_freeze();
634 if (time_after(jiffies,
635 prev_balance_time+balanced_irq_interval)) {
636 preempt_disable();
637 do_irq_balance();
638 prev_balance_time = jiffies;
639 time_remaining = balanced_irq_interval;
640 preempt_enable();
641 }
642 }
643 return 0;
644 }
646 static int __init balanced_irq_init(void)
647 {
648 int i;
649 struct cpuinfo_x86 *c;
650 cpumask_t tmp;
652 cpus_shift_right(tmp, cpu_online_map, 2);
653 c = &boot_cpu_data;
654 /* When not overwritten by the command line ask subarchitecture. */
655 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
656 irqbalance_disabled = NO_BALANCE_IRQ;
657 if (irqbalance_disabled)
658 return 0;
660 /* disable irqbalance completely if there is only one processor online */
661 if (num_online_cpus() < 2) {
662 irqbalance_disabled = 1;
663 return 0;
664 }
665 /*
666 * Enable physical balance only if more than 1 physical processor
667 * is present
668 */
669 if (smp_num_siblings > 1 && !cpus_empty(tmp))
670 physical_balance = 1;
672 for_each_online_cpu(i) {
673 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
674 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
675 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
676 printk(KERN_ERR "balanced_irq_init: out of memory");
677 goto failed;
678 }
679 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
680 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
681 }
683 printk(KERN_INFO "Starting balanced_irq\n");
684 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
685 return 0;
686 else
687 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
688 failed:
689 for_each_possible_cpu(i) {
690 kfree(irq_cpu_data[i].irq_delta);
691 irq_cpu_data[i].irq_delta = NULL;
692 kfree(irq_cpu_data[i].last_irq);
693 irq_cpu_data[i].last_irq = NULL;
694 }
695 return 0;
696 }
698 int __init irqbalance_disable(char *str)
699 {
700 irqbalance_disabled = 1;
701 return 1;
702 }
704 __setup("noirqbalance", irqbalance_disable);
706 late_initcall(balanced_irq_init);
707 #endif /* CONFIG_IRQBALANCE */
708 #endif /* CONFIG_SMP */
709 #endif
711 #ifndef CONFIG_SMP
712 void fastcall send_IPI_self(int vector)
713 {
714 #ifndef CONFIG_XEN
715 unsigned int cfg;
717 /*
718 * Wait for idle.
719 */
720 apic_wait_icr_idle();
721 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
722 /*
723 * Send the IPI. The write to APIC_ICR fires this off.
724 */
725 apic_write_around(APIC_ICR, cfg);
726 #endif
727 }
728 #endif /* !CONFIG_SMP */
731 /*
732 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
733 * specific CPU-side IRQs.
734 */
736 #define MAX_PIRQS 8
737 static int pirq_entries [MAX_PIRQS];
738 static int pirqs_enabled;
739 int skip_ioapic_setup;
741 static int __init ioapic_setup(char *str)
742 {
743 skip_ioapic_setup = 1;
744 return 1;
745 }
747 __setup("noapic", ioapic_setup);
749 static int __init ioapic_pirq_setup(char *str)
750 {
751 int i, max;
752 int ints[MAX_PIRQS+1];
754 get_options(str, ARRAY_SIZE(ints), ints);
756 for (i = 0; i < MAX_PIRQS; i++)
757 pirq_entries[i] = -1;
759 pirqs_enabled = 1;
760 apic_printk(APIC_VERBOSE, KERN_INFO
761 "PIRQ redirection, working around broken MP-BIOS.\n");
762 max = MAX_PIRQS;
763 if (ints[0] < MAX_PIRQS)
764 max = ints[0];
766 for (i = 0; i < max; i++) {
767 apic_printk(APIC_VERBOSE, KERN_DEBUG
768 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
769 /*
770 * PIRQs are mapped upside down, usually.
771 */
772 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
773 }
774 return 1;
775 }
777 __setup("pirq=", ioapic_pirq_setup);
779 /*
780 * Find the IRQ entry number of a certain pin.
781 */
782 static int find_irq_entry(int apic, int pin, int type)
783 {
784 int i;
786 for (i = 0; i < mp_irq_entries; i++)
787 if (mp_irqs[i].mpc_irqtype == type &&
788 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
789 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
790 mp_irqs[i].mpc_dstirq == pin)
791 return i;
793 return -1;
794 }
796 /*
797 * Find the pin to which IRQ[irq] (ISA) is connected
798 */
799 static int __init find_isa_irq_pin(int irq, int type)
800 {
801 int i;
803 for (i = 0; i < mp_irq_entries; i++) {
804 int lbus = mp_irqs[i].mpc_srcbus;
806 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
807 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
808 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
809 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
810 ) &&
811 (mp_irqs[i].mpc_irqtype == type) &&
812 (mp_irqs[i].mpc_srcbusirq == irq))
814 return mp_irqs[i].mpc_dstirq;
815 }
816 return -1;
817 }
819 static int __init find_isa_irq_apic(int irq, int type)
820 {
821 int i;
823 for (i = 0; i < mp_irq_entries; i++) {
824 int lbus = mp_irqs[i].mpc_srcbus;
826 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
827 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
828 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
829 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
830 ) &&
831 (mp_irqs[i].mpc_irqtype == type) &&
832 (mp_irqs[i].mpc_srcbusirq == irq))
833 break;
834 }
835 if (i < mp_irq_entries) {
836 int apic;
837 for(apic = 0; apic < nr_ioapics; apic++) {
838 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
839 return apic;
840 }
841 }
843 return -1;
844 }
846 /*
847 * Find a specific PCI IRQ entry.
848 * Not an __init, possibly needed by modules
849 */
850 static int pin_2_irq(int idx, int apic, int pin);
852 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
853 {
854 int apic, i, best_guess = -1;
856 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
857 "slot:%d, pin:%d.\n", bus, slot, pin);
858 if (mp_bus_id_to_pci_bus[bus] == -1) {
859 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
860 return -1;
861 }
862 for (i = 0; i < mp_irq_entries; i++) {
863 int lbus = mp_irqs[i].mpc_srcbus;
865 for (apic = 0; apic < nr_ioapics; apic++)
866 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
867 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
868 break;
870 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
871 !mp_irqs[i].mpc_irqtype &&
872 (bus == lbus) &&
873 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
874 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
876 if (!(apic || IO_APIC_IRQ(irq)))
877 continue;
879 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
880 return irq;
881 /*
882 * Use the first all-but-pin matching entry as a
883 * best-guess fuzzy result for broken mptables.
884 */
885 if (best_guess < 0)
886 best_guess = irq;
887 }
888 }
889 return best_guess;
890 }
891 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
893 /*
894 * This function currently is only a helper for the i386 smp boot process where
895 * we need to reprogram the ioredtbls to cater for the cpus which have come online
896 * so mask in all cases should simply be TARGET_CPUS
897 */
898 #ifdef CONFIG_SMP
899 #ifndef CONFIG_XEN
900 void __init setup_ioapic_dest(void)
901 {
902 int pin, ioapic, irq, irq_entry;
904 if (skip_ioapic_setup == 1)
905 return;
907 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
908 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
909 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
910 if (irq_entry == -1)
911 continue;
912 irq = pin_2_irq(irq_entry, ioapic, pin);
913 set_ioapic_affinity_irq(irq, TARGET_CPUS);
914 }
916 }
917 }
918 #endif /* !CONFIG_XEN */
919 #endif
921 /*
922 * EISA Edge/Level control register, ELCR
923 */
924 static int EISA_ELCR(unsigned int irq)
925 {
926 if (irq < 16) {
927 unsigned int port = 0x4d0 + (irq >> 3);
928 return (inb(port) >> (irq & 7)) & 1;
929 }
930 apic_printk(APIC_VERBOSE, KERN_INFO
931 "Broken MPtable reports ISA irq %d\n", irq);
932 return 0;
933 }
935 /* EISA interrupts are always polarity zero and can be edge or level
936 * trigger depending on the ELCR value. If an interrupt is listed as
937 * EISA conforming in the MP table, that means its trigger type must
938 * be read in from the ELCR */
940 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
941 #define default_EISA_polarity(idx) (0)
943 /* ISA interrupts are always polarity zero edge triggered,
944 * when listed as conforming in the MP table. */
946 #define default_ISA_trigger(idx) (0)
947 #define default_ISA_polarity(idx) (0)
949 /* PCI interrupts are always polarity one level triggered,
950 * when listed as conforming in the MP table. */
952 #define default_PCI_trigger(idx) (1)
953 #define default_PCI_polarity(idx) (1)
955 /* MCA interrupts are always polarity zero level triggered,
956 * when listed as conforming in the MP table. */
958 #define default_MCA_trigger(idx) (1)
959 #define default_MCA_polarity(idx) (0)
961 /* NEC98 interrupts are always polarity zero edge triggered,
962 * when listed as conforming in the MP table. */
964 #define default_NEC98_trigger(idx) (0)
965 #define default_NEC98_polarity(idx) (0)
967 static int __init MPBIOS_polarity(int idx)
968 {
969 int bus = mp_irqs[idx].mpc_srcbus;
970 int polarity;
972 /*
973 * Determine IRQ line polarity (high active or low active):
974 */
975 switch (mp_irqs[idx].mpc_irqflag & 3)
976 {
977 case 0: /* conforms, ie. bus-type dependent polarity */
978 {
979 switch (mp_bus_id_to_type[bus])
980 {
981 case MP_BUS_ISA: /* ISA pin */
982 {
983 polarity = default_ISA_polarity(idx);
984 break;
985 }
986 case MP_BUS_EISA: /* EISA pin */
987 {
988 polarity = default_EISA_polarity(idx);
989 break;
990 }
991 case MP_BUS_PCI: /* PCI pin */
992 {
993 polarity = default_PCI_polarity(idx);
994 break;
995 }
996 case MP_BUS_MCA: /* MCA pin */
997 {
998 polarity = default_MCA_polarity(idx);
999 break;
1001 case MP_BUS_NEC98: /* NEC 98 pin */
1003 polarity = default_NEC98_polarity(idx);
1004 break;
1006 default:
1008 printk(KERN_WARNING "broken BIOS!!\n");
1009 polarity = 1;
1010 break;
1013 break;
1015 case 1: /* high active */
1017 polarity = 0;
1018 break;
1020 case 2: /* reserved */
1022 printk(KERN_WARNING "broken BIOS!!\n");
1023 polarity = 1;
1024 break;
1026 case 3: /* low active */
1028 polarity = 1;
1029 break;
1031 default: /* invalid */
1033 printk(KERN_WARNING "broken BIOS!!\n");
1034 polarity = 1;
1035 break;
1038 return polarity;
1041 static int MPBIOS_trigger(int idx)
1043 int bus = mp_irqs[idx].mpc_srcbus;
1044 int trigger;
1046 /*
1047 * Determine IRQ trigger mode (edge or level sensitive):
1048 */
1049 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1051 case 0: /* conforms, ie. bus-type dependent */
1053 switch (mp_bus_id_to_type[bus])
1055 case MP_BUS_ISA: /* ISA pin */
1057 trigger = default_ISA_trigger(idx);
1058 break;
1060 case MP_BUS_EISA: /* EISA pin */
1062 trigger = default_EISA_trigger(idx);
1063 break;
1065 case MP_BUS_PCI: /* PCI pin */
1067 trigger = default_PCI_trigger(idx);
1068 break;
1070 case MP_BUS_MCA: /* MCA pin */
1072 trigger = default_MCA_trigger(idx);
1073 break;
1075 case MP_BUS_NEC98: /* NEC 98 pin */
1077 trigger = default_NEC98_trigger(idx);
1078 break;
1080 default:
1082 printk(KERN_WARNING "broken BIOS!!\n");
1083 trigger = 1;
1084 break;
1087 break;
1089 case 1: /* edge */
1091 trigger = 0;
1092 break;
1094 case 2: /* reserved */
1096 printk(KERN_WARNING "broken BIOS!!\n");
1097 trigger = 1;
1098 break;
1100 case 3: /* level */
1102 trigger = 1;
1103 break;
1105 default: /* invalid */
1107 printk(KERN_WARNING "broken BIOS!!\n");
1108 trigger = 0;
1109 break;
1112 return trigger;
1115 static inline int irq_polarity(int idx)
1117 return MPBIOS_polarity(idx);
1120 static inline int irq_trigger(int idx)
1122 return MPBIOS_trigger(idx);
1125 static int pin_2_irq(int idx, int apic, int pin)
1127 int irq, i;
1128 int bus = mp_irqs[idx].mpc_srcbus;
1130 /*
1131 * Debugging check, we are in big trouble if this message pops up!
1132 */
1133 if (mp_irqs[idx].mpc_dstirq != pin)
1134 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1136 switch (mp_bus_id_to_type[bus])
1138 case MP_BUS_ISA: /* ISA pin */
1139 case MP_BUS_EISA:
1140 case MP_BUS_MCA:
1141 case MP_BUS_NEC98:
1143 irq = mp_irqs[idx].mpc_srcbusirq;
1144 break;
1146 case MP_BUS_PCI: /* PCI pin */
1148 /*
1149 * PCI IRQs are mapped in order
1150 */
1151 i = irq = 0;
1152 while (i < apic)
1153 irq += nr_ioapic_registers[i++];
1154 irq += pin;
1156 /*
1157 * For MPS mode, so far only needed by ES7000 platform
1158 */
1159 if (ioapic_renumber_irq)
1160 irq = ioapic_renumber_irq(apic, irq);
1162 break;
1164 default:
1166 printk(KERN_ERR "unknown bus type %d.\n",bus);
1167 irq = 0;
1168 break;
1172 /*
1173 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1174 */
1175 if ((pin >= 16) && (pin <= 23)) {
1176 if (pirq_entries[pin-16] != -1) {
1177 if (!pirq_entries[pin-16]) {
1178 apic_printk(APIC_VERBOSE, KERN_DEBUG
1179 "disabling PIRQ%d\n", pin-16);
1180 } else {
1181 irq = pirq_entries[pin-16];
1182 apic_printk(APIC_VERBOSE, KERN_DEBUG
1183 "using PIRQ%d -> IRQ %d\n",
1184 pin-16, irq);
1188 return irq;
1191 static inline int IO_APIC_irq_trigger(int irq)
1193 int apic, idx, pin;
1195 for (apic = 0; apic < nr_ioapics; apic++) {
1196 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1197 idx = find_irq_entry(apic,pin,mp_INT);
1198 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1199 return irq_trigger(idx);
1202 /*
1203 * nonexistent IRQs are edge default
1204 */
1205 return 0;
1208 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1209 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1211 int assign_irq_vector(int irq)
1213 unsigned long flags;
1214 int vector;
1215 struct physdev_irq irq_op;
1217 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1219 spin_lock_irqsave(&vector_lock, flags);
1221 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1222 spin_unlock_irqrestore(&vector_lock, flags);
1223 return IO_APIC_VECTOR(irq);
1226 irq_op.irq = irq;
1227 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
1228 spin_unlock_irqrestore(&vector_lock, flags);
1229 return -ENOSPC;
1232 vector = irq_op.vector;
1233 vector_irq[vector] = irq;
1234 if (irq != AUTO_ASSIGN)
1235 IO_APIC_VECTOR(irq) = vector;
1237 spin_unlock_irqrestore(&vector_lock, flags);
1239 return vector;
1242 #ifndef CONFIG_XEN
1243 static struct hw_interrupt_type ioapic_level_type;
1244 static struct hw_interrupt_type ioapic_edge_type;
1246 #define IOAPIC_AUTO -1
1247 #define IOAPIC_EDGE 0
1248 #define IOAPIC_LEVEL 1
1250 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1252 unsigned idx;
1254 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1256 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1257 trigger == IOAPIC_LEVEL)
1258 irq_desc[idx].chip = &ioapic_level_type;
1259 else
1260 irq_desc[idx].chip = &ioapic_edge_type;
1261 set_intr_gate(vector, interrupt[idx]);
1263 #else
1264 #define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
1265 #endif
1267 static void __init setup_IO_APIC_irqs(void)
1269 struct IO_APIC_route_entry entry;
1270 int apic, pin, idx, irq, first_notcon = 1, vector;
1271 unsigned long flags;
1273 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1275 for (apic = 0; apic < nr_ioapics; apic++) {
1276 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1278 /*
1279 * add it to the IO-APIC irq-routing table:
1280 */
1281 memset(&entry,0,sizeof(entry));
1283 entry.delivery_mode = INT_DELIVERY_MODE;
1284 entry.dest_mode = INT_DEST_MODE;
1285 entry.mask = 0; /* enable IRQ */
1286 entry.dest.logical.logical_dest =
1287 cpu_mask_to_apicid(TARGET_CPUS);
1289 idx = find_irq_entry(apic,pin,mp_INT);
1290 if (idx == -1) {
1291 if (first_notcon) {
1292 apic_printk(APIC_VERBOSE, KERN_DEBUG
1293 " IO-APIC (apicid-pin) %d-%d",
1294 mp_ioapics[apic].mpc_apicid,
1295 pin);
1296 first_notcon = 0;
1297 } else
1298 apic_printk(APIC_VERBOSE, ", %d-%d",
1299 mp_ioapics[apic].mpc_apicid, pin);
1300 continue;
1303 entry.trigger = irq_trigger(idx);
1304 entry.polarity = irq_polarity(idx);
1306 if (irq_trigger(idx)) {
1307 entry.trigger = 1;
1308 entry.mask = 1;
1311 irq = pin_2_irq(idx, apic, pin);
1312 /*
1313 * skip adding the timer int on secondary nodes, which causes
1314 * a small but painful rift in the time-space continuum
1315 */
1316 if (multi_timer_check(apic, irq))
1317 continue;
1318 else
1319 add_pin_to_irq(irq, apic, pin);
1321 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1322 continue;
1324 if (IO_APIC_IRQ(irq)) {
1325 vector = assign_irq_vector(irq);
1326 entry.vector = vector;
1327 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1329 if (!apic && (irq < 16))
1330 disable_8259A_irq(irq);
1332 spin_lock_irqsave(&ioapic_lock, flags);
1333 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1334 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1335 set_native_irq_info(irq, TARGET_CPUS);
1336 spin_unlock_irqrestore(&ioapic_lock, flags);
1340 if (!first_notcon)
1341 apic_printk(APIC_VERBOSE, " not connected.\n");
1344 /*
1345 * Set up the 8259A-master output pin:
1346 */
1347 #ifndef CONFIG_XEN
1348 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1350 struct IO_APIC_route_entry entry;
1351 unsigned long flags;
1353 memset(&entry,0,sizeof(entry));
1355 disable_8259A_irq(0);
1357 /* mask LVT0 */
1358 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1360 /*
1361 * We use logical delivery to get the timer IRQ
1362 * to the first CPU.
1363 */
1364 entry.dest_mode = INT_DEST_MODE;
1365 entry.mask = 0; /* unmask IRQ now */
1366 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1367 entry.delivery_mode = INT_DELIVERY_MODE;
1368 entry.polarity = 0;
1369 entry.trigger = 0;
1370 entry.vector = vector;
1372 /*
1373 * The timer IRQ doesn't have to know that behind the
1374 * scene we have a 8259A-master in AEOI mode ...
1375 */
1376 irq_desc[0].chip = &ioapic_edge_type;
1378 /*
1379 * Add it to the IO-APIC irq-routing table:
1380 */
1381 spin_lock_irqsave(&ioapic_lock, flags);
1382 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1383 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1384 spin_unlock_irqrestore(&ioapic_lock, flags);
1386 enable_8259A_irq(0);
1389 static inline void UNEXPECTED_IO_APIC(void)
1393 void __init print_IO_APIC(void)
1395 int apic, i;
1396 union IO_APIC_reg_00 reg_00;
1397 union IO_APIC_reg_01 reg_01;
1398 union IO_APIC_reg_02 reg_02;
1399 union IO_APIC_reg_03 reg_03;
1400 unsigned long flags;
1402 if (apic_verbosity == APIC_QUIET)
1403 return;
1405 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1406 for (i = 0; i < nr_ioapics; i++)
1407 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1408 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1410 /*
1411 * We are a bit conservative about what we expect. We have to
1412 * know about every hardware change ASAP.
1413 */
1414 printk(KERN_INFO "testing the IO APIC.......................\n");
1416 for (apic = 0; apic < nr_ioapics; apic++) {
1418 spin_lock_irqsave(&ioapic_lock, flags);
1419 reg_00.raw = io_apic_read(apic, 0);
1420 reg_01.raw = io_apic_read(apic, 1);
1421 if (reg_01.bits.version >= 0x10)
1422 reg_02.raw = io_apic_read(apic, 2);
1423 if (reg_01.bits.version >= 0x20)
1424 reg_03.raw = io_apic_read(apic, 3);
1425 spin_unlock_irqrestore(&ioapic_lock, flags);
1427 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1428 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1429 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1430 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1431 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1432 if (reg_00.bits.ID >= get_physical_broadcast())
1433 UNEXPECTED_IO_APIC();
1434 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1435 UNEXPECTED_IO_APIC();
1437 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1438 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1439 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1440 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1441 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1442 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1443 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1444 (reg_01.bits.entries != 0x2E) &&
1445 (reg_01.bits.entries != 0x3F)
1447 UNEXPECTED_IO_APIC();
1449 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1450 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1451 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1452 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1453 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1454 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1455 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1457 UNEXPECTED_IO_APIC();
1458 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1459 UNEXPECTED_IO_APIC();
1461 /*
1462 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1463 * but the value of reg_02 is read as the previous read register
1464 * value, so ignore it if reg_02 == reg_01.
1465 */
1466 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1467 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1468 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1469 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1470 UNEXPECTED_IO_APIC();
1473 /*
1474 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1475 * or reg_03, but the value of reg_0[23] is read as the previous read
1476 * register value, so ignore it if reg_03 == reg_0[12].
1477 */
1478 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1479 reg_03.raw != reg_01.raw) {
1480 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1481 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1482 if (reg_03.bits.__reserved_1)
1483 UNEXPECTED_IO_APIC();
1486 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1488 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1489 " Stat Dest Deli Vect: \n");
1491 for (i = 0; i <= reg_01.bits.entries; i++) {
1492 struct IO_APIC_route_entry entry;
1494 spin_lock_irqsave(&ioapic_lock, flags);
1495 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1496 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1497 spin_unlock_irqrestore(&ioapic_lock, flags);
1499 printk(KERN_DEBUG " %02x %03X %02X ",
1500 i,
1501 entry.dest.logical.logical_dest,
1502 entry.dest.physical.physical_dest
1503 );
1505 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1506 entry.mask,
1507 entry.trigger,
1508 entry.irr,
1509 entry.polarity,
1510 entry.delivery_status,
1511 entry.dest_mode,
1512 entry.delivery_mode,
1513 entry.vector
1514 );
1517 if (use_pci_vector())
1518 printk(KERN_INFO "Using vector-based indexing\n");
1519 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1520 for (i = 0; i < NR_IRQS; i++) {
1521 struct irq_pin_list *entry = irq_2_pin + i;
1522 if (entry->pin < 0)
1523 continue;
1524 if (use_pci_vector() && !platform_legacy_irq(i))
1525 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1526 else
1527 printk(KERN_DEBUG "IRQ%d ", i);
1528 for (;;) {
1529 printk("-> %d:%d", entry->apic, entry->pin);
1530 if (!entry->next)
1531 break;
1532 entry = irq_2_pin + entry->next;
1534 printk("\n");
1537 printk(KERN_INFO ".................................... done.\n");
1539 return;
1542 static void print_APIC_bitfield (int base)
1544 unsigned int v;
1545 int i, j;
1547 if (apic_verbosity == APIC_QUIET)
1548 return;
1550 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1551 for (i = 0; i < 8; i++) {
1552 v = apic_read(base + i*0x10);
1553 for (j = 0; j < 32; j++) {
1554 if (v & (1<<j))
1555 printk("1");
1556 else
1557 printk("0");
1559 printk("\n");
1563 void /*__init*/ print_local_APIC(void * dummy)
1565 unsigned int v, ver, maxlvt;
1567 if (apic_verbosity == APIC_QUIET)
1568 return;
1570 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1571 smp_processor_id(), hard_smp_processor_id());
1572 v = apic_read(APIC_ID);
1573 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1574 v = apic_read(APIC_LVR);
1575 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1576 ver = GET_APIC_VERSION(v);
1577 maxlvt = get_maxlvt();
1579 v = apic_read(APIC_TASKPRI);
1580 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1582 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1583 v = apic_read(APIC_ARBPRI);
1584 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1585 v & APIC_ARBPRI_MASK);
1586 v = apic_read(APIC_PROCPRI);
1587 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1590 v = apic_read(APIC_EOI);
1591 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1592 v = apic_read(APIC_RRR);
1593 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1594 v = apic_read(APIC_LDR);
1595 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1596 v = apic_read(APIC_DFR);
1597 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1598 v = apic_read(APIC_SPIV);
1599 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1601 printk(KERN_DEBUG "... APIC ISR field:\n");
1602 print_APIC_bitfield(APIC_ISR);
1603 printk(KERN_DEBUG "... APIC TMR field:\n");
1604 print_APIC_bitfield(APIC_TMR);
1605 printk(KERN_DEBUG "... APIC IRR field:\n");
1606 print_APIC_bitfield(APIC_IRR);
1608 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1609 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1610 apic_write(APIC_ESR, 0);
1611 v = apic_read(APIC_ESR);
1612 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1615 v = apic_read(APIC_ICR);
1616 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1617 v = apic_read(APIC_ICR2);
1618 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1620 v = apic_read(APIC_LVTT);
1621 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1623 if (maxlvt > 3) { /* PC is LVT#4. */
1624 v = apic_read(APIC_LVTPC);
1625 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1627 v = apic_read(APIC_LVT0);
1628 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1629 v = apic_read(APIC_LVT1);
1630 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1632 if (maxlvt > 2) { /* ERR is LVT#3. */
1633 v = apic_read(APIC_LVTERR);
1634 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1637 v = apic_read(APIC_TMICT);
1638 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1639 v = apic_read(APIC_TMCCT);
1640 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1641 v = apic_read(APIC_TDCR);
1642 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1643 printk("\n");
1646 void print_all_local_APICs (void)
1648 on_each_cpu(print_local_APIC, NULL, 1, 1);
1651 void /*__init*/ print_PIC(void)
1653 unsigned int v;
1654 unsigned long flags;
1656 if (apic_verbosity == APIC_QUIET)
1657 return;
1659 printk(KERN_DEBUG "\nprinting PIC contents\n");
1661 spin_lock_irqsave(&i8259A_lock, flags);
1663 v = inb(0xa1) << 8 | inb(0x21);
1664 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1666 v = inb(0xa0) << 8 | inb(0x20);
1667 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1669 outb(0x0b,0xa0);
1670 outb(0x0b,0x20);
1671 v = inb(0xa0) << 8 | inb(0x20);
1672 outb(0x0a,0xa0);
1673 outb(0x0a,0x20);
1675 spin_unlock_irqrestore(&i8259A_lock, flags);
1677 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1679 v = inb(0x4d1) << 8 | inb(0x4d0);
1680 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1682 #endif /* !CONFIG_XEN */
1684 static void __init enable_IO_APIC(void)
1686 union IO_APIC_reg_01 reg_01;
1687 int i8259_apic, i8259_pin;
1688 int i, apic;
1689 unsigned long flags;
1691 for (i = 0; i < PIN_MAP_SIZE; i++) {
1692 irq_2_pin[i].pin = -1;
1693 irq_2_pin[i].next = 0;
1695 if (!pirqs_enabled)
1696 for (i = 0; i < MAX_PIRQS; i++)
1697 pirq_entries[i] = -1;
1699 /*
1700 * The number of IO-APIC IRQ registers (== #pins):
1701 */
1702 for (apic = 0; apic < nr_ioapics; apic++) {
1703 spin_lock_irqsave(&ioapic_lock, flags);
1704 reg_01.raw = io_apic_read(apic, 1);
1705 spin_unlock_irqrestore(&ioapic_lock, flags);
1706 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1708 for(apic = 0; apic < nr_ioapics; apic++) {
1709 int pin;
1710 /* See if any of the pins is in ExtINT mode */
1711 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1712 struct IO_APIC_route_entry entry;
1713 spin_lock_irqsave(&ioapic_lock, flags);
1714 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1715 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1716 spin_unlock_irqrestore(&ioapic_lock, flags);
1719 /* If the interrupt line is enabled and in ExtInt mode
1720 * I have found the pin where the i8259 is connected.
1721 */
1722 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1723 ioapic_i8259.apic = apic;
1724 ioapic_i8259.pin = pin;
1725 goto found_i8259;
1729 found_i8259:
1730 /* Look to see what if the MP table has reported the ExtINT */
1731 /* If we could not find the appropriate pin by looking at the ioapic
1732 * the i8259 probably is not connected the ioapic but give the
1733 * mptable a chance anyway.
1734 */
1735 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1736 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1737 /* Trust the MP table if nothing is setup in the hardware */
1738 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1739 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1740 ioapic_i8259.pin = i8259_pin;
1741 ioapic_i8259.apic = i8259_apic;
1743 /* Complain if the MP table and the hardware disagree */
1744 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1745 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1747 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1750 /*
1751 * Do not trust the IO-APIC being empty at bootup
1752 */
1753 clear_IO_APIC();
1756 /*
1757 * Not an __init, needed by the reboot code
1758 */
1759 void disable_IO_APIC(void)
1761 /*
1762 * Clear the IO-APIC before rebooting:
1763 */
1764 clear_IO_APIC();
1766 #ifndef CONFIG_XEN
1767 /*
1768 * If the i8259 is routed through an IOAPIC
1769 * Put that IOAPIC in virtual wire mode
1770 * so legacy interrupts can be delivered.
1771 */
1772 if (ioapic_i8259.pin != -1) {
1773 struct IO_APIC_route_entry entry;
1774 unsigned long flags;
1776 memset(&entry, 0, sizeof(entry));
1777 entry.mask = 0; /* Enabled */
1778 entry.trigger = 0; /* Edge */
1779 entry.irr = 0;
1780 entry.polarity = 0; /* High */
1781 entry.delivery_status = 0;
1782 entry.dest_mode = 0; /* Physical */
1783 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1784 entry.vector = 0;
1785 entry.dest.physical.physical_dest =
1786 GET_APIC_ID(apic_read(APIC_ID));
1788 /*
1789 * Add it to the IO-APIC irq-routing table:
1790 */
1791 spin_lock_irqsave(&ioapic_lock, flags);
1792 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1793 *(((int *)&entry)+1));
1794 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1795 *(((int *)&entry)+0));
1796 spin_unlock_irqrestore(&ioapic_lock, flags);
1798 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1799 #endif
1802 /*
1803 * function to set the IO-APIC physical IDs based on the
1804 * values stored in the MPC table.
1806 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1807 */
1809 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1810 static void __init setup_ioapic_ids_from_mpc(void)
1812 union IO_APIC_reg_00 reg_00;
1813 physid_mask_t phys_id_present_map;
1814 int apic;
1815 int i;
1816 unsigned char old_id;
1817 unsigned long flags;
1819 /*
1820 * Don't check I/O APIC IDs for xAPIC systems. They have
1821 * no meaning without the serial APIC bus.
1822 */
1823 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1824 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1825 return;
1826 /*
1827 * This is broken; anything with a real cpu count has to
1828 * circumvent this idiocy regardless.
1829 */
1830 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1832 /*
1833 * Set the IOAPIC ID to the value stored in the MPC table.
1834 */
1835 for (apic = 0; apic < nr_ioapics; apic++) {
1837 /* Read the register 0 value */
1838 spin_lock_irqsave(&ioapic_lock, flags);
1839 reg_00.raw = io_apic_read(apic, 0);
1840 spin_unlock_irqrestore(&ioapic_lock, flags);
1842 old_id = mp_ioapics[apic].mpc_apicid;
1844 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1845 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1846 apic, mp_ioapics[apic].mpc_apicid);
1847 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1848 reg_00.bits.ID);
1849 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1852 /*
1853 * Sanity check, is the ID really free? Every APIC in a
1854 * system must have a unique ID or we get lots of nice
1855 * 'stuck on smp_invalidate_needed IPI wait' messages.
1856 */
1857 if (check_apicid_used(phys_id_present_map,
1858 mp_ioapics[apic].mpc_apicid)) {
1859 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1860 apic, mp_ioapics[apic].mpc_apicid);
1861 for (i = 0; i < get_physical_broadcast(); i++)
1862 if (!physid_isset(i, phys_id_present_map))
1863 break;
1864 if (i >= get_physical_broadcast())
1865 panic("Max APIC ID exceeded!\n");
1866 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1867 i);
1868 physid_set(i, phys_id_present_map);
1869 mp_ioapics[apic].mpc_apicid = i;
1870 } else {
1871 physid_mask_t tmp;
1872 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1873 apic_printk(APIC_VERBOSE, "Setting %d in the "
1874 "phys_id_present_map\n",
1875 mp_ioapics[apic].mpc_apicid);
1876 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1880 /*
1881 * We need to adjust the IRQ routing table
1882 * if the ID changed.
1883 */
1884 if (old_id != mp_ioapics[apic].mpc_apicid)
1885 for (i = 0; i < mp_irq_entries; i++)
1886 if (mp_irqs[i].mpc_dstapic == old_id)
1887 mp_irqs[i].mpc_dstapic
1888 = mp_ioapics[apic].mpc_apicid;
1890 /*
1891 * Read the right value from the MPC table and
1892 * write it into the ID register.
1893 */
1894 apic_printk(APIC_VERBOSE, KERN_INFO
1895 "...changing IO-APIC physical APIC ID to %d ...",
1896 mp_ioapics[apic].mpc_apicid);
1898 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1899 spin_lock_irqsave(&ioapic_lock, flags);
1900 io_apic_write(apic, 0, reg_00.raw);
1901 spin_unlock_irqrestore(&ioapic_lock, flags);
1903 /*
1904 * Sanity check
1905 */
1906 spin_lock_irqsave(&ioapic_lock, flags);
1907 reg_00.raw = io_apic_read(apic, 0);
1908 spin_unlock_irqrestore(&ioapic_lock, flags);
1909 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1910 printk("could not set ID!\n");
1911 else
1912 apic_printk(APIC_VERBOSE, " ok.\n");
1915 #else
1916 static void __init setup_ioapic_ids_from_mpc(void) { }
1917 #endif
1919 #ifndef CONFIG_XEN
1920 /*
1921 * There is a nasty bug in some older SMP boards, their mptable lies
1922 * about the timer IRQ. We do the following to work around the situation:
1924 * - timer IRQ defaults to IO-APIC IRQ
1925 * - if this function detects that timer IRQs are defunct, then we fall
1926 * back to ISA timer IRQs
1927 */
1928 static int __init timer_irq_works(void)
1930 unsigned long t1 = jiffies;
1932 local_irq_enable();
1933 /* Let ten ticks pass... */
1934 mdelay((10 * 1000) / HZ);
1936 /*
1937 * Expect a few ticks at least, to be sure some possible
1938 * glue logic does not lock up after one or two first
1939 * ticks in a non-ExtINT mode. Also the local APIC
1940 * might have cached one ExtINT interrupt. Finally, at
1941 * least one tick may be lost due to delays.
1942 */
1943 if (jiffies - t1 > 4)
1944 return 1;
1946 return 0;
1949 /*
1950 * In the SMP+IOAPIC case it might happen that there are an unspecified
1951 * number of pending IRQ events unhandled. These cases are very rare,
1952 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1953 * better to do it this way as thus we do not have to be aware of
1954 * 'pending' interrupts in the IRQ path, except at this point.
1955 */
1956 /*
1957 * Edge triggered needs to resend any interrupt
1958 * that was delayed but this is now handled in the device
1959 * independent code.
1960 */
1962 /*
1963 * Starting up a edge-triggered IO-APIC interrupt is
1964 * nasty - we need to make sure that we get the edge.
1965 * If it is already asserted for some reason, we need
1966 * return 1 to indicate that is was pending.
1968 * This is not complete - we should be able to fake
1969 * an edge even if it isn't on the 8259A...
1970 */
1971 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1973 int was_pending = 0;
1974 unsigned long flags;
1976 spin_lock_irqsave(&ioapic_lock, flags);
1977 if (irq < 16) {
1978 disable_8259A_irq(irq);
1979 if (i8259A_irq_pending(irq))
1980 was_pending = 1;
1982 __unmask_IO_APIC_irq(irq);
1983 spin_unlock_irqrestore(&ioapic_lock, flags);
1985 return was_pending;
1988 /*
1989 * Once we have recorded IRQ_PENDING already, we can mask the
1990 * interrupt for real. This prevents IRQ storms from unhandled
1991 * devices.
1992 */
1993 static void ack_edge_ioapic_irq(unsigned int irq)
1995 move_irq(irq);
1996 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1997 == (IRQ_PENDING | IRQ_DISABLED))
1998 mask_IO_APIC_irq(irq);
1999 ack_APIC_irq();
2002 /*
2003 * Level triggered interrupts can just be masked,
2004 * and shutting down and starting up the interrupt
2005 * is the same as enabling and disabling them -- except
2006 * with a startup need to return a "was pending" value.
2008 * Level triggered interrupts are special because we
2009 * do not touch any IO-APIC register while handling
2010 * them. We ack the APIC in the end-IRQ handler, not
2011 * in the start-IRQ-handler. Protection against reentrance
2012 * from the same interrupt is still provided, both by the
2013 * generic IRQ layer and by the fact that an unacked local
2014 * APIC does not accept IRQs.
2015 */
2016 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2018 unmask_IO_APIC_irq(irq);
2020 return 0; /* don't check for pending */
2023 static void end_level_ioapic_irq (unsigned int irq)
2025 unsigned long v;
2026 int i;
2028 move_irq(irq);
2029 /*
2030 * It appears there is an erratum which affects at least version 0x11
2031 * of I/O APIC (that's the 82093AA and cores integrated into various
2032 * chipsets). Under certain conditions a level-triggered interrupt is
2033 * erroneously delivered as edge-triggered one but the respective IRR
2034 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2035 * message but it will never arrive and further interrupts are blocked
2036 * from the source. The exact reason is so far unknown, but the
2037 * phenomenon was observed when two consecutive interrupt requests
2038 * from a given source get delivered to the same CPU and the source is
2039 * temporarily disabled in between.
2041 * A workaround is to simulate an EOI message manually. We achieve it
2042 * by setting the trigger mode to edge and then to level when the edge
2043 * trigger mode gets detected in the TMR of a local APIC for a
2044 * level-triggered interrupt. We mask the source for the time of the
2045 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2046 * The idea is from Manfred Spraul. --macro
2047 */
2048 i = IO_APIC_VECTOR(irq);
2050 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2052 ack_APIC_irq();
2054 if (!(v & (1 << (i & 0x1f)))) {
2055 atomic_inc(&irq_mis_count);
2056 spin_lock(&ioapic_lock);
2057 __mask_and_edge_IO_APIC_irq(irq);
2058 __unmask_and_level_IO_APIC_irq(irq);
2059 spin_unlock(&ioapic_lock);
2063 #ifdef CONFIG_PCI_MSI
2064 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2066 int irq = vector_to_irq(vector);
2068 return startup_edge_ioapic_irq(irq);
2071 static void ack_edge_ioapic_vector(unsigned int vector)
2073 int irq = vector_to_irq(vector);
2075 move_native_irq(vector);
2076 ack_edge_ioapic_irq(irq);
2079 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2081 int irq = vector_to_irq(vector);
2083 return startup_level_ioapic_irq (irq);
2086 static void end_level_ioapic_vector (unsigned int vector)
2088 int irq = vector_to_irq(vector);
2090 move_native_irq(vector);
2091 end_level_ioapic_irq(irq);
2094 static void mask_IO_APIC_vector (unsigned int vector)
2096 int irq = vector_to_irq(vector);
2098 mask_IO_APIC_irq(irq);
2101 static void unmask_IO_APIC_vector (unsigned int vector)
2103 int irq = vector_to_irq(vector);
2105 unmask_IO_APIC_irq(irq);
2108 #ifdef CONFIG_SMP
2109 static void set_ioapic_affinity_vector (unsigned int vector,
2110 cpumask_t cpu_mask)
2112 int irq = vector_to_irq(vector);
2114 set_native_irq_info(vector, cpu_mask);
2115 set_ioapic_affinity_irq(irq, cpu_mask);
2117 #endif
2118 #endif
2120 static int ioapic_retrigger(unsigned int irq)
2122 send_IPI_self(IO_APIC_VECTOR(irq));
2124 return 1;
2127 /*
2128 * Level and edge triggered IO-APIC interrupts need different handling,
2129 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2130 * handled with the level-triggered descriptor, but that one has slightly
2131 * more overhead. Level-triggered interrupts cannot be handled with the
2132 * edge-triggered handler, without risking IRQ storms and other ugly
2133 * races.
2134 */
2135 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2136 .typename = "IO-APIC-edge",
2137 .startup = startup_edge_ioapic,
2138 .shutdown = shutdown_edge_ioapic,
2139 .enable = enable_edge_ioapic,
2140 .disable = disable_edge_ioapic,
2141 .ack = ack_edge_ioapic,
2142 .end = end_edge_ioapic,
2143 #ifdef CONFIG_SMP
2144 .set_affinity = set_ioapic_affinity,
2145 #endif
2146 .retrigger = ioapic_retrigger,
2147 };
2149 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2150 .typename = "IO-APIC-level",
2151 .startup = startup_level_ioapic,
2152 .shutdown = shutdown_level_ioapic,
2153 .enable = enable_level_ioapic,
2154 .disable = disable_level_ioapic,
2155 .ack = mask_and_ack_level_ioapic,
2156 .end = end_level_ioapic,
2157 #ifdef CONFIG_SMP
2158 .set_affinity = set_ioapic_affinity,
2159 #endif
2160 .retrigger = ioapic_retrigger,
2161 };
2162 #endif /* !CONFIG_XEN */
2164 static inline void init_IO_APIC_traps(void)
2166 int irq;
2168 /*
2169 * NOTE! The local APIC isn't very good at handling
2170 * multiple interrupts at the same interrupt level.
2171 * As the interrupt level is determined by taking the
2172 * vector number and shifting that right by 4, we
2173 * want to spread these out a bit so that they don't
2174 * all fall in the same interrupt level.
2176 * Also, we've got to be careful not to trash gate
2177 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2178 */
2179 for (irq = 0; irq < NR_IRQS ; irq++) {
2180 int tmp = irq;
2181 if (use_pci_vector()) {
2182 if (!platform_legacy_irq(tmp))
2183 if ((tmp = vector_to_irq(tmp)) == -1)
2184 continue;
2186 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2187 /*
2188 * Hmm.. We don't have an entry for this,
2189 * so default to an old-fashioned 8259
2190 * interrupt if we can..
2191 */
2192 if (irq < 16)
2193 make_8259A_irq(irq);
2194 #ifndef CONFIG_XEN
2195 else
2196 /* Strange. Oh, well.. */
2197 irq_desc[irq].chip = &no_irq_type;
2198 #endif
2203 #ifndef CONFIG_XEN
2204 static void enable_lapic_irq (unsigned int irq)
2206 unsigned long v;
2208 v = apic_read(APIC_LVT0);
2209 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2212 static void disable_lapic_irq (unsigned int irq)
2214 unsigned long v;
2216 v = apic_read(APIC_LVT0);
2217 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2220 static void ack_lapic_irq (unsigned int irq)
2222 ack_APIC_irq();
2225 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2227 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2228 .typename = "local-APIC-edge",
2229 .startup = NULL, /* startup_irq() not used for IRQ0 */
2230 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2231 .enable = enable_lapic_irq,
2232 .disable = disable_lapic_irq,
2233 .ack = ack_lapic_irq,
2234 .end = end_lapic_irq
2235 };
2237 static void setup_nmi (void)
2239 /*
2240 * Dirty trick to enable the NMI watchdog ...
2241 * We put the 8259A master into AEOI mode and
2242 * unmask on all local APICs LVT0 as NMI.
2244 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2245 * is from Maciej W. Rozycki - so we do not have to EOI from
2246 * the NMI handler or the timer interrupt.
2247 */
2248 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2250 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2252 apic_printk(APIC_VERBOSE, " done.\n");
2255 /*
2256 * This looks a bit hackish but it's about the only one way of sending
2257 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2258 * not support the ExtINT mode, unfortunately. We need to send these
2259 * cycles as some i82489DX-based boards have glue logic that keeps the
2260 * 8259A interrupt line asserted until INTA. --macro
2261 */
2262 static inline void unlock_ExtINT_logic(void)
2264 int apic, pin, i;
2265 struct IO_APIC_route_entry entry0, entry1;
2266 unsigned char save_control, save_freq_select;
2267 unsigned long flags;
2269 pin = find_isa_irq_pin(8, mp_INT);
2270 apic = find_isa_irq_apic(8, mp_INT);
2271 if (pin == -1)
2272 return;
2274 spin_lock_irqsave(&ioapic_lock, flags);
2275 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2276 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2277 spin_unlock_irqrestore(&ioapic_lock, flags);
2278 clear_IO_APIC_pin(apic, pin);
2280 memset(&entry1, 0, sizeof(entry1));
2282 entry1.dest_mode = 0; /* physical delivery */
2283 entry1.mask = 0; /* unmask IRQ now */
2284 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2285 entry1.delivery_mode = dest_ExtINT;
2286 entry1.polarity = entry0.polarity;
2287 entry1.trigger = 0;
2288 entry1.vector = 0;
2290 spin_lock_irqsave(&ioapic_lock, flags);
2291 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2292 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2293 spin_unlock_irqrestore(&ioapic_lock, flags);
2295 save_control = CMOS_READ(RTC_CONTROL);
2296 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2297 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2298 RTC_FREQ_SELECT);
2299 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2301 i = 100;
2302 while (i-- > 0) {
2303 mdelay(10);
2304 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2305 i -= 10;
2308 CMOS_WRITE(save_control, RTC_CONTROL);
2309 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2310 clear_IO_APIC_pin(apic, pin);
2312 spin_lock_irqsave(&ioapic_lock, flags);
2313 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2314 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2315 spin_unlock_irqrestore(&ioapic_lock, flags);
2318 int timer_uses_ioapic_pin_0;
2320 /*
2321 * This code may look a bit paranoid, but it's supposed to cooperate with
2322 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2323 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2324 * fanatically on his truly buggy board.
2325 */
2326 static inline void check_timer(void)
2328 int apic1, pin1, apic2, pin2;
2329 int vector;
2331 /*
2332 * get/set the timer IRQ vector:
2333 */
2334 disable_8259A_irq(0);
2335 vector = assign_irq_vector(0);
2336 set_intr_gate(vector, interrupt[0]);
2338 /*
2339 * Subtle, code in do_timer_interrupt() expects an AEOI
2340 * mode for the 8259A whenever interrupts are routed
2341 * through I/O APICs. Also IRQ0 has to be enabled in
2342 * the 8259A which implies the virtual wire has to be
2343 * disabled in the local APIC.
2344 */
2345 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2346 init_8259A(1);
2347 timer_ack = 1;
2348 if (timer_over_8254 > 0)
2349 enable_8259A_irq(0);
2351 pin1 = find_isa_irq_pin(0, mp_INT);
2352 apic1 = find_isa_irq_apic(0, mp_INT);
2353 pin2 = ioapic_i8259.pin;
2354 apic2 = ioapic_i8259.apic;
2356 if (pin1 == 0)
2357 timer_uses_ioapic_pin_0 = 1;
2359 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2360 vector, apic1, pin1, apic2, pin2);
2362 if (pin1 != -1) {
2363 /*
2364 * Ok, does IRQ0 through the IOAPIC work?
2365 */
2366 unmask_IO_APIC_irq(0);
2367 if (timer_irq_works()) {
2368 if (nmi_watchdog == NMI_IO_APIC) {
2369 disable_8259A_irq(0);
2370 setup_nmi();
2371 enable_8259A_irq(0);
2373 if (disable_timer_pin_1 > 0)
2374 clear_IO_APIC_pin(0, pin1);
2375 return;
2377 clear_IO_APIC_pin(apic1, pin1);
2378 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2379 "IO-APIC\n");
2382 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2383 if (pin2 != -1) {
2384 printk("\n..... (found pin %d) ...", pin2);
2385 /*
2386 * legacy devices should be connected to IO APIC #0
2387 */
2388 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2389 if (timer_irq_works()) {
2390 printk("works.\n");
2391 if (pin1 != -1)
2392 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2393 else
2394 add_pin_to_irq(0, apic2, pin2);
2395 if (nmi_watchdog == NMI_IO_APIC) {
2396 setup_nmi();
2398 return;
2400 /*
2401 * Cleanup, just in case ...
2402 */
2403 clear_IO_APIC_pin(apic2, pin2);
2405 printk(" failed.\n");
2407 if (nmi_watchdog == NMI_IO_APIC) {
2408 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2409 nmi_watchdog = 0;
2412 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2414 disable_8259A_irq(0);
2415 irq_desc[0].chip = &lapic_irq_type;
2416 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2417 enable_8259A_irq(0);
2419 if (timer_irq_works()) {
2420 printk(" works.\n");
2421 return;
2423 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2424 printk(" failed.\n");
2426 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2428 timer_ack = 0;
2429 init_8259A(0);
2430 make_8259A_irq(0);
2431 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2433 unlock_ExtINT_logic();
2435 if (timer_irq_works()) {
2436 printk(" works.\n");
2437 return;
2439 printk(" failed :(.\n");
2440 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2441 "report. Then try booting with the 'noapic' option");
2443 #else
2444 int timer_uses_ioapic_pin_0 = 0;
2445 #define check_timer() ((void)0)
2446 #endif
2448 /*
2450 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2451 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2452 * Linux doesn't really care, as it's not actually used
2453 * for any interrupt handling anyway.
2454 */
2455 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2457 void __init setup_IO_APIC(void)
2459 enable_IO_APIC();
2461 if (acpi_ioapic)
2462 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2463 else
2464 io_apic_irqs = ~PIC_IRQS;
2466 printk("ENABLING IO-APIC IRQs\n");
2468 /*
2469 * Set up IO-APIC IRQ routing.
2470 */
2471 if (!acpi_ioapic)
2472 setup_ioapic_ids_from_mpc();
2473 #ifndef CONFIG_XEN
2474 sync_Arb_IDs();
2475 #endif
2476 setup_IO_APIC_irqs();
2477 init_IO_APIC_traps();
2478 check_timer();
2479 if (!acpi_ioapic)
2480 print_IO_APIC();
2483 static int __init setup_disable_8254_timer(char *s)
2485 timer_over_8254 = -1;
2486 return 1;
2488 static int __init setup_enable_8254_timer(char *s)
2490 timer_over_8254 = 2;
2491 return 1;
2494 __setup("disable_8254_timer", setup_disable_8254_timer);
2495 __setup("enable_8254_timer", setup_enable_8254_timer);
2497 /*
2498 * Called after all the initialization is done. If we didnt find any
2499 * APIC bugs then we can allow the modify fast path
2500 */
2502 static int __init io_apic_bug_finalize(void)
2504 if(sis_apic_bug == -1)
2505 sis_apic_bug = 0;
2506 if (is_initial_xendomain()) {
2507 struct xen_platform_op op = { .cmd = XENPF_platform_quirk };
2508 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2509 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2510 VOID(HYPERVISOR_platform_op(&op));
2512 return 0;
2515 late_initcall(io_apic_bug_finalize);
2517 struct sysfs_ioapic_data {
2518 struct sys_device dev;
2519 struct IO_APIC_route_entry entry[0];
2520 };
2521 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2523 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2525 struct IO_APIC_route_entry *entry;
2526 struct sysfs_ioapic_data *data;
2527 unsigned long flags;
2528 int i;
2530 data = container_of(dev, struct sysfs_ioapic_data, dev);
2531 entry = data->entry;
2532 spin_lock_irqsave(&ioapic_lock, flags);
2533 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2534 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2535 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2537 spin_unlock_irqrestore(&ioapic_lock, flags);
2539 return 0;
2542 static int ioapic_resume(struct sys_device *dev)
2544 struct IO_APIC_route_entry *entry;
2545 struct sysfs_ioapic_data *data;
2546 unsigned long flags;
2547 union IO_APIC_reg_00 reg_00;
2548 int i;
2550 data = container_of(dev, struct sysfs_ioapic_data, dev);
2551 entry = data->entry;
2553 spin_lock_irqsave(&ioapic_lock, flags);
2554 reg_00.raw = io_apic_read(dev->id, 0);
2555 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2556 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2557 io_apic_write(dev->id, 0, reg_00.raw);
2559 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2560 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2561 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2563 spin_unlock_irqrestore(&ioapic_lock, flags);
2565 return 0;
2568 static struct sysdev_class ioapic_sysdev_class = {
2569 set_kset_name("ioapic"),
2570 .suspend = ioapic_suspend,
2571 .resume = ioapic_resume,
2572 };
2574 static int __init ioapic_init_sysfs(void)
2576 struct sys_device * dev;
2577 int i, size, error = 0;
2579 error = sysdev_class_register(&ioapic_sysdev_class);
2580 if (error)
2581 return error;
2583 for (i = 0; i < nr_ioapics; i++ ) {
2584 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2585 * sizeof(struct IO_APIC_route_entry);
2586 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2587 if (!mp_ioapic_data[i]) {
2588 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2589 continue;
2591 memset(mp_ioapic_data[i], 0, size);
2592 dev = &mp_ioapic_data[i]->dev;
2593 dev->id = i;
2594 dev->cls = &ioapic_sysdev_class;
2595 error = sysdev_register(dev);
2596 if (error) {
2597 kfree(mp_ioapic_data[i]);
2598 mp_ioapic_data[i] = NULL;
2599 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2600 continue;
2604 return 0;
2607 device_initcall(ioapic_init_sysfs);
2609 /* --------------------------------------------------------------------------
2610 ACPI-based IOAPIC Configuration
2611 -------------------------------------------------------------------------- */
2613 #ifdef CONFIG_ACPI
2615 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2617 #ifndef CONFIG_XEN
2618 union IO_APIC_reg_00 reg_00;
2619 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2620 physid_mask_t tmp;
2621 unsigned long flags;
2622 int i = 0;
2624 /*
2625 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2626 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2627 * supports up to 16 on one shared APIC bus.
2629 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2630 * advantage of new APIC bus architecture.
2631 */
2633 if (physids_empty(apic_id_map))
2634 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2636 spin_lock_irqsave(&ioapic_lock, flags);
2637 reg_00.raw = io_apic_read(ioapic, 0);
2638 spin_unlock_irqrestore(&ioapic_lock, flags);
2640 if (apic_id >= get_physical_broadcast()) {
2641 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2642 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2643 apic_id = reg_00.bits.ID;
2646 /*
2647 * Every APIC in a system must have a unique ID or we get lots of nice
2648 * 'stuck on smp_invalidate_needed IPI wait' messages.
2649 */
2650 if (check_apicid_used(apic_id_map, apic_id)) {
2652 for (i = 0; i < get_physical_broadcast(); i++) {
2653 if (!check_apicid_used(apic_id_map, i))
2654 break;
2657 if (i == get_physical_broadcast())
2658 panic("Max apic_id exceeded!\n");
2660 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2661 "trying %d\n", ioapic, apic_id, i);
2663 apic_id = i;
2666 tmp = apicid_to_cpu_present(apic_id);
2667 physids_or(apic_id_map, apic_id_map, tmp);
2669 if (reg_00.bits.ID != apic_id) {
2670 reg_00.bits.ID = apic_id;
2672 spin_lock_irqsave(&ioapic_lock, flags);
2673 io_apic_write(ioapic, 0, reg_00.raw);
2674 reg_00.raw = io_apic_read(ioapic, 0);
2675 spin_unlock_irqrestore(&ioapic_lock, flags);
2677 /* Sanity check */
2678 if (reg_00.bits.ID != apic_id) {
2679 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2680 return -1;
2684 apic_printk(APIC_VERBOSE, KERN_INFO
2685 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2686 #endif /* !CONFIG_XEN */
2688 return apic_id;
2692 int __init io_apic_get_version (int ioapic)
2694 union IO_APIC_reg_01 reg_01;
2695 unsigned long flags;
2697 spin_lock_irqsave(&ioapic_lock, flags);
2698 reg_01.raw = io_apic_read(ioapic, 1);
2699 spin_unlock_irqrestore(&ioapic_lock, flags);
2701 return reg_01.bits.version;
2705 int __init io_apic_get_redir_entries (int ioapic)
2707 union IO_APIC_reg_01 reg_01;
2708 unsigned long flags;
2710 spin_lock_irqsave(&ioapic_lock, flags);
2711 reg_01.raw = io_apic_read(ioapic, 1);
2712 spin_unlock_irqrestore(&ioapic_lock, flags);
2714 return reg_01.bits.entries;
2718 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2720 struct IO_APIC_route_entry entry;
2721 unsigned long flags;
2723 if (!IO_APIC_IRQ(irq)) {
2724 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2725 ioapic);
2726 return -EINVAL;
2729 /*
2730 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2731 * Note that we mask (disable) IRQs now -- these get enabled when the
2732 * corresponding device driver registers for this IRQ.
2733 */
2735 memset(&entry,0,sizeof(entry));
2737 entry.delivery_mode = INT_DELIVERY_MODE;
2738 entry.dest_mode = INT_DEST_MODE;
2739 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2740 entry.trigger = edge_level;
2741 entry.polarity = active_high_low;
2742 entry.mask = 1;
2744 /*
2745 * IRQs < 16 are already in the irq_2_pin[] map
2746 */
2747 if (irq >= 16)
2748 add_pin_to_irq(irq, ioapic, pin);
2750 entry.vector = assign_irq_vector(irq);
2752 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2753 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2754 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2755 edge_level, active_high_low);
2757 ioapic_register_intr(irq, entry.vector, edge_level);
2759 if (!ioapic && (irq < 16))
2760 disable_8259A_irq(irq);
2762 spin_lock_irqsave(&ioapic_lock, flags);
2763 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2764 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2765 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2766 spin_unlock_irqrestore(&ioapic_lock, flags);
2768 return 0;
2771 #endif /* CONFIG_ACPI */