ia64/linux-2.6.18-xen.hg

view drivers/pci/msi-xen.c @ 790:77e3b255381e

linux: remove xen specific member from pci_dev

Move msi related variable irq_old out of struct pci_dev. This is
logically more consistent and has the additional benefit that xen
kernel and vanilla kernel now have the same pci_dev layout

Signed-off-by: Qing He <qing.he@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Feb 04 12:25:09 2009 +0000 (2009-02-04)
parents 63a878f8851b
children 6a0fee3b8b7d
line source
1 /*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
9 #include <linux/mm.h>
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/smp_lock.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
18 #include <xen/evtchn.h>
20 #include <asm/errno.h>
21 #include <asm/io.h>
22 #include <asm/smp.h>
24 #include "pci.h"
25 #include "msi.h"
27 static int pci_msi_enable = 1;
29 static struct msi_ops *msi_ops;
31 int msi_register(struct msi_ops *ops)
32 {
33 msi_ops = ops;
34 return 0;
35 }
37 static LIST_HEAD(msi_dev_head);
38 DEFINE_SPINLOCK(msi_dev_lock);
40 struct msi_dev_list {
41 struct pci_dev *dev;
42 struct list_head list;
43 spinlock_t pirq_list_lock;
44 struct list_head pirq_list_head;
45 /* Used for saving/restoring MSI-X tables */
46 void __iomem *mask_base;
47 /* Store default pre-assigned irq */
48 unsigned int default_irq;
49 };
51 struct msi_pirq_entry {
52 struct list_head list;
53 int pirq;
54 int entry_nr;
55 #ifdef CONFIG_PM
56 /* PM save area for MSIX address/data */
57 u32 address_hi_save;
58 u32 address_lo_save;
59 u32 data_save;
60 #endif
61 };
63 static struct msi_dev_list *get_msi_dev_pirq_list(struct pci_dev *dev)
64 {
65 struct msi_dev_list *msi_dev_list, *ret = NULL;
66 unsigned long flags;
68 spin_lock_irqsave(&msi_dev_lock, flags);
70 list_for_each_entry(msi_dev_list, &msi_dev_head, list)
71 if ( msi_dev_list->dev == dev )
72 ret = msi_dev_list;
74 if ( ret ) {
75 spin_unlock_irqrestore(&msi_dev_lock, flags);
76 return ret;
77 }
79 /* Has not allocate msi_dev until now. */
80 ret = kzalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
82 /* Failed to allocate msi_dev structure */
83 if ( !ret ) {
84 spin_unlock_irqrestore(&msi_dev_lock, flags);
85 return NULL;
86 }
88 ret->dev = dev;
89 spin_lock_init(&ret->pirq_list_lock);
90 INIT_LIST_HEAD(&ret->pirq_list_head);
91 list_add_tail(&ret->list, &msi_dev_head);
92 spin_unlock_irqrestore(&msi_dev_lock, flags);
93 return ret;
94 }
96 static int attach_pirq_entry(int pirq, int entry_nr,
97 struct msi_dev_list *msi_dev_entry)
98 {
99 struct msi_pirq_entry *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
100 unsigned long flags;
102 if (!entry)
103 return -ENOMEM;
104 entry->pirq = pirq;
105 entry->entry_nr = entry_nr;
106 spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
107 list_add_tail(&entry->list, &msi_dev_entry->pirq_list_head);
108 spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
109 return 0;
110 }
112 static void detach_pirq_entry(int entry_nr,
113 struct msi_dev_list *msi_dev_entry)
114 {
115 unsigned long flags;
116 struct msi_pirq_entry *pirq_entry;
118 list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
119 if (pirq_entry->entry_nr == entry_nr) {
120 spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
121 list_del(&pirq_entry->list);
122 spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
123 kfree(pirq_entry);
124 return;
125 }
126 }
127 }
129 /*
130 * pciback will provide device's owner
131 */
132 static int (*get_owner)(struct pci_dev *dev);
134 int register_msi_get_owner(int (*func)(struct pci_dev *dev))
135 {
136 if (get_owner) {
137 printk(KERN_WARNING "register msi_get_owner again\n");
138 return -EEXIST;
139 }
140 get_owner = func;
141 return 0;
142 }
144 int unregister_msi_get_owner(int (*func)(struct pci_dev *dev))
145 {
146 if (get_owner != func)
147 return -EINVAL;
148 get_owner = NULL;
149 return 0;
150 }
152 static int msi_get_dev_owner(struct pci_dev *dev)
153 {
154 int owner;
156 BUG_ON(!is_initial_xendomain());
157 if (get_owner && (owner = get_owner(dev)) >= 0) {
158 printk(KERN_INFO "get owner for dev %x get %x \n",
159 dev->devfn, owner);
160 return owner;
161 }
163 return DOMID_SELF;
164 }
166 static int msi_unmap_pirq(struct pci_dev *dev, int pirq)
167 {
168 struct physdev_unmap_pirq unmap;
169 int rc;
171 unmap.domid = msi_get_dev_owner(dev);
172 /* See comments in msi_map_pirq_to_vector, input parameter pirq
173 * mean irq number only if the device belongs to dom0 itself.
174 */
175 unmap.pirq = (unmap.domid != DOMID_SELF)
176 ? pirq : evtchn_get_xen_pirq(pirq);
178 if ((rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap)))
179 printk(KERN_WARNING "unmap irq %x failed\n", pirq);
181 if (rc < 0)
182 return rc;
184 if (unmap.domid == DOMID_SELF)
185 evtchn_map_pirq(pirq, 0);
187 return 0;
188 }
190 static u64 find_table_base(struct pci_dev *dev, int pos)
191 {
192 u8 bar;
193 u32 reg;
194 unsigned long flags;
196 pci_read_config_dword(dev, msix_table_offset_reg(pos), &reg);
197 bar = reg & PCI_MSIX_FLAGS_BIRMASK;
199 flags = pci_resource_flags(dev, bar);
200 if (flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET | IORESOURCE_BUSY))
201 return 0;
203 return pci_resource_start(dev, bar);
204 }
206 /*
207 * Protected by msi_lock
208 */
209 static int msi_map_pirq_to_vector(struct pci_dev *dev, int pirq,
210 int entry_nr, u64 table_base)
211 {
212 struct physdev_map_pirq map_irq;
213 int rc;
214 domid_t domid = DOMID_SELF;
216 domid = msi_get_dev_owner(dev);
218 map_irq.domid = domid;
219 map_irq.type = MAP_PIRQ_TYPE_MSI;
220 map_irq.index = -1;
221 map_irq.pirq = pirq < 0 ? -1 : evtchn_get_xen_pirq(pirq);
222 map_irq.bus = dev->bus->number;
223 map_irq.devfn = dev->devfn;
224 map_irq.entry_nr = entry_nr;
225 map_irq.table_base = table_base;
227 if ((rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq)))
228 printk(KERN_WARNING "map irq failed\n");
230 if (rc < 0)
231 return rc;
232 /* This happens when MSI support is not enabled in Xen. */
233 if (rc == 0 && map_irq.pirq < 0)
234 return -ENOSYS;
236 BUG_ON(map_irq.pirq <= 0);
238 /* If mapping of this particular MSI is on behalf of another domain,
239 * we do not need to get an irq in dom0. This also implies:
240 * dev->irq in dom0 will be 'Xen pirq' if this device belongs to
241 * to another domain, and will be 'Linux irq' if it belongs to dom0.
242 */
243 return ((domid != DOMID_SELF) ?
244 map_irq.pirq : evtchn_map_pirq(pirq, map_irq.pirq));
245 }
247 static int msi_map_vector(struct pci_dev *dev, int entry_nr, u64 table_base)
248 {
249 return msi_map_pirq_to_vector(dev, -1, entry_nr, table_base);
250 }
252 static int msi_init(void)
253 {
254 static int status = 0;
256 if (pci_msi_quirk) {
257 pci_msi_enable = 0;
258 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
259 status = -EINVAL;
260 }
262 return status;
263 }
265 void pci_scan_msi_device(struct pci_dev *dev) { }
267 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
268 {
269 u16 control;
271 pci_read_config_word(dev, msi_control_reg(pos), &control);
272 if (type == PCI_CAP_ID_MSI) {
273 /* Set enabled bits to single MSI & enable MSI_enable bit */
274 msi_disable(control);
275 pci_write_config_word(dev, msi_control_reg(pos), control);
276 dev->msi_enabled = 0;
277 } else {
278 msix_disable(control);
279 pci_write_config_word(dev, msi_control_reg(pos), control);
280 dev->msix_enabled = 0;
281 }
282 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
283 /* PCI Express Endpoint device detected */
284 pci_intx(dev, 1); /* enable intx */
285 }
286 }
288 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
289 {
290 u16 control;
292 pci_read_config_word(dev, msi_control_reg(pos), &control);
293 if (type == PCI_CAP_ID_MSI) {
294 /* Set enabled bits to single MSI & enable MSI_enable bit */
295 msi_enable(control, 1);
296 pci_write_config_word(dev, msi_control_reg(pos), control);
297 dev->msi_enabled = 1;
298 } else {
299 msix_enable(control);
300 pci_write_config_word(dev, msi_control_reg(pos), control);
301 dev->msix_enabled = 1;
302 }
303 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
304 /* PCI Express Endpoint device detected */
305 pci_intx(dev, 0); /* disable intx */
306 }
307 }
309 #ifdef CONFIG_PM
310 int pci_save_msi_state(struct pci_dev *dev)
311 {
312 int pos, i = 0;
313 u16 control;
314 struct pci_cap_saved_state *save_state;
315 u32 *cap;
317 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
318 if (pos <= 0 || dev->no_msi)
319 return 0;
321 pci_read_config_word(dev, msi_control_reg(pos), &control);
322 if (!(control & PCI_MSI_FLAGS_ENABLE))
323 return 0;
325 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
326 GFP_KERNEL);
327 if (!save_state) {
328 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
329 return -ENOMEM;
330 }
331 cap = &save_state->data[0];
333 pci_read_config_dword(dev, pos, &cap[i++]);
334 control = cap[0] >> 16;
335 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
336 if (control & PCI_MSI_FLAGS_64BIT) {
337 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
338 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
339 } else
340 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
341 if (control & PCI_MSI_FLAGS_MASKBIT)
342 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
343 save_state->cap_nr = PCI_CAP_ID_MSI;
344 pci_add_saved_cap(dev, save_state);
345 return 0;
346 }
348 void pci_restore_msi_state(struct pci_dev *dev)
349 {
350 int i = 0, pos;
351 u16 control;
352 struct pci_cap_saved_state *save_state;
353 u32 *cap;
355 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
356 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
357 if (!save_state || pos <= 0)
358 return;
359 cap = &save_state->data[0];
361 control = cap[i++] >> 16;
362 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
363 if (control & PCI_MSI_FLAGS_64BIT) {
364 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
365 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
366 } else
367 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
368 if (control & PCI_MSI_FLAGS_MASKBIT)
369 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
370 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
371 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
372 pci_remove_saved_cap(save_state);
373 kfree(save_state);
374 }
376 int pci_save_msix_state(struct pci_dev *dev)
377 {
378 int pos;
379 u16 control;
380 struct pci_cap_saved_state *save_state;
381 unsigned long flags;
382 struct msi_dev_list *msi_dev_entry;
383 struct msi_pirq_entry *pirq_entry;
384 void __iomem *base;
386 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
387 if (pos <= 0 || dev->no_msi)
388 return 0;
390 /* save the capability */
391 pci_read_config_word(dev, msi_control_reg(pos), &control);
392 if (!(control & PCI_MSIX_FLAGS_ENABLE))
393 return 0;
395 msi_dev_entry = get_msi_dev_pirq_list(dev);
396 /* If we failed to map the MSI-X table at pci_enable_msix,
397 * We could not support saving them here.
398 */
399 if (!(base = msi_dev_entry->mask_base))
400 return -ENOMEM;
402 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
403 GFP_KERNEL);
404 if (!save_state) {
405 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
406 return -ENOMEM;
407 }
408 *((u16 *)&save_state->data[0]) = control;
410 spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
411 list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
412 int j;
414 /* save the table */
415 j = pirq_entry->entry_nr;
416 pirq_entry->address_lo_save =
417 readl(base + j * PCI_MSIX_ENTRY_SIZE +
418 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
419 pirq_entry->address_hi_save =
420 readl(base + j * PCI_MSIX_ENTRY_SIZE +
421 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
422 pirq_entry->data_save =
423 readl(base + j * PCI_MSIX_ENTRY_SIZE +
424 PCI_MSIX_ENTRY_DATA_OFFSET);
425 }
426 spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
428 save_state->cap_nr = PCI_CAP_ID_MSIX;
429 pci_add_saved_cap(dev, save_state);
430 return 0;
431 }
433 void pci_restore_msix_state(struct pci_dev *dev)
434 {
435 u16 save;
436 int pos, j;
437 void __iomem *base;
438 struct pci_cap_saved_state *save_state;
439 unsigned long flags;
440 struct msi_dev_list *msi_dev_entry;
441 struct msi_pirq_entry *pirq_entry;
443 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
444 if (!save_state)
445 return;
447 save = *((u16 *)&save_state->data[0]);
448 pci_remove_saved_cap(save_state);
449 kfree(save_state);
451 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
452 if (pos <= 0)
453 return;
455 msi_dev_entry = get_msi_dev_pirq_list(dev);
456 base = msi_dev_entry->mask_base;
458 spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
459 list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
460 /* route the table */
461 j = pirq_entry->entry_nr;
462 writel(pirq_entry->address_lo_save,
463 base + j * PCI_MSIX_ENTRY_SIZE +
464 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
465 writel(pirq_entry->address_hi_save,
466 base + j * PCI_MSIX_ENTRY_SIZE +
467 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
468 writel(pirq_entry->data_save,
469 base + j * PCI_MSIX_ENTRY_SIZE +
470 PCI_MSIX_ENTRY_DATA_OFFSET);
471 }
472 spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
474 pci_write_config_word(dev, msi_control_reg(pos), save);
475 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
476 }
477 #endif
479 /**
480 * msi_capability_init - configure device's MSI capability structure
481 * @dev: pointer to the pci_dev data structure of MSI device function
482 *
483 * Setup the MSI capability structure of device function with a single
484 * MSI vector, regardless of device function is capable of handling
485 * multiple messages. A return of zero indicates the successful setup
486 * of an entry zero with the new MSI vector or non-zero for otherwise.
487 **/
488 static int msi_capability_init(struct pci_dev *dev)
489 {
490 int pos, pirq;
491 u16 control;
493 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
494 pci_read_config_word(dev, msi_control_reg(pos), &control);
496 pirq = msi_map_vector(dev, 0, 0);
497 if (pirq < 0)
498 return -EBUSY;
500 dev->irq = pirq;
501 /* Set MSI enabled bits */
502 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
503 dev->msi_enabled = 1;
505 return 0;
506 }
508 /**
509 * msix_capability_init - configure device's MSI-X capability
510 * @dev: pointer to the pci_dev data structure of MSI-X device function
511 * @entries: pointer to an array of struct msix_entry entries
512 * @nvec: number of @entries
513 *
514 * Setup the MSI-X capability structure of device function with a
515 * single MSI-X vector. A return of zero indicates the successful setup of
516 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
517 **/
518 static int msix_capability_init(struct pci_dev *dev,
519 struct msix_entry *entries, int nvec)
520 {
521 u64 table_base;
522 u16 control;
523 int pirq, i, j, mapped, pos, nr_entries;
524 struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
525 struct msi_pirq_entry *pirq_entry;
527 if (!msi_dev_entry)
528 return -ENOMEM;
530 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
531 table_base = find_table_base(dev, pos);
532 if (!table_base)
533 return -ENODEV;
535 pci_read_config_word(dev, msi_control_reg(pos), &control);
536 nr_entries = multi_msix_capable(control);
537 if (!msi_dev_entry->mask_base)
538 msi_dev_entry->mask_base =
539 ioremap_nocache(table_base, nr_entries * PCI_MSIX_ENTRY_SIZE);
541 /* MSI-X Table Initialization */
542 for (i = 0; i < nvec; i++) {
543 mapped = 0;
544 list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
545 if (pirq_entry->entry_nr == entries[i].entry) {
546 printk(KERN_WARNING "msix entry %d for dev %02x:%02x:%01x are \
547 not freed before acquire again.\n", entries[i].entry,
548 dev->bus->number, PCI_SLOT(dev->devfn),
549 PCI_FUNC(dev->devfn));
550 (entries + i)->vector = pirq_entry->pirq;
551 mapped = 1;
552 break;
553 }
554 }
555 if (mapped)
556 continue;
557 pirq = msi_map_vector(dev, entries[i].entry, table_base);
558 if (pirq < 0)
559 break;
560 attach_pirq_entry(pirq, entries[i].entry, msi_dev_entry);
561 (entries + i)->vector = pirq;
562 }
564 if (i != nvec) {
565 for (j = --i; j >= 0; j--) {
566 msi_unmap_pirq(dev, entries[j].vector);
567 detach_pirq_entry(entries[j].entry, msi_dev_entry);
568 entries[j].vector = 0;
569 }
570 return -EBUSY;
571 }
573 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
574 dev->msix_enabled = 1;
576 return 0;
577 }
579 /**
580 * pci_enable_msi - configure device's MSI capability structure
581 * @dev: pointer to the pci_dev data structure of MSI device function
582 *
583 * Setup the MSI capability structure of device function with
584 * a single MSI vector upon its software driver call to request for
585 * MSI mode enabled on its hardware device function. A return of zero
586 * indicates the successful setup of an entry zero with the new MSI
587 * vector or non-zero for otherwise.
588 **/
589 extern int pci_frontend_enable_msi(struct pci_dev *dev);
590 int pci_enable_msi(struct pci_dev* dev)
591 {
592 struct pci_bus *bus;
593 int pos, temp, status = -EINVAL;
594 struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
596 if (!pci_msi_enable || !dev)
597 return status;
599 if (dev->no_msi)
600 return status;
602 for (bus = dev->bus; bus; bus = bus->parent)
603 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
604 return -EINVAL;
606 status = msi_init();
607 if (status < 0)
608 return status;
610 #ifdef CONFIG_XEN_PCIDEV_FRONTEND
611 if (!is_initial_xendomain())
612 {
613 int ret;
615 temp = dev->irq;
616 ret = pci_frontend_enable_msi(dev);
617 if (ret)
618 return ret;
620 dev->irq = evtchn_map_pirq(-1, dev->irq);
621 msi_dev_entry->default_irq = temp;
623 return ret;
624 }
625 #endif
627 temp = dev->irq;
629 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
630 if (!pos)
631 return -EINVAL;
633 /* Check whether driver already requested for MSI-X vectors */
634 if (dev->msix_enabled) {
635 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
636 "Device already has MSI-X vectors assigned\n",
637 pci_name(dev));
638 dev->irq = temp;
639 return -EINVAL;
640 }
642 status = msi_capability_init(dev);
643 if ( !status )
644 msi_dev_entry->default_irq = temp;
645 else
646 dev->irq = temp;
648 return status;
649 }
651 extern void pci_frontend_disable_msi(struct pci_dev* dev);
652 void pci_disable_msi(struct pci_dev* dev)
653 {
654 int pos;
655 int pirq;
656 struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
658 if (!pci_msi_enable)
659 return;
660 if (!dev)
661 return;
663 #ifdef CONFIG_XEN_PCIDEV_FRONTEND
664 if (!is_initial_xendomain()) {
665 evtchn_map_pirq(dev->irq, 0);
666 pci_frontend_disable_msi(dev);
667 dev->irq = msi_dev_entry->default_irq;
668 return;
669 }
670 #endif
672 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
673 if (!pos)
674 return;
676 pirq = dev->irq;
677 /* Restore dev->irq to its default pin-assertion vector */
678 dev->irq = msi_dev_entry->default_irq;
679 msi_unmap_pirq(dev, pirq);
681 /* Disable MSI mode */
682 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
683 }
685 /**
686 * pci_enable_msix - configure device's MSI-X capability structure
687 * @dev: pointer to the pci_dev data structure of MSI-X device function
688 * @entries: pointer to an array of MSI-X entries
689 * @nvec: number of MSI-X vectors requested for allocation by device driver
690 *
691 * Setup the MSI-X capability structure of device function with the number
692 * of requested vectors upon its software driver call to request for
693 * MSI-X mode enabled on its hardware device function. A return of zero
694 * indicates the successful configuration of MSI-X capability structure
695 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
696 * Or a return of > 0 indicates that driver request is exceeding the number
697 * of vectors available. Driver should use the returned value to re-send
698 * its request.
699 **/
700 extern int pci_frontend_enable_msix(struct pci_dev *dev,
701 struct msix_entry *entries, int nvec);
702 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
703 {
704 struct pci_bus *bus;
705 int status, pos, nr_entries;
706 int i, j, temp;
707 u16 control;
708 struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
710 if (!pci_msi_enable || !dev || !entries)
711 return -EINVAL;
713 if (dev->no_msi)
714 return -EINVAL;
716 for (bus = dev->bus; bus; bus = bus->parent)
717 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
718 return -EINVAL;
720 #ifdef CONFIG_XEN_PCIDEV_FRONTEND
721 if (!is_initial_xendomain()) {
722 struct msi_dev_list *msi_dev_entry;
723 struct msi_pirq_entry *pirq_entry;
724 int ret, irq;
726 temp = dev->irq;
727 ret = pci_frontend_enable_msix(dev, entries, nvec);
728 if (ret) {
729 printk("get %x from pci_frontend_enable_msix\n", ret);
730 return ret;
731 }
732 msi_dev_entry->default_irq = temp;
734 msi_dev_entry = get_msi_dev_pirq_list(dev);
735 for (i = 0; i < nvec; i++) {
736 int mapped = 0;
738 list_for_each_entry(pirq_entry, &msi_dev_entry->pirq_list_head, list) {
739 if (pirq_entry->entry_nr == entries[i].entry) {
740 irq = pirq_entry->pirq;
741 BUG_ON(entries[i].vector != evtchn_get_xen_pirq(irq));
742 entries[i].vector = irq;
743 mapped = 1;
744 break;
745 }
746 }
747 if (mapped)
748 continue;
749 irq = evtchn_map_pirq(-1, entries[i].vector);
750 attach_pirq_entry(irq, entries[i].entry, msi_dev_entry);
751 entries[i].vector = irq;
752 }
753 return 0;
754 }
755 #endif
757 status = msi_init();
758 if (status < 0)
759 return status;
761 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
762 if (!pos)
763 return -EINVAL;
765 pci_read_config_word(dev, msi_control_reg(pos), &control);
766 nr_entries = multi_msix_capable(control);
767 if (nvec > nr_entries)
768 return -EINVAL;
770 /* Check for any invalid entries */
771 for (i = 0; i < nvec; i++) {
772 if (entries[i].entry >= nr_entries)
773 return -EINVAL; /* invalid entry */
774 for (j = i + 1; j < nvec; j++) {
775 if (entries[i].entry == entries[j].entry)
776 return -EINVAL; /* duplicate entry */
777 }
778 }
780 temp = dev->irq;
781 /* Check whether driver already requested for MSI vector */
782 if (dev->msi_enabled) {
783 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
784 "Device already has an MSI vector assigned\n",
785 pci_name(dev));
786 dev->irq = temp;
787 return -EINVAL;
788 }
790 status = msix_capability_init(dev, entries, nvec);
792 if ( !status )
793 msi_dev_entry->default_irq = temp;
794 else
795 dev->irq = temp;
797 return status;
798 }
800 extern void pci_frontend_disable_msix(struct pci_dev* dev);
801 void pci_disable_msix(struct pci_dev* dev)
802 {
803 int pos;
804 u16 control;
805 struct msi_dev_list *msi_dev_entry = get_msi_dev_pirq_list(dev);
808 if (!pci_msi_enable)
809 return;
810 if (!dev)
811 return;
813 #ifdef CONFIG_XEN_PCIDEV_FRONTEND
814 if (!is_initial_xendomain()) {
815 struct msi_dev_list *msi_dev_entry;
816 struct msi_pirq_entry *pirq_entry, *tmp;
818 pci_frontend_disable_msix(dev);
820 msi_dev_entry = get_msi_dev_pirq_list(dev);
821 list_for_each_entry_safe(pirq_entry, tmp,
822 &msi_dev_entry->pirq_list_head, list) {
823 evtchn_map_pirq(pirq_entry->pirq, 0);
824 list_del(&pirq_entry->list);
825 kfree(pirq_entry);
826 }
828 dev->irq = msi_dev_entry->default_irq;
829 return;
830 }
831 #endif
833 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
834 if (!pos)
835 return;
837 pci_read_config_word(dev, msi_control_reg(pos), &control);
838 if (!(control & PCI_MSIX_FLAGS_ENABLE))
839 return;
841 msi_remove_pci_irq_vectors(dev);
843 /* Disable MSI mode */
844 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
845 }
847 /**
848 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
849 * @dev: pointer to the pci_dev data structure of MSI(X) device function
850 *
851 * Being called during hotplug remove, from which the device function
852 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
853 * allocated for this device function, are reclaimed to unused state,
854 * which may be used later on.
855 **/
856 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
857 {
858 unsigned long flags;
859 struct msi_dev_list *msi_dev_entry;
860 struct msi_pirq_entry *pirq_entry, *tmp;
862 if (!pci_msi_enable || !dev)
863 return;
865 msi_dev_entry = get_msi_dev_pirq_list(dev);
867 spin_lock_irqsave(&msi_dev_entry->pirq_list_lock, flags);
868 if (!list_empty(&msi_dev_entry->pirq_list_head))
869 list_for_each_entry_safe(pirq_entry, tmp,
870 &msi_dev_entry->pirq_list_head, list) {
871 msi_unmap_pirq(dev, pirq_entry->pirq);
872 list_del(&pirq_entry->list);
873 kfree(pirq_entry);
874 }
875 spin_unlock_irqrestore(&msi_dev_entry->pirq_list_lock, flags);
876 iounmap(msi_dev_entry->mask_base);
877 msi_dev_entry->mask_base = NULL;
878 dev->irq = msi_dev_entry->default_irq;
879 }
881 void pci_no_msi(void)
882 {
883 pci_msi_enable = 0;
884 }
886 EXPORT_SYMBOL(pci_enable_msi);
887 EXPORT_SYMBOL(pci_disable_msi);
888 EXPORT_SYMBOL(pci_enable_msix);
889 EXPORT_SYMBOL(pci_disable_msix);
890 #ifdef CONFIG_XEN
891 EXPORT_SYMBOL(register_msi_get_owner);
892 EXPORT_SYMBOL(unregister_msi_get_owner);
893 #endif