ia64/linux-2.6.18-xen.hg

view drivers/pci/quirks.c @ 853:711e402bc141

PCI: sync up the SR-IOV changes between Dom0 and upstream kernel

The SR-IOV patches for the upstream kernel are finally in-tree. This
patch backports some minor changes that appeared in the upstream
kernel after the Dom0 patches were checked-in.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:48:03 2009 +0100 (2009-04-06)
parents 571229e265e2
children
line source
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include "pci.h"
27 #ifdef CONFIG_PCI_REASSIGN
28 /*
29 * This quirk function disables memory decoding and releases memory
30 * resources which is specified by kernel's boot parameter 'reassigndev'.
31 * Later on, kernel will assign page-aligned memory resource back
32 * to the device.
33 */
34 static void __devinit quirk_release_resources(struct pci_dev *dev)
35 {
36 int i;
37 struct resource *r;
38 u16 command;
40 if (pci_is_reassigndev(dev)) {
41 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
42 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
43 /* PCI Host Bridge isn't a target device */
44 return;
45 }
46 printk(KERN_INFO
47 "PCI: Disable memory decoding and release memory resources [%s].\n",
48 pci_name(dev));
49 pci_read_config_word(dev, PCI_COMMAND, &command);
50 command &= ~PCI_COMMAND_MEMORY;
51 pci_write_config_word(dev, PCI_COMMAND, command);
53 for (i=0; i < PCI_NUM_RESOURCES; i++) {
54 r = &dev->resource[i];
55 if (!(r->flags & IORESOURCE_MEM))
56 continue;
58 r->end = r->end - r->start;
59 r->start = 0;
61 if (i < PCI_BRIDGE_RESOURCES) {
62 pci_update_resource(dev, i);
63 }
64 }
65 /* need to disable bridge's resource window,
66 * to make kernel enable to reassign new resource
67 * window later on.
68 */
69 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
70 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
71 pci_disable_bridge_window(dev);
72 }
73 }
74 }
75 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_release_resources);
76 #endif /* CONFIG_PCI_REASSIGN */
78 /* The Mellanox Tavor device gives false positive parity errors
79 * Mark this device with a broken_parity_status, to allow
80 * PCI scanning code to "skip" this now blacklisted device.
81 */
82 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
83 {
84 dev->broken_parity_status = 1; /* This device gives false positives */
85 }
86 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
87 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
89 /* Deal with broken BIOS'es that neglect to enable passive release,
90 which can cause problems in combination with the 82441FX/PPro MTRRs */
91 static void __devinit quirk_passive_release(struct pci_dev *dev)
92 {
93 struct pci_dev *d = NULL;
94 unsigned char dlc;
96 /* We have to make sure a particular bit is set in the PIIX3
97 ISA bridge, so we have to go out and find it. */
98 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
99 pci_read_config_byte(d, 0x82, &dlc);
100 if (!(dlc & 1<<1)) {
101 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
102 dlc |= 1<<1;
103 pci_write_config_byte(d, 0x82, dlc);
104 }
105 }
106 }
107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
109 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
110 but VIA don't answer queries. If you happen to have good contacts at VIA
111 ask them for me please -- Alan
113 This appears to be BIOS not version dependent. So presumably there is a
114 chipset level fix */
115 int isa_dma_bridge_buggy; /* Exported */
117 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
118 {
119 if (!isa_dma_bridge_buggy) {
120 isa_dma_bridge_buggy=1;
121 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
122 }
123 }
124 /*
125 * Its not totally clear which chipsets are the problematic ones
126 * We know 82C586 and 82C596 variants are affected.
127 */
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
136 int pci_pci_problems;
138 /*
139 * Chipsets where PCI->PCI transfers vanish or hang
140 */
141 static void __devinit quirk_nopcipci(struct pci_dev *dev)
142 {
143 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
144 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
145 pci_pci_problems |= PCIPCI_FAIL;
146 }
147 }
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
151 /*
152 * Triton requires workarounds to be used by the drivers
153 */
154 static void __devinit quirk_triton(struct pci_dev *dev)
155 {
156 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
157 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
158 pci_pci_problems |= PCIPCI_TRITON;
159 }
160 }
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
166 /*
167 * VIA Apollo KT133 needs PCI latency patch
168 * Made according to a windows driver based patch by George E. Breese
169 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
176 static void __devinit quirk_vialatency(struct pci_dev *dev)
177 {
178 struct pci_dev *p;
179 u8 rev;
180 u8 busarb;
181 /* Ok we have a potential problem chipset here. Now see if we have
182 a buggy southbridge */
184 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
185 if (p!=NULL) {
186 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
187 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
188 /* Check for buggy part revisions */
189 if (rev < 0x40 || rev > 0x42)
190 goto exit;
191 } else {
192 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
193 if (p==NULL) /* No problem parts */
194 goto exit;
195 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
196 /* Check for buggy part revisions */
197 if (rev < 0x10 || rev > 0x12)
198 goto exit;
199 }
201 /*
202 * Ok we have the problem. Now set the PCI master grant to
203 * occur every master grant. The apparent bug is that under high
204 * PCI load (quite common in Linux of course) you can get data
205 * loss when the CPU is held off the bus for 3 bus master requests
206 * This happens to include the IDE controllers....
207 *
208 * VIA only apply this fix when an SB Live! is present but under
209 * both Linux and Windows this isnt enough, and we have seen
210 * corruption without SB Live! but with things like 3 UDMA IDE
211 * controllers. So we ignore that bit of the VIA recommendation..
212 */
214 pci_read_config_byte(dev, 0x76, &busarb);
215 /* Set bit 4 and bi 5 of byte 76 to 0x01
216 "Master priority rotation on every PCI master grant */
217 busarb &= ~(1<<5);
218 busarb |= (1<<4);
219 pci_write_config_byte(dev, 0x76, busarb);
220 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
221 exit:
222 pci_dev_put(p);
223 }
224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
228 /*
229 * VIA Apollo VP3 needs ETBF on BT848/878
230 */
231 static void __devinit quirk_viaetbf(struct pci_dev *dev)
232 {
233 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
234 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
235 pci_pci_problems |= PCIPCI_VIAETBF;
236 }
237 }
238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
240 static void __devinit quirk_vsfx(struct pci_dev *dev)
241 {
242 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
243 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
244 pci_pci_problems |= PCIPCI_VSFX;
245 }
246 }
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
249 /*
250 * Ali Magik requires workarounds to be used by the drivers
251 * that DMA to AGP space. Latency must be set to 0xA and triton
252 * workaround applied too
253 * [Info kindly provided by ALi]
254 */
255 static void __init quirk_alimagik(struct pci_dev *dev)
256 {
257 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
258 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
259 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
260 }
261 }
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
265 /*
266 * Natoma has some interesting boundary conditions with Zoran stuff
267 * at least
268 */
269 static void __devinit quirk_natoma(struct pci_dev *dev)
270 {
271 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
272 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
273 pci_pci_problems |= PCIPCI_NATOMA;
274 }
275 }
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
283 /*
284 * This chip can cause PCI parity errors if config register 0xA0 is read
285 * while DMAs are occurring.
286 */
287 static void __devinit quirk_citrine(struct pci_dev *dev)
288 {
289 dev->cfg_size = 0xA0;
290 }
291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
293 /*
294 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
295 * If it's needed, re-allocate the region.
296 */
297 static void __devinit quirk_s3_64M(struct pci_dev *dev)
298 {
299 struct resource *r = &dev->resource[0];
301 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
302 r->start = 0;
303 r->end = 0x3ffffff;
304 }
305 }
306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
309 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
310 unsigned size, int nr, const char *name)
311 {
312 region &= ~(size-1);
313 if (region) {
314 struct pci_bus_region bus_region;
315 struct resource *res = dev->resource + nr;
317 res->name = pci_name(dev);
318 res->start = region;
319 res->end = region + size - 1;
320 res->flags = IORESOURCE_IO;
322 /* Convert from PCI bus to resource space. */
323 bus_region.start = res->start;
324 bus_region.end = res->end;
325 pcibios_bus_to_resource(dev, res, &bus_region);
327 pci_claim_resource(dev, nr);
328 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
329 }
330 }
332 /*
333 * ATI Northbridge setups MCE the processor if you even
334 * read somewhere between 0x3b0->0x3bb or read 0x3d3
335 */
336 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
337 {
338 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
339 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
340 request_region(0x3b0, 0x0C, "RadeonIGP");
341 request_region(0x3d3, 0x01, "RadeonIGP");
342 }
343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
345 /*
346 * Let's make the southbridge information explicit instead
347 * of having to worry about people probing the ACPI areas,
348 * for example.. (Yes, it happens, and if you read the wrong
349 * ACPI register it will put the machine to sleep with no
350 * way of waking it up again. Bummer).
351 *
352 * ALI M7101: Two IO regions pointed to by words at
353 * 0xE0 (64 bytes of ACPI registers)
354 * 0xE2 (32 bytes of SMB registers)
355 */
356 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
357 {
358 u16 region;
360 pci_read_config_word(dev, 0xE0, &region);
361 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
362 pci_read_config_word(dev, 0xE2, &region);
363 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
364 }
365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
367 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
368 {
369 u32 devres;
370 u32 mask, size, base;
372 pci_read_config_dword(dev, port, &devres);
373 if ((devres & enable) != enable)
374 return;
375 mask = (devres >> 16) & 15;
376 base = devres & 0xffff;
377 size = 16;
378 for (;;) {
379 unsigned bit = size >> 1;
380 if ((bit & mask) == bit)
381 break;
382 size = bit;
383 }
384 /*
385 * For now we only print it out. Eventually we'll want to
386 * reserve it (at least if it's in the 0x1000+ range), but
387 * let's get enough confirmation reports first.
388 */
389 base &= -size;
390 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
391 }
393 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
394 {
395 u32 devres;
396 u32 mask, size, base;
398 pci_read_config_dword(dev, port, &devres);
399 if ((devres & enable) != enable)
400 return;
401 base = devres & 0xffff0000;
402 mask = (devres & 0x3f) << 16;
403 size = 128 << 16;
404 for (;;) {
405 unsigned bit = size >> 1;
406 if ((bit & mask) == bit)
407 break;
408 size = bit;
409 }
410 /*
411 * For now we only print it out. Eventually we'll want to
412 * reserve it, but let's get enough confirmation reports first.
413 */
414 base &= -size;
415 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
416 }
418 /*
419 * PIIX4 ACPI: Two IO regions pointed to by longwords at
420 * 0x40 (64 bytes of ACPI registers)
421 * 0x90 (16 bytes of SMB registers)
422 * and a few strange programmable PIIX4 device resources.
423 */
424 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
425 {
426 u32 region, res_a;
428 pci_read_config_dword(dev, 0x40, &region);
429 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
430 pci_read_config_dword(dev, 0x90, &region);
431 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
433 /* Device resource A has enables for some of the other ones */
434 pci_read_config_dword(dev, 0x5c, &res_a);
436 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
437 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
439 /* Device resource D is just bitfields for static resources */
441 /* Device 12 enabled? */
442 if (res_a & (1 << 29)) {
443 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
444 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
445 }
446 /* Device 13 enabled? */
447 if (res_a & (1 << 30)) {
448 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
449 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
450 }
451 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
452 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
453 }
454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
457 /*
458 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
459 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
460 * 0x58 (64 bytes of GPIO I/O space)
461 */
462 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
463 {
464 u32 region;
466 pci_read_config_dword(dev, 0x40, &region);
467 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
469 pci_read_config_dword(dev, 0x58, &region);
470 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
471 }
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
483 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
484 {
485 u32 region;
487 pci_read_config_dword(dev, 0x40, &region);
488 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
490 pci_read_config_dword(dev, 0x48, &region);
491 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
492 }
493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
496 /*
497 * VIA ACPI: One IO region pointed to by longword at
498 * 0x48 or 0x20 (256 bytes of ACPI registers)
499 */
500 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
501 {
502 u8 rev;
503 u32 region;
505 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
506 if (rev & 0x10) {
507 pci_read_config_dword(dev, 0x48, &region);
508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
510 }
511 }
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
514 /*
515 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
516 * 0x48 (256 bytes of ACPI registers)
517 * 0x70 (128 bytes of hardware monitoring register)
518 * 0x90 (16 bytes of SMB registers)
519 */
520 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
521 {
522 u16 hm;
523 u32 smb;
525 quirk_vt82c586_acpi(dev);
527 pci_read_config_word(dev, 0x70, &hm);
528 hm &= PCI_BASE_ADDRESS_IO_MASK;
529 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
531 pci_read_config_dword(dev, 0x90, &smb);
532 smb &= PCI_BASE_ADDRESS_IO_MASK;
533 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
534 }
535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
537 /*
538 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
539 * 0x88 (128 bytes of power management registers)
540 * 0xd0 (16 bytes of SMB registers)
541 */
542 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
543 {
544 u16 pm, smb;
546 pci_read_config_word(dev, 0x88, &pm);
547 pm &= PCI_BASE_ADDRESS_IO_MASK;
548 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
550 pci_read_config_word(dev, 0xd0, &smb);
551 smb &= PCI_BASE_ADDRESS_IO_MASK;
552 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
553 }
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
557 #ifdef CONFIG_X86_IO_APIC
559 #include <asm/io_apic.h>
561 /*
562 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
563 * devices to the external APIC.
564 *
565 * TODO: When we have device-specific interrupt routers,
566 * this code will go away from quirks.
567 */
568 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
569 {
570 u8 tmp;
572 if (nr_ioapics < 1)
573 tmp = 0; /* nothing routed to external APIC */
574 else
575 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
577 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
578 tmp == 0 ? "Disa" : "Ena");
580 /* Offset 0x58: External APIC IRQ output control */
581 pci_write_config_byte (dev, 0x58, tmp);
582 }
583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
585 /*
586 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
587 * This leads to doubled level interrupt rates.
588 * Set this bit to get rid of cycle wastage.
589 * Otherwise uncritical.
590 */
591 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
592 {
593 u8 misc_control2;
594 #define BYPASS_APIC_DEASSERT 8
596 pci_read_config_byte(dev, 0x5B, &misc_control2);
597 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
598 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
599 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
600 }
601 }
602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
604 /*
605 * The AMD io apic can hang the box when an apic irq is masked.
606 * We check all revs >= B0 (yet not in the pre production!) as the bug
607 * is currently marked NoFix
608 *
609 * We have multiple reports of hangs with this chipset that went away with
610 * noapic specified. For the moment we assume its the errata. We may be wrong
611 * of course. However the advice is demonstrably good even if so..
612 */
613 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
614 {
615 u8 rev;
617 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
618 if (rev >= 0x02) {
619 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
620 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
621 }
622 }
623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
625 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
626 {
627 if (dev->devfn == 0 && dev->bus->number == 0)
628 sis_apic_bug = 1;
629 }
630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
632 int pci_msi_quirk;
634 #define AMD8131_revA0 0x01
635 #define AMD8131_revB0 0x11
636 #define AMD8131_MISC 0x40
637 #define AMD8131_NIOAMODE_BIT 0
638 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
639 {
640 unsigned char revid, tmp;
642 if (dev->subordinate) {
643 printk(KERN_WARNING "PCI: MSI quirk detected. "
644 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
645 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
646 }
648 if (nr_ioapics == 0)
649 return;
651 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
652 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
653 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
654 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
655 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
656 pci_write_config_byte( dev, AMD8131_MISC, tmp);
657 }
658 }
659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
661 static void __init quirk_svw_msi(struct pci_dev *dev)
662 {
663 pci_msi_quirk = 1;
664 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
665 }
666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
667 #endif /* CONFIG_X86_IO_APIC */
670 /*
671 * FIXME: it is questionable that quirk_via_acpi
672 * is needed. It shows up as an ISA bridge, and does not
673 * support the PCI_INTERRUPT_LINE register at all. Therefore
674 * it seems like setting the pci_dev's 'irq' to the
675 * value of the ACPI SCI interrupt is only done for convenience.
676 * -jgarzik
677 */
678 static void __devinit quirk_via_acpi(struct pci_dev *d)
679 {
680 /*
681 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
682 */
683 u8 irq;
684 pci_read_config_byte(d, 0x42, &irq);
685 irq &= 0xf;
686 if (irq && (irq != 2))
687 d->irq = irq;
688 }
689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
692 /*
693 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
694 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
695 * when written, it makes an internal connection to the PIC.
696 * For these devices, this register is defined to be 4 bits wide.
697 * Normally this is fine. However for IO-APIC motherboards, or
698 * non-x86 architectures (yes Via exists on PPC among other places),
699 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
700 * interrupts delivered properly.
701 *
702 * Some of the on-chip devices are actually '586 devices' so they are
703 * listed here.
704 */
705 static void quirk_via_irq(struct pci_dev *dev)
706 {
707 u8 irq, new_irq;
709 new_irq = dev->irq & 0xf;
710 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
711 if (new_irq != irq) {
712 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
713 pci_name(dev), irq, new_irq);
714 udelay(15); /* unknown if delay really needed */
715 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
716 }
717 }
718 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
719 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
720 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
721 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
722 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq);
723 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
724 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
725 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
727 /*
728 * VIA VT82C598 has its device ID settable and many BIOSes
729 * set it to the ID of VT82C597 for backward compatibility.
730 * We need to switch it off to be able to recognize the real
731 * type of the chip.
732 */
733 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
734 {
735 pci_write_config_byte(dev, 0xfc, 0);
736 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
737 }
738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
740 /*
741 * CardBus controllers have a legacy base address that enables them
742 * to respond as i82365 pcmcia controllers. We don't want them to
743 * do this even if the Linux CardBus driver is not loaded, because
744 * the Linux i82365 driver does not (and should not) handle CardBus.
745 */
746 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
747 {
748 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
749 return;
750 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
751 }
752 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
754 /*
755 * Following the PCI ordering rules is optional on the AMD762. I'm not
756 * sure what the designers were smoking but let's not inhale...
757 *
758 * To be fair to AMD, it follows the spec by default, its BIOS people
759 * who turn it off!
760 */
761 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
762 {
763 u32 pcic;
764 pci_read_config_dword(dev, 0x4C, &pcic);
765 if ((pcic&6)!=6) {
766 pcic |= 6;
767 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
768 pci_write_config_dword(dev, 0x4C, pcic);
769 pci_read_config_dword(dev, 0x84, &pcic);
770 pcic |= (1<<23); /* Required in this mode */
771 pci_write_config_dword(dev, 0x84, pcic);
772 }
773 }
774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
776 /*
777 * DreamWorks provided workaround for Dunord I-3000 problem
778 *
779 * This card decodes and responds to addresses not apparently
780 * assigned to it. We force a larger allocation to ensure that
781 * nothing gets put too close to it.
782 */
783 static void __devinit quirk_dunord ( struct pci_dev * dev )
784 {
785 struct resource *r = &dev->resource [1];
786 r->start = 0;
787 r->end = 0xffffff;
788 }
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
791 /*
792 * i82380FB mobile docking controller: its PCI-to-PCI bridge
793 * is subtractive decoding (transparent), and does indicate this
794 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
795 * instead of 0x01.
796 */
797 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
798 {
799 dev->transparent = 1;
800 }
801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
804 /*
805 * Common misconfiguration of the MediaGX/Geode PCI master that will
806 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
807 * datasheets found at http://www.national.com/ds/GX for info on what
808 * these bits do. <christer@weinigel.se>
809 */
810 static void __init quirk_mediagx_master(struct pci_dev *dev)
811 {
812 u8 reg;
813 pci_read_config_byte(dev, 0x41, &reg);
814 if (reg & 2) {
815 reg &= ~2;
816 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
817 pci_write_config_byte(dev, 0x41, reg);
818 }
819 }
820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
822 /*
823 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
824 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
825 * secondary channels respectively). If the device reports Compatible mode
826 * but does use BAR0-3 for address decoding, we assume that firmware has
827 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
828 * Exceptions (if they exist) must be handled in chip/architecture specific
829 * fixups.
830 *
831 * Note: for non x86 people. You may need an arch specific quirk to handle
832 * moving IDE devices to native mode as well. Some plug in card devices power
833 * up in compatible mode and assume the BIOS will adjust them.
834 *
835 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
836 * we do now ? We don't want is pci_enable_device to come along
837 * and assign new resources. Both approaches work for that.
838 */
839 static void __devinit quirk_ide_bases(struct pci_dev *dev)
840 {
841 struct resource *res;
842 int first_bar = 2, last_bar = 0;
844 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
845 return;
847 res = &dev->resource[0];
849 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
850 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
851 res[0].start = res[0].end = res[0].flags = 0;
852 res[1].start = res[1].end = res[1].flags = 0;
853 first_bar = 0;
854 last_bar = 1;
855 }
857 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
858 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
859 res[2].start = res[2].end = res[2].flags = 0;
860 res[3].start = res[3].end = res[3].flags = 0;
861 last_bar = 3;
862 }
864 if (!last_bar)
865 return;
867 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
868 first_bar, last_bar, pci_name(dev));
869 }
870 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
872 /*
873 * Ensure C0 rev restreaming is off. This is normally done by
874 * the BIOS but in the odd case it is not the results are corruption
875 * hence the presence of a Linux check
876 */
877 static void __init quirk_disable_pxb(struct pci_dev *pdev)
878 {
879 u16 config;
880 u8 rev;
882 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
883 if (rev != 0x04) /* Only C0 requires this */
884 return;
885 pci_read_config_word(pdev, 0x40, &config);
886 if (config & (1<<6)) {
887 config &= ~(1<<6);
888 pci_write_config_word(pdev, 0x40, config);
889 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
890 }
891 }
892 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
894 static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
895 {
896 /* set sb600/sb700/sb800 sata to ahci mode */
897 u8 tmp;
899 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
900 if (tmp == 0x01) {
901 pci_read_config_byte(pdev, 0x40, &tmp);
902 pci_write_config_byte(pdev, 0x40, tmp|1);
903 pci_write_config_byte(pdev, 0x9, 1);
904 pci_write_config_byte(pdev, 0xa, 6);
905 pci_write_config_byte(pdev, 0x40, tmp);
907 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
908 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
909 }
910 }
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
914 /*
915 * Serverworks CSB5 IDE does not fully support native mode
916 */
917 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
918 {
919 u8 prog;
920 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
921 if (prog & 5) {
922 prog &= ~5;
923 pdev->class &= ~5;
924 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
925 /* need to re-assign BARs for compat mode */
926 quirk_ide_bases(pdev);
927 }
928 }
929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
931 /*
932 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
933 */
934 static void __init quirk_ide_samemode(struct pci_dev *pdev)
935 {
936 u8 prog;
938 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
940 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
941 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
942 prog &= ~5;
943 pdev->class &= ~5;
944 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
945 /* need to re-assign BARs for compat mode */
946 quirk_ide_bases(pdev);
947 }
948 }
949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
951 /* This was originally an Alpha specific thing, but it really fits here.
952 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
953 */
954 static void __init quirk_eisa_bridge(struct pci_dev *dev)
955 {
956 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
957 }
958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
960 /*
961 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
962 * when a PCI-Soundcard is added. The BIOS only gives Options
963 * "Disabled" and "AUTO". This Quirk Sets the corresponding
964 * Register-Value to enable the Soundcard.
965 *
966 * FIXME: Presently this quirk will run on anything that has an 8237
967 * which isn't correct, we need to check DMI tables or something in
968 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
969 * runs everywhere at present we suppress the printk output in most
970 * irrelevant cases.
971 */
972 static void __init k8t_sound_hostbridge(struct pci_dev *dev)
973 {
974 unsigned char val;
976 pci_read_config_byte(dev, 0x50, &val);
977 if (val == 0x88 || val == 0xc8) {
978 /* Assume it's probably a MSI-K8T-Neo2Fir */
979 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
980 pci_write_config_byte(dev, 0x50, val & (~0x40));
982 /* Verify the Change for Status output */
983 pci_read_config_byte(dev, 0x50, &val);
984 if (val & 0x40)
985 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
986 else
987 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
988 }
989 }
990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
992 #ifndef CONFIG_ACPI_SLEEP
993 /*
994 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
995 * is not activated. The myth is that Asus said that they do not want the
996 * users to be irritated by just another PCI Device in the Win98 device
997 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
998 * package 2.7.0 for details)
999 *
1000 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1001 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1002 * becomes necessary to do this tweak in two steps -- I've chosen the Host
1003 * bridge as trigger.
1005 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
1006 * will cause thermal management to break down, and causing machine to
1007 * overheat.
1008 */
1009 static int __initdata asus_hides_smbus;
1011 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1013 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1014 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1015 switch(dev->subsystem_device) {
1016 case 0x8025: /* P4B-LX */
1017 case 0x8070: /* P4B */
1018 case 0x8088: /* P4B533 */
1019 case 0x1626: /* L3C notebook */
1020 asus_hides_smbus = 1;
1022 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1023 switch(dev->subsystem_device) {
1024 case 0x80b1: /* P4GE-V */
1025 case 0x80b2: /* P4PE */
1026 case 0x8093: /* P4B533-V */
1027 asus_hides_smbus = 1;
1029 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1030 switch(dev->subsystem_device) {
1031 case 0x8030: /* P4T533 */
1032 asus_hides_smbus = 1;
1034 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1035 switch (dev->subsystem_device) {
1036 case 0x8070: /* P4G8X Deluxe */
1037 asus_hides_smbus = 1;
1039 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1040 switch (dev->subsystem_device) {
1041 case 0x80c9: /* PU-DLS */
1042 asus_hides_smbus = 1;
1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1045 switch (dev->subsystem_device) {
1046 case 0x1751: /* M2N notebook */
1047 case 0x1821: /* M5N notebook */
1048 asus_hides_smbus = 1;
1050 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1051 switch (dev->subsystem_device) {
1052 case 0x184b: /* W1N notebook */
1053 case 0x186a: /* M6Ne notebook */
1054 asus_hides_smbus = 1;
1056 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1057 switch (dev->subsystem_device) {
1058 case 0x1882: /* M6V notebook */
1059 case 0x1977: /* A6VA notebook */
1060 asus_hides_smbus = 1;
1063 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1064 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1065 switch(dev->subsystem_device) {
1066 case 0x088C: /* HP Compaq nc8000 */
1067 case 0x0890: /* HP Compaq nc6000 */
1068 asus_hides_smbus = 1;
1070 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1071 switch (dev->subsystem_device) {
1072 case 0x12bc: /* HP D330L */
1073 case 0x12bd: /* HP D530 */
1074 asus_hides_smbus = 1;
1076 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1077 switch (dev->subsystem_device) {
1078 case 0x099c: /* HP Compaq nx6110 */
1079 asus_hides_smbus = 1;
1082 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1083 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1084 switch(dev->subsystem_device) {
1085 case 0x0001: /* Toshiba Satellite A40 */
1086 asus_hides_smbus = 1;
1088 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1089 switch(dev->subsystem_device) {
1090 case 0x0001: /* Toshiba Tecra M2 */
1091 asus_hides_smbus = 1;
1093 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1094 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1095 switch(dev->subsystem_device) {
1096 case 0xC00C: /* Samsung P35 notebook */
1097 asus_hides_smbus = 1;
1099 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1100 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1101 switch(dev->subsystem_device) {
1102 case 0x0058: /* Compaq Evo N620c */
1103 asus_hides_smbus = 1;
1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1117 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1119 u16 val;
1121 if (likely(!asus_hides_smbus))
1122 return;
1124 pci_read_config_word(dev, 0xF2, &val);
1125 if (val & 0x8) {
1126 pci_write_config_word(dev, 0xF2, val & (~0x8));
1127 pci_read_config_word(dev, 0xF2, &val);
1128 if (val & 0x8)
1129 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1130 else
1131 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1141 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1143 u32 val, rcba;
1144 void __iomem *base;
1146 if (likely(!asus_hides_smbus))
1147 return;
1148 pci_read_config_dword(dev, 0xF0, &rcba);
1149 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1150 if (base == NULL) return;
1151 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1152 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1153 iounmap(base);
1154 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1158 #endif
1160 /*
1161 * SiS 96x south bridge: BIOS typically hides SMBus device...
1162 */
1163 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1165 u8 val = 0;
1166 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1167 pci_read_config_byte(dev, 0x77, &val);
1168 pci_write_config_byte(dev, 0x77, val & ~0x10);
1169 pci_read_config_byte(dev, 0x77, &val);
1172 /*
1173 * ... This is further complicated by the fact that some SiS96x south
1174 * bridges pretend to be 85C503/5513 instead. In that case see if we
1175 * spotted a compatible north bridge to make sure.
1176 * (pci_find_device doesn't work yet)
1178 * We can also enable the sis96x bit in the discovery register..
1179 */
1180 static int __devinitdata sis_96x_compatible = 0;
1182 #define SIS_DETECT_REGISTER 0x40
1184 static void __init quirk_sis_503(struct pci_dev *dev)
1186 u8 reg;
1187 u16 devid;
1189 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1190 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1191 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1192 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1193 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1194 return;
1197 /* Make people aware that we changed the config.. */
1198 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1200 /*
1201 * Ok, it now shows up as a 96x.. The 96x quirks are after
1202 * the 503 quirk in the quirk table, so they'll automatically
1203 * run and enable things like the SMBus device
1204 */
1205 dev->device = devid;
1208 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1210 sis_96x_compatible = 1;
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1220 /*
1221 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1222 * and MC97 modem controller are disabled when a second PCI soundcard is
1223 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1224 * -- bjd
1225 */
1226 static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1228 u8 val;
1229 int asus_hides_ac97 = 0;
1231 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1232 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1233 asus_hides_ac97 = 1;
1236 if (!asus_hides_ac97)
1237 return;
1239 pci_read_config_byte(dev, 0x50, &val);
1240 if (val & 0xc0) {
1241 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1242 pci_read_config_byte(dev, 0x50, &val);
1243 if (val & 0xc0)
1244 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1245 else
1246 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1257 #if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE)
1259 /*
1260 * If we are using libata we can drive this chip properly but must
1261 * do this early on to make the additional device appear during
1262 * the PCI scanning.
1263 */
1265 static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1267 u32 conf;
1268 u8 hdr;
1270 /* Only poke fn 0 */
1271 if (PCI_FUNC(pdev->devfn))
1272 return;
1274 switch(pdev->device) {
1275 case PCI_DEVICE_ID_JMICRON_JMB365:
1276 case PCI_DEVICE_ID_JMICRON_JMB366:
1277 /* Redirect IDE second PATA port to the right spot */
1278 pci_read_config_dword(pdev, 0x80, &conf);
1279 conf |= (1 << 24);
1280 /* Fall through */
1281 pci_write_config_dword(pdev, 0x80, conf);
1282 case PCI_DEVICE_ID_JMICRON_JMB361:
1283 case PCI_DEVICE_ID_JMICRON_JMB363:
1284 pci_read_config_dword(pdev, 0x40, &conf);
1285 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1286 /* Set the class codes correctly and then direct IDE 0 */
1287 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1288 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1289 pci_write_config_dword(pdev, 0x40, conf);
1291 /* Reconfigure so that the PCI scanner discovers the
1292 device is now multifunction */
1294 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1295 pdev->hdr_type = hdr & 0x7f;
1296 pdev->multifunction = !!(hdr & 0x80);
1298 break;
1302 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1304 #endif
1306 #ifdef CONFIG_X86_IO_APIC
1307 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1309 int i;
1311 if ((pdev->class >> 8) != 0xff00)
1312 return;
1314 /* the first BAR is the location of the IO APIC...we must
1315 * not touch this (and it's already covered by the fixmap), so
1316 * forcibly insert it into the resource tree */
1317 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1318 insert_resource(&iomem_resource, &pdev->resource[0]);
1320 /* The next five BARs all seem to be rubbish, so just clean
1321 * them out */
1322 for (i=1; i < 6; i++) {
1323 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1328 #endif
1330 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1331 /* Defaults to combined */
1332 static enum ide_combined_type combined_mode;
1334 static int __init combined_setup(char *str)
1336 if (!strncmp(str, "ide", 3))
1337 combined_mode = IDE;
1338 else if (!strncmp(str, "libata", 6))
1339 combined_mode = LIBATA;
1340 else /* "combined" or anything else defaults to old behavior */
1341 combined_mode = COMBINED;
1343 return 1;
1345 __setup("combined_mode=", combined_setup);
1347 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1348 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1350 u8 prog, comb, tmp;
1351 int ich = 0;
1353 /*
1354 * Narrow down to Intel SATA PCI devices.
1355 */
1356 switch (pdev->device) {
1357 /* PCI ids taken from drivers/scsi/ata_piix.c */
1358 case 0x24d1:
1359 case 0x24df:
1360 case 0x25a3:
1361 case 0x25b0:
1362 ich = 5;
1363 break;
1364 case 0x2651:
1365 case 0x2652:
1366 case 0x2653:
1367 case 0x2680: /* ESB2 */
1368 ich = 6;
1369 break;
1370 case 0x27c0:
1371 case 0x27c4:
1372 ich = 7;
1373 break;
1374 case 0x2828: /* ICH8M */
1375 ich = 8;
1376 break;
1377 default:
1378 /* we do not handle this PCI device */
1379 return;
1382 /*
1383 * Read combined mode register.
1384 */
1385 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1387 if (ich == 5) {
1388 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1389 if (tmp == 0x4) /* bits 10x */
1390 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1391 else if (tmp == 0x6) /* bits 11x */
1392 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1393 else
1394 return; /* not in combined mode */
1395 } else {
1396 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1397 tmp &= 0x3; /* interesting bits 1:0 */
1398 if (tmp & (1 << 0))
1399 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1400 else if (tmp & (1 << 1))
1401 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1402 else
1403 return; /* not in combined mode */
1406 /*
1407 * Read programming interface register.
1408 * (Tells us if it's legacy or native mode)
1409 */
1410 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1412 /* if SATA port is in native mode, we're ok. */
1413 if (prog & comb)
1414 return;
1416 /* Don't reserve any so the IDE driver can get them (but only if
1417 * combined_mode=ide).
1418 */
1419 if (combined_mode == IDE)
1420 return;
1422 /* Grab them both for libata if combined_mode=libata. */
1423 if (combined_mode == LIBATA) {
1424 request_region(0x1f0, 8, "libata"); /* port 0 */
1425 request_region(0x170, 8, "libata"); /* port 1 */
1426 return;
1429 /* SATA port is in legacy mode. Reserve port so that
1430 * IDE driver does not attempt to use it. If request_region
1431 * fails, it will be obvious at boot time, so we don't bother
1432 * checking return values.
1433 */
1434 if (comb == (1 << 0))
1435 request_region(0x1f0, 8, "libata"); /* port 0 */
1436 else
1437 request_region(0x170, 8, "libata"); /* port 1 */
1439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1440 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1443 int pcie_mch_quirk;
1445 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1447 pcie_mch_quirk = 1;
1449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1454 /*
1455 * It's possible for the MSI to get corrupted if shpc and acpi
1456 * are used together on certain PXH-based systems.
1457 */
1458 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1460 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1461 PCI_CAP_ID_MSI);
1462 dev->no_msi = 1;
1464 printk(KERN_WARNING "PCI: PXH quirk detected, "
1465 "disabling MSI for SHPC device\n");
1467 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1468 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1469 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1470 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1471 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1473 /*
1474 * Some Intel PCI Express chipsets have trouble with downstream
1475 * device power management.
1476 */
1477 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1479 pci_pm_d3_delay = 120;
1480 dev->no_d1d2 = 1;
1483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1493 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1497 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1498 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1505 /*
1506 * Fixup the cardbus bridges on the IBM Dock II docking station
1507 */
1508 static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1510 u32 val;
1512 /*
1513 * tie the 2 interrupt pins to INTA, and configure the
1514 * multifunction routing register to handle this.
1515 */
1516 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1517 (dev->subsystem_device == 0x0148)) {
1518 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1519 "applying quirk\n");
1520 pci_read_config_dword(dev, 0x8c, &val);
1521 val = ((val & 0xffffff00) | 0x1002);
1522 pci_write_config_dword(dev, 0x8c, val);
1523 pci_read_config_dword(dev, 0x80, &val);
1524 val = ((val & 0x00ffff00) | 0x2864c077);
1525 pci_write_config_dword(dev, 0x80, val);
1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1530 quirk_ibm_dock2_cardbus);
1532 static void __devinit quirk_netmos(struct pci_dev *dev)
1534 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1535 unsigned int num_serial = dev->subsystem_device & 0xf;
1537 /*
1538 * These Netmos parts are multiport serial devices with optional
1539 * parallel ports. Even when parallel ports are present, they
1540 * are identified as class SERIAL, which means the serial driver
1541 * will claim them. To prevent this, mark them as class OTHER.
1542 * These combo devices should be claimed by parport_serial.
1544 * The subdevice ID is of the form 0x00PS, where <P> is the number
1545 * of parallel ports and <S> is the number of serial ports.
1546 */
1547 switch (dev->device) {
1548 case PCI_DEVICE_ID_NETMOS_9735:
1549 case PCI_DEVICE_ID_NETMOS_9745:
1550 case PCI_DEVICE_ID_NETMOS_9835:
1551 case PCI_DEVICE_ID_NETMOS_9845:
1552 case PCI_DEVICE_ID_NETMOS_9855:
1553 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1554 num_parallel) {
1555 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1556 "%u serial); changing class SERIAL to OTHER "
1557 "(use parport_serial)\n",
1558 dev->device, num_parallel, num_serial);
1559 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1560 (dev->class & 0xff);
1564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1566 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1568 u16 command, pmcsr;
1569 u32 bar;
1570 u8 __iomem *csr;
1571 u8 cmd_hi;
1572 int pm;
1574 switch (dev->device) {
1575 /* PCI IDs taken from drivers/net/e100.c */
1576 case 0x1029:
1577 case 0x1030 ... 0x1034:
1578 case 0x1038 ... 0x103E:
1579 case 0x1050 ... 0x1057:
1580 case 0x1059:
1581 case 0x1064 ... 0x106B:
1582 case 0x1091 ... 0x1095:
1583 case 0x1209:
1584 case 0x1229:
1585 case 0x2449:
1586 case 0x2459:
1587 case 0x245D:
1588 case 0x27DC:
1589 break;
1590 default:
1591 return;
1594 /*
1595 * Some firmware hands off the e100 with interrupts enabled,
1596 * which can cause a flood of interrupts if packets are
1597 * received before the driver attaches to the device. So
1598 * disable all e100 interrupts here. The driver will
1599 * re-enable them when it's ready.
1600 */
1601 pci_read_config_word(dev, PCI_COMMAND, &command);
1602 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1604 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1605 return;
1607 /*
1608 * Check that the device is in the D0 power state. If it's not,
1609 * there is no point to look any further.
1610 */
1611 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1612 if (pm) {
1613 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1614 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1615 return;
1618 csr = ioremap(bar, 8);
1619 if (!csr) {
1620 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1621 pci_name(dev));
1622 return;
1625 cmd_hi = readb(csr + 3);
1626 if (cmd_hi == 0) {
1627 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1628 "enabled, disabling\n", pci_name(dev));
1629 writeb(1, csr + 3);
1632 iounmap(csr);
1634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1636 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1638 /* rev 1 ncr53c810 chips don't set the class at all which means
1639 * they don't get their resources remapped. Fix that here.
1640 */
1642 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1643 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1644 dev->class = PCI_CLASS_STORAGE_SCSI;
1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1650 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1652 while (f < end) {
1653 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1654 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1655 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1656 f->hook(dev);
1658 f++;
1662 extern struct pci_fixup __start_pci_fixups_early[];
1663 extern struct pci_fixup __end_pci_fixups_early[];
1664 extern struct pci_fixup __start_pci_fixups_header[];
1665 extern struct pci_fixup __end_pci_fixups_header[];
1666 extern struct pci_fixup __start_pci_fixups_final[];
1667 extern struct pci_fixup __end_pci_fixups_final[];
1668 extern struct pci_fixup __start_pci_fixups_enable[];
1669 extern struct pci_fixup __end_pci_fixups_enable[];
1672 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1674 struct pci_fixup *start, *end;
1676 switch(pass) {
1677 case pci_fixup_early:
1678 start = __start_pci_fixups_early;
1679 end = __end_pci_fixups_early;
1680 break;
1682 case pci_fixup_header:
1683 start = __start_pci_fixups_header;
1684 end = __end_pci_fixups_header;
1685 break;
1687 case pci_fixup_final:
1688 start = __start_pci_fixups_final;
1689 end = __end_pci_fixups_final;
1690 break;
1692 case pci_fixup_enable:
1693 start = __start_pci_fixups_enable;
1694 end = __end_pci_fixups_enable;
1695 break;
1697 default:
1698 /* stupid compiler warning, you would think with an enum... */
1699 return;
1701 pci_do_fixups(dev, start, end);
1704 /* Enable 1k I/O space granularity on the Intel P64H2 */
1705 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1707 u16 en1k;
1708 u8 io_base_lo, io_limit_lo;
1709 unsigned long base, limit;
1710 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1712 pci_read_config_word(dev, 0x40, &en1k);
1714 if (en1k & 0x200) {
1715 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1717 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1718 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1719 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1720 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1722 if (base <= limit) {
1723 res->start = base;
1724 res->end = limit + 0x3ff;
1728 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1730 /* Under some circumstances, AER is not linked with extended capabilities.
1731 * Force it to be linked by setting the corresponding control bit in the
1732 * config space.
1733 */
1734 static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1736 uint8_t b;
1737 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1738 if (!(b & 0x20)) {
1739 pci_write_config_byte(dev, 0xf41, b | 0x20);
1740 printk(KERN_INFO
1741 "PCI: Linking AER extended capability on %s\n",
1742 pci_name(dev));
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1747 quirk_nvidia_ck804_pcie_aer_ext_cap);
1749 EXPORT_SYMBOL(pcie_mch_quirk);
1750 #ifdef CONFIG_HOTPLUG
1751 EXPORT_SYMBOL(pci_fixup_device);
1752 #endif
1754 #ifdef CONFIG_PCI_IOV
1756 /*
1757 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
1758 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
1759 * old Flash Memory Space.
1760 */
1761 static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
1763 int pos, flags;
1764 u32 bar, start, size;
1766 if (PAGE_SIZE > 0x10000)
1767 return;
1769 flags = pci_resource_flags(dev, 0);
1770 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
1771 PCI_BASE_ADDRESS_SPACE_MEMORY ||
1772 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
1773 PCI_BASE_ADDRESS_MEM_TYPE_32)
1774 return;
1776 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
1777 if (!pos)
1778 return;
1780 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
1781 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
1782 return;
1784 start = pci_resource_start(dev, 1);
1785 size = pci_resource_len(dev, 1);
1786 if (!start || size != 0x400000 || start & (size - 1))
1787 return;
1789 pci_resource_flags(dev, 1) = 0;
1790 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1791 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
1792 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
1794 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
1796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
1797 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
1798 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
1800 #endif /* CONFIG_PCI_IOV */