ia64/linux-2.6.18-xen.hg

view drivers/serial/sunsu.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* $Id: su.c,v 1.55 2002/01/08 16:00:16 davem Exp $
2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
15 * David S. Miller (davem@davemloft.net), 2002-Jul-29
16 */
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #ifdef CONFIG_SERIO
34 #include <linux/serio.h>
35 #endif
36 #include <linux/serial_reg.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <asm/io.h>
41 #include <asm/irq.h>
42 #include <asm/prom.h>
43 #include <asm/of_device.h>
45 #if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46 #define SUPPORT_SYSRQ
47 #endif
49 #include <linux/serial_core.h>
51 #include "suncore.h"
53 /* We are on a NS PC87303 clocked with 24.0 MHz, which results
54 * in a UART clock of 1.8462 MHz.
55 */
56 #define SU_BASE_BAUD (1846200 / 16)
58 enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
59 static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
61 /*
62 * Here we define the default xmit fifo size used for each type of UART.
63 */
64 static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
65 { "unknown", 1, 0 },
66 { "8250", 1, 0 },
67 { "16450", 1, 0 },
68 { "16550", 1, 0 },
69 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
70 { "Cirrus", 1, 0 },
71 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
72 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
73 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
74 { "Startech", 1, 0 },
75 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
76 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
77 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
78 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
79 };
81 struct uart_sunsu_port {
82 struct uart_port port;
83 unsigned char acr;
84 unsigned char ier;
85 unsigned short rev;
86 unsigned char lcr;
87 unsigned int lsr_break_flag;
88 unsigned int cflag;
90 /* Probing information. */
91 enum su_type su_type;
92 unsigned int type_probed; /* XXX Stupid */
93 unsigned long reg_size;
95 #ifdef CONFIG_SERIO
96 struct serio serio;
97 int serio_open;
98 #endif
99 };
101 static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
102 {
103 offset <<= up->port.regshift;
105 switch (up->port.iotype) {
106 case UPIO_HUB6:
107 outb(up->port.hub6 - 1 + offset, up->port.iobase);
108 return inb(up->port.iobase + 1);
110 case UPIO_MEM:
111 return readb(up->port.membase + offset);
113 default:
114 return inb(up->port.iobase + offset);
115 }
116 }
118 static void serial_out(struct uart_sunsu_port *up, int offset, int value)
119 {
120 #ifndef CONFIG_SPARC64
121 /*
122 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
123 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
124 * gate outputs a logical one. Since we use level triggered interrupts
125 * we have lockup and watchdog reset. We cannot mask IRQ because
126 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
127 * This problem is similar to what Alpha people suffer, see serial.c.
128 */
129 if (offset == UART_MCR)
130 value |= UART_MCR_OUT2;
131 #endif
132 offset <<= up->port.regshift;
134 switch (up->port.iotype) {
135 case UPIO_HUB6:
136 outb(up->port.hub6 - 1 + offset, up->port.iobase);
137 outb(value, up->port.iobase + 1);
138 break;
140 case UPIO_MEM:
141 writeb(value, up->port.membase + offset);
142 break;
144 default:
145 outb(value, up->port.iobase + offset);
146 }
147 }
149 /*
150 * We used to support using pause I/O for certain machines. We
151 * haven't supported this for a while, but just in case it's badly
152 * needed for certain old 386 machines, I've left these #define's
153 * in....
154 */
155 #define serial_inp(up, offset) serial_in(up, offset)
156 #define serial_outp(up, offset, value) serial_out(up, offset, value)
159 /*
160 * For the 16C950
161 */
162 static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
163 {
164 serial_out(up, UART_SCR, offset);
165 serial_out(up, UART_ICR, value);
166 }
168 #if 0 /* Unused currently */
169 static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
170 {
171 unsigned int value;
173 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
174 serial_out(up, UART_SCR, offset);
175 value = serial_in(up, UART_ICR);
176 serial_icr_write(up, UART_ACR, up->acr);
178 return value;
179 }
180 #endif
182 #ifdef CONFIG_SERIAL_8250_RSA
183 /*
184 * Attempts to turn on the RSA FIFO. Returns zero on failure.
185 * We set the port uart clock rate if we succeed.
186 */
187 static int __enable_rsa(struct uart_sunsu_port *up)
188 {
189 unsigned char mode;
190 int result;
192 mode = serial_inp(up, UART_RSA_MSR);
193 result = mode & UART_RSA_MSR_FIFO;
195 if (!result) {
196 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
197 mode = serial_inp(up, UART_RSA_MSR);
198 result = mode & UART_RSA_MSR_FIFO;
199 }
201 if (result)
202 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
204 return result;
205 }
207 static void enable_rsa(struct uart_sunsu_port *up)
208 {
209 if (up->port.type == PORT_RSA) {
210 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
211 spin_lock_irq(&up->port.lock);
212 __enable_rsa(up);
213 spin_unlock_irq(&up->port.lock);
214 }
215 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
216 serial_outp(up, UART_RSA_FRR, 0);
217 }
218 }
220 /*
221 * Attempts to turn off the RSA FIFO. Returns zero on failure.
222 * It is unknown why interrupts were disabled in here. However,
223 * the caller is expected to preserve this behaviour by grabbing
224 * the spinlock before calling this function.
225 */
226 static void disable_rsa(struct uart_sunsu_port *up)
227 {
228 unsigned char mode;
229 int result;
231 if (up->port.type == PORT_RSA &&
232 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
233 spin_lock_irq(&up->port.lock);
235 mode = serial_inp(up, UART_RSA_MSR);
236 result = !(mode & UART_RSA_MSR_FIFO);
238 if (!result) {
239 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
240 mode = serial_inp(up, UART_RSA_MSR);
241 result = !(mode & UART_RSA_MSR_FIFO);
242 }
244 if (result)
245 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
246 spin_unlock_irq(&up->port.lock);
247 }
248 }
249 #endif /* CONFIG_SERIAL_8250_RSA */
251 static inline void __stop_tx(struct uart_sunsu_port *p)
252 {
253 if (p->ier & UART_IER_THRI) {
254 p->ier &= ~UART_IER_THRI;
255 serial_out(p, UART_IER, p->ier);
256 }
257 }
259 static void sunsu_stop_tx(struct uart_port *port)
260 {
261 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
263 __stop_tx(up);
265 /*
266 * We really want to stop the transmitter from sending.
267 */
268 if (up->port.type == PORT_16C950) {
269 up->acr |= UART_ACR_TXDIS;
270 serial_icr_write(up, UART_ACR, up->acr);
271 }
272 }
274 static void sunsu_start_tx(struct uart_port *port)
275 {
276 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
278 if (!(up->ier & UART_IER_THRI)) {
279 up->ier |= UART_IER_THRI;
280 serial_out(up, UART_IER, up->ier);
281 }
283 /*
284 * Re-enable the transmitter if we disabled it.
285 */
286 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
287 up->acr &= ~UART_ACR_TXDIS;
288 serial_icr_write(up, UART_ACR, up->acr);
289 }
290 }
292 static void sunsu_stop_rx(struct uart_port *port)
293 {
294 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
296 up->ier &= ~UART_IER_RLSI;
297 up->port.read_status_mask &= ~UART_LSR_DR;
298 serial_out(up, UART_IER, up->ier);
299 }
301 static void sunsu_enable_ms(struct uart_port *port)
302 {
303 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
304 unsigned long flags;
306 spin_lock_irqsave(&up->port.lock, flags);
307 up->ier |= UART_IER_MSI;
308 serial_out(up, UART_IER, up->ier);
309 spin_unlock_irqrestore(&up->port.lock, flags);
310 }
312 static struct tty_struct *
313 receive_chars(struct uart_sunsu_port *up, unsigned char *status, struct pt_regs *regs)
314 {
315 struct tty_struct *tty = up->port.info->tty;
316 unsigned char ch, flag;
317 int max_count = 256;
318 int saw_console_brk = 0;
320 do {
321 ch = serial_inp(up, UART_RX);
322 flag = TTY_NORMAL;
323 up->port.icount.rx++;
325 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
326 UART_LSR_FE | UART_LSR_OE))) {
327 /*
328 * For statistics only
329 */
330 if (*status & UART_LSR_BI) {
331 *status &= ~(UART_LSR_FE | UART_LSR_PE);
332 up->port.icount.brk++;
333 if (up->port.cons != NULL &&
334 up->port.line == up->port.cons->index)
335 saw_console_brk = 1;
336 /*
337 * We do the SysRQ and SAK checking
338 * here because otherwise the break
339 * may get masked by ignore_status_mask
340 * or read_status_mask.
341 */
342 if (uart_handle_break(&up->port))
343 goto ignore_char;
344 } else if (*status & UART_LSR_PE)
345 up->port.icount.parity++;
346 else if (*status & UART_LSR_FE)
347 up->port.icount.frame++;
348 if (*status & UART_LSR_OE)
349 up->port.icount.overrun++;
351 /*
352 * Mask off conditions which should be ingored.
353 */
354 *status &= up->port.read_status_mask;
356 if (up->port.cons != NULL &&
357 up->port.line == up->port.cons->index) {
358 /* Recover the break flag from console xmit */
359 *status |= up->lsr_break_flag;
360 up->lsr_break_flag = 0;
361 }
363 if (*status & UART_LSR_BI) {
364 flag = TTY_BREAK;
365 } else if (*status & UART_LSR_PE)
366 flag = TTY_PARITY;
367 else if (*status & UART_LSR_FE)
368 flag = TTY_FRAME;
369 }
370 if (uart_handle_sysrq_char(&up->port, ch, regs))
371 goto ignore_char;
372 if ((*status & up->port.ignore_status_mask) == 0)
373 tty_insert_flip_char(tty, ch, flag);
374 if (*status & UART_LSR_OE)
375 /*
376 * Overrun is special, since it's reported
377 * immediately, and doesn't affect the current
378 * character.
379 */
380 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
381 ignore_char:
382 *status = serial_inp(up, UART_LSR);
383 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
385 if (saw_console_brk)
386 sun_do_break();
388 return tty;
389 }
391 static void transmit_chars(struct uart_sunsu_port *up)
392 {
393 struct circ_buf *xmit = &up->port.info->xmit;
394 int count;
396 if (up->port.x_char) {
397 serial_outp(up, UART_TX, up->port.x_char);
398 up->port.icount.tx++;
399 up->port.x_char = 0;
400 return;
401 }
402 if (uart_tx_stopped(&up->port)) {
403 sunsu_stop_tx(&up->port);
404 return;
405 }
406 if (uart_circ_empty(xmit)) {
407 __stop_tx(up);
408 return;
409 }
411 count = up->port.fifosize;
412 do {
413 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
414 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
415 up->port.icount.tx++;
416 if (uart_circ_empty(xmit))
417 break;
418 } while (--count > 0);
420 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
421 uart_write_wakeup(&up->port);
423 if (uart_circ_empty(xmit))
424 __stop_tx(up);
425 }
427 static void check_modem_status(struct uart_sunsu_port *up)
428 {
429 int status;
431 status = serial_in(up, UART_MSR);
433 if ((status & UART_MSR_ANY_DELTA) == 0)
434 return;
436 if (status & UART_MSR_TERI)
437 up->port.icount.rng++;
438 if (status & UART_MSR_DDSR)
439 up->port.icount.dsr++;
440 if (status & UART_MSR_DDCD)
441 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
442 if (status & UART_MSR_DCTS)
443 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
445 wake_up_interruptible(&up->port.info->delta_msr_wait);
446 }
448 static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id, struct pt_regs *regs)
449 {
450 struct uart_sunsu_port *up = dev_id;
451 unsigned long flags;
452 unsigned char status;
454 spin_lock_irqsave(&up->port.lock, flags);
456 do {
457 struct tty_struct *tty;
459 status = serial_inp(up, UART_LSR);
460 tty = NULL;
461 if (status & UART_LSR_DR)
462 tty = receive_chars(up, &status, regs);
463 check_modem_status(up);
464 if (status & UART_LSR_THRE)
465 transmit_chars(up);
467 spin_unlock_irqrestore(&up->port.lock, flags);
469 if (tty)
470 tty_flip_buffer_push(tty);
472 spin_lock_irqsave(&up->port.lock, flags);
474 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
476 spin_unlock_irqrestore(&up->port.lock, flags);
478 return IRQ_HANDLED;
479 }
481 /* Separate interrupt handling path for keyboard/mouse ports. */
483 static void
484 sunsu_change_speed(struct uart_port *port, unsigned int cflag,
485 unsigned int iflag, unsigned int quot);
487 static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
488 {
489 unsigned int cur_cflag = up->cflag;
490 int quot, new_baud;
492 up->cflag &= ~CBAUD;
493 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
495 quot = up->port.uartclk / (16 * new_baud);
497 sunsu_change_speed(&up->port, up->cflag, 0, quot);
498 }
500 static void receive_kbd_ms_chars(struct uart_sunsu_port *up, struct pt_regs *regs, int is_break)
501 {
502 do {
503 unsigned char ch = serial_inp(up, UART_RX);
505 /* Stop-A is handled by drivers/char/keyboard.c now. */
506 if (up->su_type == SU_PORT_KBD) {
507 #ifdef CONFIG_SERIO
508 serio_interrupt(&up->serio, ch, 0, regs);
509 #endif
510 } else if (up->su_type == SU_PORT_MS) {
511 int ret = suncore_mouse_baud_detection(ch, is_break);
513 switch (ret) {
514 case 2:
515 sunsu_change_mouse_baud(up);
516 /* fallthru */
517 case 1:
518 break;
520 case 0:
521 #ifdef CONFIG_SERIO
522 serio_interrupt(&up->serio, ch, 0, regs);
523 #endif
524 break;
525 };
526 }
527 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
528 }
530 static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id, struct pt_regs *regs)
531 {
532 struct uart_sunsu_port *up = dev_id;
534 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
535 unsigned char status = serial_inp(up, UART_LSR);
537 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
538 receive_kbd_ms_chars(up, regs,
539 (status & UART_LSR_BI) != 0);
540 }
542 return IRQ_HANDLED;
543 }
545 static unsigned int sunsu_tx_empty(struct uart_port *port)
546 {
547 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
548 unsigned long flags;
549 unsigned int ret;
551 spin_lock_irqsave(&up->port.lock, flags);
552 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
553 spin_unlock_irqrestore(&up->port.lock, flags);
555 return ret;
556 }
558 static unsigned int sunsu_get_mctrl(struct uart_port *port)
559 {
560 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
561 unsigned char status;
562 unsigned int ret;
564 status = serial_in(up, UART_MSR);
566 ret = 0;
567 if (status & UART_MSR_DCD)
568 ret |= TIOCM_CAR;
569 if (status & UART_MSR_RI)
570 ret |= TIOCM_RNG;
571 if (status & UART_MSR_DSR)
572 ret |= TIOCM_DSR;
573 if (status & UART_MSR_CTS)
574 ret |= TIOCM_CTS;
575 return ret;
576 }
578 static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
579 {
580 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
581 unsigned char mcr = 0;
583 if (mctrl & TIOCM_RTS)
584 mcr |= UART_MCR_RTS;
585 if (mctrl & TIOCM_DTR)
586 mcr |= UART_MCR_DTR;
587 if (mctrl & TIOCM_OUT1)
588 mcr |= UART_MCR_OUT1;
589 if (mctrl & TIOCM_OUT2)
590 mcr |= UART_MCR_OUT2;
591 if (mctrl & TIOCM_LOOP)
592 mcr |= UART_MCR_LOOP;
594 serial_out(up, UART_MCR, mcr);
595 }
597 static void sunsu_break_ctl(struct uart_port *port, int break_state)
598 {
599 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
600 unsigned long flags;
602 spin_lock_irqsave(&up->port.lock, flags);
603 if (break_state == -1)
604 up->lcr |= UART_LCR_SBC;
605 else
606 up->lcr &= ~UART_LCR_SBC;
607 serial_out(up, UART_LCR, up->lcr);
608 spin_unlock_irqrestore(&up->port.lock, flags);
609 }
611 static int sunsu_startup(struct uart_port *port)
612 {
613 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
614 unsigned long flags;
615 int retval;
617 if (up->port.type == PORT_16C950) {
618 /* Wake up and initialize UART */
619 up->acr = 0;
620 serial_outp(up, UART_LCR, 0xBF);
621 serial_outp(up, UART_EFR, UART_EFR_ECB);
622 serial_outp(up, UART_IER, 0);
623 serial_outp(up, UART_LCR, 0);
624 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
625 serial_outp(up, UART_LCR, 0xBF);
626 serial_outp(up, UART_EFR, UART_EFR_ECB);
627 serial_outp(up, UART_LCR, 0);
628 }
630 #ifdef CONFIG_SERIAL_8250_RSA
631 /*
632 * If this is an RSA port, see if we can kick it up to the
633 * higher speed clock.
634 */
635 enable_rsa(up);
636 #endif
638 /*
639 * Clear the FIFO buffers and disable them.
640 * (they will be reenabled in set_termios())
641 */
642 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
643 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
644 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
645 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
646 serial_outp(up, UART_FCR, 0);
647 }
649 /*
650 * Clear the interrupt registers.
651 */
652 (void) serial_inp(up, UART_LSR);
653 (void) serial_inp(up, UART_RX);
654 (void) serial_inp(up, UART_IIR);
655 (void) serial_inp(up, UART_MSR);
657 /*
658 * At this point, there's no way the LSR could still be 0xff;
659 * if it is, then bail out, because there's likely no UART
660 * here.
661 */
662 if (!(up->port.flags & UPF_BUGGY_UART) &&
663 (serial_inp(up, UART_LSR) == 0xff)) {
664 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
665 return -ENODEV;
666 }
668 if (up->su_type != SU_PORT_PORT) {
669 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
670 IRQF_SHARED, su_typev[up->su_type], up);
671 } else {
672 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
673 IRQF_SHARED, su_typev[up->su_type], up);
674 }
675 if (retval) {
676 printk("su: Cannot register IRQ %d\n", up->port.irq);
677 return retval;
678 }
680 /*
681 * Now, initialize the UART
682 */
683 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
685 spin_lock_irqsave(&up->port.lock, flags);
687 up->port.mctrl |= TIOCM_OUT2;
689 sunsu_set_mctrl(&up->port, up->port.mctrl);
690 spin_unlock_irqrestore(&up->port.lock, flags);
692 /*
693 * Finally, enable interrupts. Note: Modem status interrupts
694 * are set via set_termios(), which will be occurring imminently
695 * anyway, so we don't enable them here.
696 */
697 up->ier = UART_IER_RLSI | UART_IER_RDI;
698 serial_outp(up, UART_IER, up->ier);
700 if (up->port.flags & UPF_FOURPORT) {
701 unsigned int icp;
702 /*
703 * Enable interrupts on the AST Fourport board
704 */
705 icp = (up->port.iobase & 0xfe0) | 0x01f;
706 outb_p(0x80, icp);
707 (void) inb_p(icp);
708 }
710 /*
711 * And clear the interrupt registers again for luck.
712 */
713 (void) serial_inp(up, UART_LSR);
714 (void) serial_inp(up, UART_RX);
715 (void) serial_inp(up, UART_IIR);
716 (void) serial_inp(up, UART_MSR);
718 return 0;
719 }
721 static void sunsu_shutdown(struct uart_port *port)
722 {
723 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
724 unsigned long flags;
726 /*
727 * Disable interrupts from this port
728 */
729 up->ier = 0;
730 serial_outp(up, UART_IER, 0);
732 spin_lock_irqsave(&up->port.lock, flags);
733 if (up->port.flags & UPF_FOURPORT) {
734 /* reset interrupts on the AST Fourport board */
735 inb((up->port.iobase & 0xfe0) | 0x1f);
736 up->port.mctrl |= TIOCM_OUT1;
737 } else
738 up->port.mctrl &= ~TIOCM_OUT2;
740 sunsu_set_mctrl(&up->port, up->port.mctrl);
741 spin_unlock_irqrestore(&up->port.lock, flags);
743 /*
744 * Disable break condition and FIFOs
745 */
746 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
747 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
748 UART_FCR_CLEAR_RCVR |
749 UART_FCR_CLEAR_XMIT);
750 serial_outp(up, UART_FCR, 0);
752 #ifdef CONFIG_SERIAL_8250_RSA
753 /*
754 * Reset the RSA board back to 115kbps compat mode.
755 */
756 disable_rsa(up);
757 #endif
759 /*
760 * Read data port to reset things.
761 */
762 (void) serial_in(up, UART_RX);
764 free_irq(up->port.irq, up);
765 }
767 static void
768 sunsu_change_speed(struct uart_port *port, unsigned int cflag,
769 unsigned int iflag, unsigned int quot)
770 {
771 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
772 unsigned char cval, fcr = 0;
773 unsigned long flags;
775 switch (cflag & CSIZE) {
776 case CS5:
777 cval = 0x00;
778 break;
779 case CS6:
780 cval = 0x01;
781 break;
782 case CS7:
783 cval = 0x02;
784 break;
785 default:
786 case CS8:
787 cval = 0x03;
788 break;
789 }
791 if (cflag & CSTOPB)
792 cval |= 0x04;
793 if (cflag & PARENB)
794 cval |= UART_LCR_PARITY;
795 if (!(cflag & PARODD))
796 cval |= UART_LCR_EPAR;
797 #ifdef CMSPAR
798 if (cflag & CMSPAR)
799 cval |= UART_LCR_SPAR;
800 #endif
802 /*
803 * Work around a bug in the Oxford Semiconductor 952 rev B
804 * chip which causes it to seriously miscalculate baud rates
805 * when DLL is 0.
806 */
807 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
808 up->rev == 0x5201)
809 quot ++;
811 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
812 if ((up->port.uartclk / quot) < (2400 * 16))
813 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
814 #ifdef CONFIG_SERIAL_8250_RSA
815 else if (up->port.type == PORT_RSA)
816 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
817 #endif
818 else
819 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
820 }
821 if (up->port.type == PORT_16750)
822 fcr |= UART_FCR7_64BYTE;
824 /*
825 * Ok, we're now changing the port state. Do it with
826 * interrupts disabled.
827 */
828 spin_lock_irqsave(&up->port.lock, flags);
830 /*
831 * Update the per-port timeout.
832 */
833 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
835 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
836 if (iflag & INPCK)
837 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
838 if (iflag & (BRKINT | PARMRK))
839 up->port.read_status_mask |= UART_LSR_BI;
841 /*
842 * Characteres to ignore
843 */
844 up->port.ignore_status_mask = 0;
845 if (iflag & IGNPAR)
846 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
847 if (iflag & IGNBRK) {
848 up->port.ignore_status_mask |= UART_LSR_BI;
849 /*
850 * If we're ignoring parity and break indicators,
851 * ignore overruns too (for real raw support).
852 */
853 if (iflag & IGNPAR)
854 up->port.ignore_status_mask |= UART_LSR_OE;
855 }
857 /*
858 * ignore all characters if CREAD is not set
859 */
860 if ((cflag & CREAD) == 0)
861 up->port.ignore_status_mask |= UART_LSR_DR;
863 /*
864 * CTS flow control flag and modem status interrupts
865 */
866 up->ier &= ~UART_IER_MSI;
867 if (UART_ENABLE_MS(&up->port, cflag))
868 up->ier |= UART_IER_MSI;
870 serial_out(up, UART_IER, up->ier);
872 if (uart_config[up->port.type].flags & UART_STARTECH) {
873 serial_outp(up, UART_LCR, 0xBF);
874 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
875 }
876 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
877 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
878 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
879 if (up->port.type == PORT_16750)
880 serial_outp(up, UART_FCR, fcr); /* set fcr */
881 serial_outp(up, UART_LCR, cval); /* reset DLAB */
882 up->lcr = cval; /* Save LCR */
883 if (up->port.type != PORT_16750) {
884 if (fcr & UART_FCR_ENABLE_FIFO) {
885 /* emulated UARTs (Lucent Venus 167x) need two steps */
886 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
887 }
888 serial_outp(up, UART_FCR, fcr); /* set fcr */
889 }
891 up->cflag = cflag;
893 spin_unlock_irqrestore(&up->port.lock, flags);
894 }
896 static void
897 sunsu_set_termios(struct uart_port *port, struct termios *termios,
898 struct termios *old)
899 {
900 unsigned int baud, quot;
902 /*
903 * Ask the core to calculate the divisor for us.
904 */
905 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
906 quot = uart_get_divisor(port, baud);
908 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
909 }
911 static void sunsu_release_port(struct uart_port *port)
912 {
913 }
915 static int sunsu_request_port(struct uart_port *port)
916 {
917 return 0;
918 }
920 static void sunsu_config_port(struct uart_port *port, int flags)
921 {
922 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
924 if (flags & UART_CONFIG_TYPE) {
925 /*
926 * We are supposed to call autoconfig here, but this requires
927 * splitting all the OBP probing crap from the UART probing.
928 * We'll do it when we kill sunsu.c altogether.
929 */
930 port->type = up->type_probed; /* XXX */
931 }
932 }
934 static int
935 sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
936 {
937 return -EINVAL;
938 }
940 static const char *
941 sunsu_type(struct uart_port *port)
942 {
943 int type = port->type;
945 if (type >= ARRAY_SIZE(uart_config))
946 type = 0;
947 return uart_config[type].name;
948 }
950 static struct uart_ops sunsu_pops = {
951 .tx_empty = sunsu_tx_empty,
952 .set_mctrl = sunsu_set_mctrl,
953 .get_mctrl = sunsu_get_mctrl,
954 .stop_tx = sunsu_stop_tx,
955 .start_tx = sunsu_start_tx,
956 .stop_rx = sunsu_stop_rx,
957 .enable_ms = sunsu_enable_ms,
958 .break_ctl = sunsu_break_ctl,
959 .startup = sunsu_startup,
960 .shutdown = sunsu_shutdown,
961 .set_termios = sunsu_set_termios,
962 .type = sunsu_type,
963 .release_port = sunsu_release_port,
964 .request_port = sunsu_request_port,
965 .config_port = sunsu_config_port,
966 .verify_port = sunsu_verify_port,
967 };
969 #define UART_NR 4
971 static struct uart_sunsu_port sunsu_ports[UART_NR];
973 #ifdef CONFIG_SERIO
975 static DEFINE_SPINLOCK(sunsu_serio_lock);
977 static int sunsu_serio_write(struct serio *serio, unsigned char ch)
978 {
979 struct uart_sunsu_port *up = serio->port_data;
980 unsigned long flags;
981 int lsr;
983 spin_lock_irqsave(&sunsu_serio_lock, flags);
985 do {
986 lsr = serial_in(up, UART_LSR);
987 } while (!(lsr & UART_LSR_THRE));
989 /* Send the character out. */
990 serial_out(up, UART_TX, ch);
992 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
994 return 0;
995 }
997 static int sunsu_serio_open(struct serio *serio)
998 {
999 struct uart_sunsu_port *up = serio->port_data;
1000 unsigned long flags;
1001 int ret;
1003 spin_lock_irqsave(&sunsu_serio_lock, flags);
1004 if (!up->serio_open) {
1005 up->serio_open = 1;
1006 ret = 0;
1007 } else
1008 ret = -EBUSY;
1009 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1011 return ret;
1014 static void sunsu_serio_close(struct serio *serio)
1016 struct uart_sunsu_port *up = serio->port_data;
1017 unsigned long flags;
1019 spin_lock_irqsave(&sunsu_serio_lock, flags);
1020 up->serio_open = 0;
1021 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1024 #endif /* CONFIG_SERIO */
1026 static void sunsu_autoconfig(struct uart_sunsu_port *up)
1028 unsigned char status1, status2, scratch, scratch2, scratch3;
1029 unsigned char save_lcr, save_mcr;
1030 unsigned long flags;
1032 if (up->su_type == SU_PORT_NONE)
1033 return;
1035 up->type_probed = PORT_UNKNOWN;
1036 up->port.iotype = UPIO_MEM;
1038 spin_lock_irqsave(&up->port.lock, flags);
1040 if (!(up->port.flags & UPF_BUGGY_UART)) {
1041 /*
1042 * Do a simple existence test first; if we fail this, there's
1043 * no point trying anything else.
1045 * 0x80 is used as a nonsense port to prevent against false
1046 * positives due to ISA bus float. The assumption is that
1047 * 0x80 is a non-existent port; which should be safe since
1048 * include/asm/io.h also makes this assumption.
1049 */
1050 scratch = serial_inp(up, UART_IER);
1051 serial_outp(up, UART_IER, 0);
1052 #ifdef __i386__
1053 outb(0xff, 0x080);
1054 #endif
1055 scratch2 = serial_inp(up, UART_IER);
1056 serial_outp(up, UART_IER, 0x0f);
1057 #ifdef __i386__
1058 outb(0, 0x080);
1059 #endif
1060 scratch3 = serial_inp(up, UART_IER);
1061 serial_outp(up, UART_IER, scratch);
1062 if (scratch2 != 0 || scratch3 != 0x0F)
1063 goto out; /* We failed; there's nothing here */
1066 save_mcr = serial_in(up, UART_MCR);
1067 save_lcr = serial_in(up, UART_LCR);
1069 /*
1070 * Check to see if a UART is really there. Certain broken
1071 * internal modems based on the Rockwell chipset fail this
1072 * test, because they apparently don't implement the loopback
1073 * test mode. So this test is skipped on the COM 1 through
1074 * COM 4 ports. This *should* be safe, since no board
1075 * manufacturer would be stupid enough to design a board
1076 * that conflicts with COM 1-4 --- we hope!
1077 */
1078 if (!(up->port.flags & UPF_SKIP_TEST)) {
1079 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1080 status1 = serial_inp(up, UART_MSR) & 0xF0;
1081 serial_outp(up, UART_MCR, save_mcr);
1082 if (status1 != 0x90)
1083 goto out; /* We failed loopback test */
1085 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1086 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1087 serial_outp(up, UART_LCR, 0);
1088 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 scratch = serial_in(up, UART_IIR) >> 6;
1090 switch (scratch) {
1091 case 0:
1092 up->port.type = PORT_16450;
1093 break;
1094 case 1:
1095 up->port.type = PORT_UNKNOWN;
1096 break;
1097 case 2:
1098 up->port.type = PORT_16550;
1099 break;
1100 case 3:
1101 up->port.type = PORT_16550A;
1102 break;
1104 if (up->port.type == PORT_16550A) {
1105 /* Check for Startech UART's */
1106 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1107 if (serial_in(up, UART_EFR) == 0) {
1108 up->port.type = PORT_16650;
1109 } else {
1110 serial_outp(up, UART_LCR, 0xBF);
1111 if (serial_in(up, UART_EFR) == 0)
1112 up->port.type = PORT_16650V2;
1115 if (up->port.type == PORT_16550A) {
1116 /* Check for TI 16750 */
1117 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1118 serial_outp(up, UART_FCR,
1119 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1120 scratch = serial_in(up, UART_IIR) >> 5;
1121 if (scratch == 7) {
1122 /*
1123 * If this is a 16750, and not a cheap UART
1124 * clone, then it should only go into 64 byte
1125 * mode if the UART_FCR7_64BYTE bit was set
1126 * while UART_LCR_DLAB was latched.
1127 */
1128 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1129 serial_outp(up, UART_LCR, 0);
1130 serial_outp(up, UART_FCR,
1131 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1132 scratch = serial_in(up, UART_IIR) >> 5;
1133 if (scratch == 6)
1134 up->port.type = PORT_16750;
1136 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1138 serial_outp(up, UART_LCR, save_lcr);
1139 if (up->port.type == PORT_16450) {
1140 scratch = serial_in(up, UART_SCR);
1141 serial_outp(up, UART_SCR, 0xa5);
1142 status1 = serial_in(up, UART_SCR);
1143 serial_outp(up, UART_SCR, 0x5a);
1144 status2 = serial_in(up, UART_SCR);
1145 serial_outp(up, UART_SCR, scratch);
1147 if ((status1 != 0xa5) || (status2 != 0x5a))
1148 up->port.type = PORT_8250;
1151 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1153 if (up->port.type == PORT_UNKNOWN)
1154 goto out;
1155 up->type_probed = up->port.type; /* XXX */
1157 /*
1158 * Reset the UART.
1159 */
1160 #ifdef CONFIG_SERIAL_8250_RSA
1161 if (up->port.type == PORT_RSA)
1162 serial_outp(up, UART_RSA_FRR, 0);
1163 #endif
1164 serial_outp(up, UART_MCR, save_mcr);
1165 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1166 UART_FCR_CLEAR_RCVR |
1167 UART_FCR_CLEAR_XMIT));
1168 serial_outp(up, UART_FCR, 0);
1169 (void)serial_in(up, UART_RX);
1170 serial_outp(up, UART_IER, 0);
1172 out:
1173 spin_unlock_irqrestore(&up->port.lock, flags);
1176 static struct uart_driver sunsu_reg = {
1177 .owner = THIS_MODULE,
1178 .driver_name = "serial",
1179 .dev_name = "ttyS",
1180 .major = TTY_MAJOR,
1181 };
1183 static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1185 int quot, baud;
1186 #ifdef CONFIG_SERIO
1187 struct serio *serio;
1188 #endif
1190 if (up->su_type == SU_PORT_KBD) {
1191 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1192 baud = 1200;
1193 } else {
1194 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1195 baud = 4800;
1197 quot = up->port.uartclk / (16 * baud);
1199 sunsu_autoconfig(up);
1200 if (up->port.type == PORT_UNKNOWN)
1201 return -ENODEV;
1203 printk("%s: %s port at %lx, irq %u\n",
1204 to_of_device(up->port.dev)->node->full_name,
1205 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
1206 up->port.mapbase, up->port.irq);
1208 #ifdef CONFIG_SERIO
1209 serio = &up->serio;
1210 serio->port_data = up;
1212 serio->id.type = SERIO_RS232;
1213 if (up->su_type == SU_PORT_KBD) {
1214 serio->id.proto = SERIO_SUNKBD;
1215 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1216 } else {
1217 serio->id.proto = SERIO_SUN;
1218 serio->id.extra = 1;
1219 strlcpy(serio->name, "sums", sizeof(serio->name));
1221 strlcpy(serio->phys,
1222 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1223 sizeof(serio->phys));
1225 serio->write = sunsu_serio_write;
1226 serio->open = sunsu_serio_open;
1227 serio->close = sunsu_serio_close;
1228 serio->dev.parent = up->port.dev;
1230 serio_register_port(serio);
1231 #endif
1233 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1235 sunsu_startup(&up->port);
1236 return 0;
1239 /*
1240 * ------------------------------------------------------------
1241 * Serial console driver
1242 * ------------------------------------------------------------
1243 */
1245 #ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1247 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1249 /*
1250 * Wait for transmitter & holding register to empty
1251 */
1252 static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1254 unsigned int status, tmout = 10000;
1256 /* Wait up to 10ms for the character(s) to be sent. */
1257 do {
1258 status = serial_in(up, UART_LSR);
1260 if (status & UART_LSR_BI)
1261 up->lsr_break_flag = UART_LSR_BI;
1263 if (--tmout == 0)
1264 break;
1265 udelay(1);
1266 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1268 /* Wait up to 1s for flow control if necessary */
1269 if (up->port.flags & UPF_CONS_FLOW) {
1270 tmout = 1000000;
1271 while (--tmout &&
1272 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1273 udelay(1);
1277 static void sunsu_console_putchar(struct uart_port *port, int ch)
1279 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1281 wait_for_xmitr(up);
1282 serial_out(up, UART_TX, ch);
1285 /*
1286 * Print a string to the serial port trying not to disturb
1287 * any possible real use of the port...
1288 */
1289 static void sunsu_console_write(struct console *co, const char *s,
1290 unsigned int count)
1292 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1293 unsigned int ier;
1295 /*
1296 * First save the UER then disable the interrupts
1297 */
1298 ier = serial_in(up, UART_IER);
1299 serial_out(up, UART_IER, 0);
1301 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1303 /*
1304 * Finally, wait for transmitter to become empty
1305 * and restore the IER
1306 */
1307 wait_for_xmitr(up);
1308 serial_out(up, UART_IER, ier);
1311 /*
1312 * Setup initial baud/bits/parity. We do two things here:
1313 * - construct a cflag setting for the first su_open()
1314 * - initialize the serial port
1315 * Return non-zero if we didn't find a serial port.
1316 */
1317 static int sunsu_console_setup(struct console *co, char *options)
1319 struct uart_port *port;
1320 int baud = 9600;
1321 int bits = 8;
1322 int parity = 'n';
1323 int flow = 'n';
1325 printk("Console: ttyS%d (SU)\n",
1326 (sunsu_reg.minor - 64) + co->index);
1328 /*
1329 * Check whether an invalid uart number has been specified, and
1330 * if so, search for the first available port that does have
1331 * console support.
1332 */
1333 if (co->index >= UART_NR)
1334 co->index = 0;
1335 port = &sunsu_ports[co->index].port;
1337 /*
1338 * Temporary fix.
1339 */
1340 spin_lock_init(&port->lock);
1342 if (options)
1343 uart_parse_options(options, &baud, &parity, &bits, &flow);
1345 return uart_set_options(port, co, baud, parity, bits, flow);
1348 static struct console sunsu_cons = {
1349 .name = "ttyS",
1350 .write = sunsu_console_write,
1351 .device = uart_console_device,
1352 .setup = sunsu_console_setup,
1353 .flags = CON_PRINTBUFFER,
1354 .index = -1,
1355 .data = &sunsu_reg,
1356 };
1358 /*
1359 * Register console.
1360 */
1362 static inline struct console *SUNSU_CONSOLE(int num_uart)
1364 int i;
1366 if (con_is_present())
1367 return NULL;
1369 for (i = 0; i < num_uart; i++) {
1370 int this_minor = sunsu_reg.minor + i;
1372 if ((this_minor - 64) == (serial_console - 1))
1373 break;
1375 if (i == num_uart)
1376 return NULL;
1378 sunsu_cons.index = i;
1380 return &sunsu_cons;
1382 #else
1383 #define SUNSU_CONSOLE(num_uart) (NULL)
1384 #define sunsu_serial_console_init() do { } while (0)
1385 #endif
1387 static enum su_type __devinit su_get_type(struct device_node *dp)
1389 struct device_node *ap = of_find_node_by_path("/aliases");
1391 if (ap) {
1392 char *keyb = of_get_property(ap, "keyboard", NULL);
1393 char *ms = of_get_property(ap, "mouse", NULL);
1395 if (keyb) {
1396 if (dp == of_find_node_by_path(keyb))
1397 return SU_PORT_KBD;
1399 if (ms) {
1400 if (dp == of_find_node_by_path(ms))
1401 return SU_PORT_MS;
1405 return SU_PORT_PORT;
1408 static int __devinit su_probe(struct of_device *op, const struct of_device_id *match)
1410 static int inst;
1411 struct device_node *dp = op->node;
1412 struct uart_sunsu_port *up;
1413 struct resource *rp;
1414 enum su_type type;
1415 int err;
1417 type = su_get_type(dp);
1418 if (type == SU_PORT_PORT) {
1419 if (inst >= UART_NR)
1420 return -EINVAL;
1421 up = &sunsu_ports[inst];
1422 } else {
1423 up = kzalloc(sizeof(*up), GFP_KERNEL);
1424 if (!up)
1425 return -ENOMEM;
1428 up->port.line = inst;
1430 spin_lock_init(&up->port.lock);
1432 up->su_type = type;
1434 rp = &op->resource[0];
1435 up->port.mapbase = rp->start;
1436 up->reg_size = (rp->end - rp->start) + 1;
1437 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
1438 if (!up->port.membase) {
1439 if (type != SU_PORT_PORT)
1440 kfree(up);
1441 return -ENOMEM;
1444 up->port.irq = op->irqs[0];
1446 up->port.dev = &op->dev;
1448 up->port.type = PORT_UNKNOWN;
1449 up->port.uartclk = (SU_BASE_BAUD * 16);
1451 err = 0;
1452 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1453 err = sunsu_kbd_ms_init(up);
1454 if (err) {
1455 kfree(up);
1456 goto out_unmap;
1458 dev_set_drvdata(&op->dev, up);
1460 return 0;
1463 up->port.flags |= UPF_BOOT_AUTOCONF;
1465 sunsu_autoconfig(up);
1467 err = -ENODEV;
1468 if (up->port.type == PORT_UNKNOWN)
1469 goto out_unmap;
1471 up->port.ops = &sunsu_pops;
1473 err = uart_add_one_port(&sunsu_reg, &up->port);
1474 if (err)
1475 goto out_unmap;
1477 dev_set_drvdata(&op->dev, up);
1479 inst++;
1481 return 0;
1483 out_unmap:
1484 of_iounmap(up->port.membase, up->reg_size);
1485 return err;
1488 static int __devexit su_remove(struct of_device *dev)
1490 struct uart_sunsu_port *up = dev_get_drvdata(&dev->dev);;
1492 if (up->su_type == SU_PORT_MS ||
1493 up->su_type == SU_PORT_KBD) {
1494 #ifdef CONFIG_SERIO
1495 serio_unregister_port(&up->serio);
1496 #endif
1497 kfree(up);
1498 } else if (up->port.type != PORT_UNKNOWN) {
1499 uart_remove_one_port(&sunsu_reg, &up->port);
1502 dev_set_drvdata(&dev->dev, NULL);
1504 return 0;
1507 static struct of_device_id su_match[] = {
1509 .name = "su",
1510 },
1512 .name = "su_pnp",
1513 },
1515 .name = "serial",
1516 .compatible = "su",
1517 },
1518 {},
1519 };
1520 MODULE_DEVICE_TABLE(of, su_match);
1522 static struct of_platform_driver su_driver = {
1523 .name = "su",
1524 .match_table = su_match,
1525 .probe = su_probe,
1526 .remove = __devexit_p(su_remove),
1527 };
1529 static int num_uart;
1531 static int __init sunsu_init(void)
1533 struct device_node *dp;
1534 int err;
1536 num_uart = 0;
1537 for_each_node_by_name(dp, "su") {
1538 if (su_get_type(dp) == SU_PORT_PORT)
1539 num_uart++;
1541 for_each_node_by_name(dp, "su_pnp") {
1542 if (su_get_type(dp) == SU_PORT_PORT)
1543 num_uart++;
1545 for_each_node_by_name(dp, "serial") {
1546 if (of_device_is_compatible(dp, "su")) {
1547 if (su_get_type(dp) == SU_PORT_PORT)
1548 num_uart++;
1552 if (num_uart) {
1553 sunsu_reg.minor = sunserial_current_minor;
1554 sunsu_reg.nr = num_uart;
1555 err = uart_register_driver(&sunsu_reg);
1556 if (err)
1557 return err;
1558 sunsu_reg.tty_driver->name_base = sunsu_reg.minor - 64;
1559 sunserial_current_minor += num_uart;
1560 sunsu_reg.cons = SUNSU_CONSOLE(num_uart);
1563 err = of_register_driver(&su_driver, &of_bus_type);
1564 if (err && num_uart)
1565 uart_unregister_driver(&sunsu_reg);
1567 return err;
1570 static void __exit sunsu_exit(void)
1572 if (num_uart)
1573 uart_unregister_driver(&sunsu_reg);
1576 module_init(sunsu_init);
1577 module_exit(sunsu_exit);
1579 MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller");
1580 MODULE_DESCRIPTION("Sun SU serial port driver");
1581 MODULE_VERSION("2.0");
1582 MODULE_LICENSE("GPL");