ia64/linux-2.6.18-xen.hg

view drivers/serial/m32r_sio.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
18 /*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
29 #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #define SUPPORT_SYSRQ
31 #endif
33 #include <linux/module.h>
34 #include <linux/tty.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/serial.h>
40 #include <linux/serialP.h>
41 #include <linux/delay.h>
43 #include <asm/m32r.h>
44 #include <asm/io.h>
45 #include <asm/irq.h>
47 #define PORT_M32R_BASE PORT_M32R_SIO
48 #define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
49 #define BAUD_RATE 115200
51 #include <linux/serial_core.h>
52 #include "m32r_sio.h"
53 #include "m32r_sio_reg.h"
55 /*
56 * Debugging.
57 */
58 #if 0
59 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
60 #else
61 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
62 #endif
64 #if 0
65 #define DEBUG_INTR(fmt...) printk(fmt)
66 #else
67 #define DEBUG_INTR(fmt...) do { } while (0)
68 #endif
70 #define PASS_LIMIT 256
72 /*
73 * We default to IRQ0 for the "no irq" hack. Some
74 * machine types want others as well - they're free
75 * to redefine this in their header file.
76 */
77 #define is_real_interrupt(irq) ((irq) != 0)
79 #include <asm/serial.h>
81 /* Standard COM flags */
82 #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
84 /*
85 * SERIAL_PORT_DFNS tells us about built-in ports that have no
86 * standard enumeration mechanism. Platforms that can find all
87 * serial ports via mechanisms like ACPI or PCI need not supply it.
88 */
89 #undef SERIAL_PORT_DFNS
90 #if defined(CONFIG_PLAT_USRV)
92 #define SERIAL_PORT_DFNS \
93 /* UART CLK PORT IRQ FLAGS */ \
94 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
95 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
97 #else /* !CONFIG_PLAT_USRV */
99 #if defined(CONFIG_SERIAL_M32R_PLDSIO)
100 #define SERIAL_PORT_DFNS \
101 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
102 STD_COM_FLAGS }, /* ttyS0 */
103 #else
104 #define SERIAL_PORT_DFNS \
105 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
106 STD_COM_FLAGS }, /* ttyS0 */
107 #endif
109 #endif /* !CONFIG_PLAT_USRV */
111 static struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
115 #define UART_NR ARRAY_SIZE(old_serial_port)
117 struct uart_sio_port {
118 struct uart_port port;
119 struct timer_list timer; /* "no irq" timer */
120 struct list_head list; /* ports on this IRQ */
121 unsigned short rev;
122 unsigned char acr;
123 unsigned char ier;
124 unsigned char lcr;
125 unsigned char mcr_mask; /* mask of user bits */
126 unsigned char mcr_force; /* mask of forced bits */
127 unsigned char lsr_break_flag;
129 /*
130 * We provide a per-port pm hook.
131 */
132 void (*pm)(struct uart_port *port,
133 unsigned int state, unsigned int old);
134 };
136 struct irq_info {
137 spinlock_t lock;
138 struct list_head *head;
139 };
141 static struct irq_info irq_lists[NR_IRQS];
143 /*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146 static const struct serial_uart_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .dfl_xmit_fifo_size = 1,
150 .flags = 0,
151 },
152 [PORT_INDEX(PORT_M32R_SIO)] = {
153 .name = "M32RSIO",
154 .dfl_xmit_fifo_size = 1,
155 .flags = 0,
156 },
157 };
159 #ifdef CONFIG_SERIAL_M32R_PLDSIO
161 #define __sio_in(x) inw((unsigned long)(x))
162 #define __sio_out(v,x) outw((v),(unsigned long)(x))
164 static inline void sio_set_baud_rate(unsigned long baud)
165 {
166 unsigned short sbaud;
167 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
168 __sio_out(sbaud, PLD_ESIO0BAUR);
169 }
171 static void sio_reset(void)
172 {
173 unsigned short tmp;
175 tmp = __sio_in(PLD_ESIO0RXB);
176 tmp = __sio_in(PLD_ESIO0RXB);
177 tmp = __sio_in(PLD_ESIO0CR);
178 sio_set_baud_rate(BAUD_RATE);
179 __sio_out(0x0300, PLD_ESIO0CR);
180 __sio_out(0x0003, PLD_ESIO0CR);
181 }
183 static void sio_init(void)
184 {
185 unsigned short tmp;
187 tmp = __sio_in(PLD_ESIO0RXB);
188 tmp = __sio_in(PLD_ESIO0RXB);
189 tmp = __sio_in(PLD_ESIO0CR);
190 __sio_out(0x0300, PLD_ESIO0CR);
191 __sio_out(0x0003, PLD_ESIO0CR);
192 }
194 static void sio_error(int *status)
195 {
196 printk("SIO0 error[%04x]\n", *status);
197 do {
198 sio_init();
199 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
200 }
202 #else /* not CONFIG_SERIAL_M32R_PLDSIO */
204 #define __sio_in(x) inl(x)
205 #define __sio_out(v,x) outl((v),(x))
207 static inline void sio_set_baud_rate(unsigned long baud)
208 {
209 unsigned long i, j;
211 i = boot_cpu_data.bus_clock / (baud * 16);
212 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
213 i -= 1;
214 j = (j + 1) >> 1;
216 __sio_out(i, M32R_SIO0_BAUR_PORTL);
217 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
218 }
220 static void sio_reset(void)
221 {
222 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
223 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
224 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
225 sio_set_baud_rate(BAUD_RATE);
226 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
227 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
228 }
230 static void sio_init(void)
231 {
232 unsigned int tmp;
234 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
235 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
236 tmp = __sio_in(M32R_SIO0_STS_PORTL);
237 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
238 }
240 static void sio_error(int *status)
241 {
242 printk("SIO0 error[%04x]\n", *status);
243 do {
244 sio_init();
245 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
246 }
248 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
250 static unsigned int sio_in(struct uart_sio_port *up, int offset)
251 {
252 return __sio_in(up->port.iobase + offset);
253 }
255 static void sio_out(struct uart_sio_port *up, int offset, int value)
256 {
257 __sio_out(value, up->port.iobase + offset);
258 }
260 static unsigned int serial_in(struct uart_sio_port *up, int offset)
261 {
262 if (!offset)
263 return 0;
265 return __sio_in(offset);
266 }
268 static void serial_out(struct uart_sio_port *up, int offset, int value)
269 {
270 if (!offset)
271 return;
273 __sio_out(value, offset);
274 }
276 static void m32r_sio_stop_tx(struct uart_port *port)
277 {
278 struct uart_sio_port *up = (struct uart_sio_port *)port;
280 if (up->ier & UART_IER_THRI) {
281 up->ier &= ~UART_IER_THRI;
282 serial_out(up, UART_IER, up->ier);
283 }
284 }
286 static void m32r_sio_start_tx(struct uart_port *port)
287 {
288 #ifdef CONFIG_SERIAL_M32R_PLDSIO
289 struct uart_sio_port *up = (struct uart_sio_port *)port;
290 struct circ_buf *xmit = &up->port.info->xmit;
292 if (!(up->ier & UART_IER_THRI)) {
293 up->ier |= UART_IER_THRI;
294 serial_out(up, UART_IER, up->ier);
295 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
296 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
297 up->port.icount.tx++;
298 }
299 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
300 #else
301 struct uart_sio_port *up = (struct uart_sio_port *)port;
303 if (!(up->ier & UART_IER_THRI)) {
304 up->ier |= UART_IER_THRI;
305 serial_out(up, UART_IER, up->ier);
306 }
307 #endif
308 }
310 static void m32r_sio_stop_rx(struct uart_port *port)
311 {
312 struct uart_sio_port *up = (struct uart_sio_port *)port;
314 up->ier &= ~UART_IER_RLSI;
315 up->port.read_status_mask &= ~UART_LSR_DR;
316 serial_out(up, UART_IER, up->ier);
317 }
319 static void m32r_sio_enable_ms(struct uart_port *port)
320 {
321 struct uart_sio_port *up = (struct uart_sio_port *)port;
323 up->ier |= UART_IER_MSI;
324 serial_out(up, UART_IER, up->ier);
325 }
327 static void receive_chars(struct uart_sio_port *up, int *status,
328 struct pt_regs *regs)
329 {
330 struct tty_struct *tty = up->port.info->tty;
331 unsigned char ch;
332 unsigned char flag;
333 int max_count = 256;
335 do {
336 ch = sio_in(up, SIORXB);
337 flag = TTY_NORMAL;
338 up->port.icount.rx++;
340 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
341 UART_LSR_FE | UART_LSR_OE))) {
342 /*
343 * For statistics only
344 */
345 if (*status & UART_LSR_BI) {
346 *status &= ~(UART_LSR_FE | UART_LSR_PE);
347 up->port.icount.brk++;
348 /*
349 * We do the SysRQ and SAK checking
350 * here because otherwise the break
351 * may get masked by ignore_status_mask
352 * or read_status_mask.
353 */
354 if (uart_handle_break(&up->port))
355 goto ignore_char;
356 } else if (*status & UART_LSR_PE)
357 up->port.icount.parity++;
358 else if (*status & UART_LSR_FE)
359 up->port.icount.frame++;
360 if (*status & UART_LSR_OE)
361 up->port.icount.overrun++;
363 /*
364 * Mask off conditions which should be ingored.
365 */
366 *status &= up->port.read_status_mask;
368 if (up->port.line == up->port.cons->index) {
369 /* Recover the break flag from console xmit */
370 *status |= up->lsr_break_flag;
371 up->lsr_break_flag = 0;
372 }
374 if (*status & UART_LSR_BI) {
375 DEBUG_INTR("handling break....");
376 flag = TTY_BREAK;
377 } else if (*status & UART_LSR_PE)
378 flag = TTY_PARITY;
379 else if (*status & UART_LSR_FE)
380 flag = TTY_FRAME;
381 }
382 if (uart_handle_sysrq_char(&up->port, ch, regs))
383 goto ignore_char;
384 if ((*status & up->port.ignore_status_mask) == 0)
385 tty_insert_flip_char(tty, ch, flag);
387 if (*status & UART_LSR_OE) {
388 /*
389 * Overrun is special, since it's reported
390 * immediately, and doesn't affect the current
391 * character.
392 */
393 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
394 }
395 ignore_char:
396 *status = serial_in(up, UART_LSR);
397 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
398 tty_flip_buffer_push(tty);
399 }
401 static void transmit_chars(struct uart_sio_port *up)
402 {
403 struct circ_buf *xmit = &up->port.info->xmit;
404 int count;
406 if (up->port.x_char) {
407 #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
408 serial_out(up, UART_TX, up->port.x_char);
409 #endif
410 up->port.icount.tx++;
411 up->port.x_char = 0;
412 return;
413 }
414 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
415 m32r_sio_stop_tx(&up->port);
416 return;
417 }
419 count = up->port.fifosize;
420 do {
421 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
422 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
423 up->port.icount.tx++;
424 if (uart_circ_empty(xmit))
425 break;
426 while (!serial_in(up, UART_LSR) & UART_LSR_THRE);
428 } while (--count > 0);
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&up->port);
433 DEBUG_INTR("THRE...");
435 if (uart_circ_empty(xmit))
436 m32r_sio_stop_tx(&up->port);
437 }
439 /*
440 * This handles the interrupt from one port.
441 */
442 static inline void m32r_sio_handle_port(struct uart_sio_port *up,
443 unsigned int status, struct pt_regs *regs)
444 {
445 DEBUG_INTR("status = %x...", status);
447 if (status & 0x04)
448 receive_chars(up, &status, regs);
449 if (status & 0x01)
450 transmit_chars(up);
451 }
453 /*
454 * This is the serial driver's interrupt routine.
455 *
456 * Arjan thinks the old way was overly complex, so it got simplified.
457 * Alan disagrees, saying that need the complexity to handle the weird
458 * nature of ISA shared interrupts. (This is a special exception.)
459 *
460 * In order to handle ISA shared interrupts properly, we need to check
461 * that all ports have been serviced, and therefore the ISA interrupt
462 * line has been de-asserted.
463 *
464 * This means we need to loop through all ports. checking that they
465 * don't have an interrupt pending.
466 */
467 static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id,
468 struct pt_regs *regs)
469 {
470 struct irq_info *i = dev_id;
471 struct list_head *l, *end = NULL;
472 int pass_counter = 0;
474 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
476 #ifdef CONFIG_SERIAL_M32R_PLDSIO
477 // if (irq == PLD_IRQ_SIO0_SND)
478 // irq = PLD_IRQ_SIO0_RCV;
479 #else
480 if (irq == M32R_IRQ_SIO0_S)
481 irq = M32R_IRQ_SIO0_R;
482 #endif
484 spin_lock(&i->lock);
486 l = i->head;
487 do {
488 struct uart_sio_port *up;
489 unsigned int sts;
491 up = list_entry(l, struct uart_sio_port, list);
493 sts = sio_in(up, SIOSTS);
494 if (sts & 0x5) {
495 spin_lock(&up->port.lock);
496 m32r_sio_handle_port(up, sts, regs);
497 spin_unlock(&up->port.lock);
499 end = NULL;
500 } else if (end == NULL)
501 end = l;
503 l = l->next;
505 if (l == i->head && pass_counter++ > PASS_LIMIT) {
506 if (sts & 0xe0)
507 sio_error(&sts);
508 break;
509 }
510 } while (l != end);
512 spin_unlock(&i->lock);
514 DEBUG_INTR("end.\n");
516 return IRQ_HANDLED;
517 }
519 /*
520 * To support ISA shared interrupts, we need to have one interrupt
521 * handler that ensures that the IRQ line has been deasserted
522 * before returning. Failing to do this will result in the IRQ
523 * line being stuck active, and, since ISA irqs are edge triggered,
524 * no more IRQs will be seen.
525 */
526 static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
527 {
528 spin_lock_irq(&i->lock);
530 if (!list_empty(i->head)) {
531 if (i->head == &up->list)
532 i->head = i->head->next;
533 list_del(&up->list);
534 } else {
535 BUG_ON(i->head != &up->list);
536 i->head = NULL;
537 }
539 spin_unlock_irq(&i->lock);
540 }
542 static int serial_link_irq_chain(struct uart_sio_port *up)
543 {
544 struct irq_info *i = irq_lists + up->port.irq;
545 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
547 spin_lock_irq(&i->lock);
549 if (i->head) {
550 list_add(&up->list, i->head);
551 spin_unlock_irq(&i->lock);
553 ret = 0;
554 } else {
555 INIT_LIST_HEAD(&up->list);
556 i->head = &up->list;
557 spin_unlock_irq(&i->lock);
559 ret = request_irq(up->port.irq, m32r_sio_interrupt,
560 irq_flags, "SIO0-RX", i);
561 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
562 irq_flags, "SIO0-TX", i);
563 if (ret < 0)
564 serial_do_unlink(i, up);
565 }
567 return ret;
568 }
570 static void serial_unlink_irq_chain(struct uart_sio_port *up)
571 {
572 struct irq_info *i = irq_lists + up->port.irq;
574 BUG_ON(i->head == NULL);
576 if (list_empty(i->head)) {
577 free_irq(up->port.irq, i);
578 free_irq(up->port.irq + 1, i);
579 }
581 serial_do_unlink(i, up);
582 }
584 /*
585 * This function is used to handle ports that do not have an interrupt.
586 */
587 static void m32r_sio_timeout(unsigned long data)
588 {
589 struct uart_sio_port *up = (struct uart_sio_port *)data;
590 unsigned int timeout;
591 unsigned int sts;
593 sts = sio_in(up, SIOSTS);
594 if (sts & 0x5) {
595 spin_lock(&up->port.lock);
596 m32r_sio_handle_port(up, sts, NULL);
597 spin_unlock(&up->port.lock);
598 }
600 timeout = up->port.timeout;
601 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
602 mod_timer(&up->timer, jiffies + timeout);
603 }
605 static unsigned int m32r_sio_tx_empty(struct uart_port *port)
606 {
607 struct uart_sio_port *up = (struct uart_sio_port *)port;
608 unsigned long flags;
609 unsigned int ret;
611 spin_lock_irqsave(&up->port.lock, flags);
612 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
613 spin_unlock_irqrestore(&up->port.lock, flags);
615 return ret;
616 }
618 static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
619 {
620 return 0;
621 }
623 static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
624 {
626 }
628 static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
629 {
631 }
633 static int m32r_sio_startup(struct uart_port *port)
634 {
635 struct uart_sio_port *up = (struct uart_sio_port *)port;
636 int retval;
638 sio_init();
640 /*
641 * If the "interrupt" for this port doesn't correspond with any
642 * hardware interrupt, we use a timer-based system. The original
643 * driver used to do this with IRQ0.
644 */
645 if (!is_real_interrupt(up->port.irq)) {
646 unsigned int timeout = up->port.timeout;
648 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
650 up->timer.data = (unsigned long)up;
651 mod_timer(&up->timer, jiffies + timeout);
652 } else {
653 retval = serial_link_irq_chain(up);
654 if (retval)
655 return retval;
656 }
658 /*
659 * Finally, enable interrupts. Note: Modem status interrupts
660 * are set via set_termios(), which will be occurring imminently
661 * anyway, so we don't enable them here.
662 * - M32R_SIO: 0x0c
663 * - M32R_PLDSIO: 0x04
664 */
665 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
666 sio_out(up, SIOTRCR, up->ier);
668 /*
669 * And clear the interrupt registers again for luck.
670 */
671 sio_reset();
673 return 0;
674 }
676 static void m32r_sio_shutdown(struct uart_port *port)
677 {
678 struct uart_sio_port *up = (struct uart_sio_port *)port;
680 /*
681 * Disable interrupts from this port
682 */
683 up->ier = 0;
684 sio_out(up, SIOTRCR, 0);
686 /*
687 * Disable break condition and FIFOs
688 */
690 sio_init();
692 if (!is_real_interrupt(up->port.irq))
693 del_timer_sync(&up->timer);
694 else
695 serial_unlink_irq_chain(up);
696 }
698 static unsigned int m32r_sio_get_divisor(struct uart_port *port,
699 unsigned int baud)
700 {
701 return uart_get_divisor(port, baud);
702 }
704 static void m32r_sio_set_termios(struct uart_port *port,
705 struct termios *termios, struct termios *old)
706 {
707 struct uart_sio_port *up = (struct uart_sio_port *)port;
708 unsigned char cval = 0;
709 unsigned long flags;
710 unsigned int baud, quot;
712 switch (termios->c_cflag & CSIZE) {
713 case CS5:
714 cval = UART_LCR_WLEN5;
715 break;
716 case CS6:
717 cval = UART_LCR_WLEN6;
718 break;
719 case CS7:
720 cval = UART_LCR_WLEN7;
721 break;
722 default:
723 case CS8:
724 cval = UART_LCR_WLEN8;
725 break;
726 }
728 if (termios->c_cflag & CSTOPB)
729 cval |= UART_LCR_STOP;
730 if (termios->c_cflag & PARENB)
731 cval |= UART_LCR_PARITY;
732 if (!(termios->c_cflag & PARODD))
733 cval |= UART_LCR_EPAR;
734 #ifdef CMSPAR
735 if (termios->c_cflag & CMSPAR)
736 cval |= UART_LCR_SPAR;
737 #endif
739 /*
740 * Ask the core to calculate the divisor for us.
741 */
742 #ifdef CONFIG_SERIAL_M32R_PLDSIO
743 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
744 #else
745 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
746 #endif
747 quot = m32r_sio_get_divisor(port, baud);
749 /*
750 * Ok, we're now changing the port state. Do it with
751 * interrupts disabled.
752 */
753 spin_lock_irqsave(&up->port.lock, flags);
755 sio_set_baud_rate(baud);
757 /*
758 * Update the per-port timeout.
759 */
760 uart_update_timeout(port, termios->c_cflag, baud);
762 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
763 if (termios->c_iflag & INPCK)
764 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
765 if (termios->c_iflag & (BRKINT | PARMRK))
766 up->port.read_status_mask |= UART_LSR_BI;
768 /*
769 * Characteres to ignore
770 */
771 up->port.ignore_status_mask = 0;
772 if (termios->c_iflag & IGNPAR)
773 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
774 if (termios->c_iflag & IGNBRK) {
775 up->port.ignore_status_mask |= UART_LSR_BI;
776 /*
777 * If we're ignoring parity and break indicators,
778 * ignore overruns too (for real raw support).
779 */
780 if (termios->c_iflag & IGNPAR)
781 up->port.ignore_status_mask |= UART_LSR_OE;
782 }
784 /*
785 * ignore all characters if CREAD is not set
786 */
787 if ((termios->c_cflag & CREAD) == 0)
788 up->port.ignore_status_mask |= UART_LSR_DR;
790 /*
791 * CTS flow control flag and modem status interrupts
792 */
793 up->ier &= ~UART_IER_MSI;
794 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
795 up->ier |= UART_IER_MSI;
797 serial_out(up, UART_IER, up->ier);
799 up->lcr = cval; /* Save LCR */
800 spin_unlock_irqrestore(&up->port.lock, flags);
801 }
803 static void m32r_sio_pm(struct uart_port *port, unsigned int state,
804 unsigned int oldstate)
805 {
806 struct uart_sio_port *up = (struct uart_sio_port *)port;
808 if (up->pm)
809 up->pm(port, state, oldstate);
810 }
812 /*
813 * Resource handling. This is complicated by the fact that resources
814 * depend on the port type. Maybe we should be claiming the standard
815 * 8250 ports, and then trying to get other resources as necessary?
816 */
817 static int
818 m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
819 {
820 unsigned int size = 8 << up->port.regshift;
821 #ifndef CONFIG_SERIAL_M32R_PLDSIO
822 unsigned long start;
823 #endif
824 int ret = 0;
826 switch (up->port.iotype) {
827 case UPIO_MEM:
828 if (up->port.mapbase) {
829 #ifdef CONFIG_SERIAL_M32R_PLDSIO
830 *res = request_mem_region(up->port.mapbase, size, "serial");
831 #else
832 start = up->port.mapbase;
833 *res = request_mem_region(start, size, "serial");
834 #endif
835 if (!*res)
836 ret = -EBUSY;
837 }
838 break;
840 case UPIO_PORT:
841 *res = request_region(up->port.iobase, size, "serial");
842 if (!*res)
843 ret = -EBUSY;
844 break;
845 }
846 return ret;
847 }
849 static void m32r_sio_release_port(struct uart_port *port)
850 {
851 struct uart_sio_port *up = (struct uart_sio_port *)port;
852 unsigned long start, offset = 0, size = 0;
854 size <<= up->port.regshift;
856 switch (up->port.iotype) {
857 case UPIO_MEM:
858 if (up->port.mapbase) {
859 /*
860 * Unmap the area.
861 */
862 iounmap(up->port.membase);
863 up->port.membase = NULL;
865 start = up->port.mapbase;
867 if (size)
868 release_mem_region(start + offset, size);
869 release_mem_region(start, 8 << up->port.regshift);
870 }
871 break;
873 case UPIO_PORT:
874 start = up->port.iobase;
876 if (size)
877 release_region(start + offset, size);
878 release_region(start + offset, 8 << up->port.regshift);
879 break;
881 default:
882 break;
883 }
884 }
886 static int m32r_sio_request_port(struct uart_port *port)
887 {
888 struct uart_sio_port *up = (struct uart_sio_port *)port;
889 struct resource *res = NULL;
890 int ret = 0;
892 ret = m32r_sio_request_std_resource(up, &res);
894 /*
895 * If we have a mapbase, then request that as well.
896 */
897 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
898 int size = res->end - res->start + 1;
900 up->port.membase = ioremap(up->port.mapbase, size);
901 if (!up->port.membase)
902 ret = -ENOMEM;
903 }
905 if (ret < 0) {
906 if (res)
907 release_resource(res);
908 }
910 return ret;
911 }
913 static void m32r_sio_config_port(struct uart_port *port, int flags)
914 {
915 struct uart_sio_port *up = (struct uart_sio_port *)port;
917 spin_lock_irqsave(&up->port.lock, flags);
919 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
920 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
922 spin_unlock_irqrestore(&up->port.lock, flags);
923 }
925 static int
926 m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
927 {
928 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
929 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
930 ser->type >= ARRAY_SIZE(uart_config))
931 return -EINVAL;
932 return 0;
933 }
935 static const char *
936 m32r_sio_type(struct uart_port *port)
937 {
938 int type = port->type;
940 if (type >= ARRAY_SIZE(uart_config))
941 type = 0;
942 return uart_config[type].name;
943 }
945 static struct uart_ops m32r_sio_pops = {
946 .tx_empty = m32r_sio_tx_empty,
947 .set_mctrl = m32r_sio_set_mctrl,
948 .get_mctrl = m32r_sio_get_mctrl,
949 .stop_tx = m32r_sio_stop_tx,
950 .start_tx = m32r_sio_start_tx,
951 .stop_rx = m32r_sio_stop_rx,
952 .enable_ms = m32r_sio_enable_ms,
953 .break_ctl = m32r_sio_break_ctl,
954 .startup = m32r_sio_startup,
955 .shutdown = m32r_sio_shutdown,
956 .set_termios = m32r_sio_set_termios,
957 .pm = m32r_sio_pm,
958 .type = m32r_sio_type,
959 .release_port = m32r_sio_release_port,
960 .request_port = m32r_sio_request_port,
961 .config_port = m32r_sio_config_port,
962 .verify_port = m32r_sio_verify_port,
963 };
965 static struct uart_sio_port m32r_sio_ports[UART_NR];
967 static void __init m32r_sio_init_ports(void)
968 {
969 struct uart_sio_port *up;
970 static int first = 1;
971 int i;
973 if (!first)
974 return;
975 first = 0;
977 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
978 i++, up++) {
979 up->port.iobase = old_serial_port[i].port;
980 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
981 up->port.uartclk = old_serial_port[i].baud_base * 16;
982 up->port.flags = old_serial_port[i].flags;
983 up->port.membase = old_serial_port[i].iomem_base;
984 up->port.iotype = old_serial_port[i].io_type;
985 up->port.regshift = old_serial_port[i].iomem_reg_shift;
986 up->port.ops = &m32r_sio_pops;
987 }
988 }
990 static void __init m32r_sio_register_ports(struct uart_driver *drv)
991 {
992 int i;
994 m32r_sio_init_ports();
996 for (i = 0; i < UART_NR; i++) {
997 struct uart_sio_port *up = &m32r_sio_ports[i];
999 up->port.line = i;
1000 up->port.ops = &m32r_sio_pops;
1001 init_timer(&up->timer);
1002 up->timer.function = m32r_sio_timeout;
1004 /*
1005 * ALPHA_KLUDGE_MCR needs to be killed.
1006 */
1007 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
1008 up->mcr_force = ALPHA_KLUDGE_MCR;
1010 uart_add_one_port(drv, &up->port);
1014 #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1016 /*
1017 * Wait for transmitter & holding register to empty
1018 */
1019 static inline void wait_for_xmitr(struct uart_sio_port *up)
1021 unsigned int status, tmout = 10000;
1023 /* Wait up to 10ms for the character(s) to be sent. */
1024 do {
1025 status = sio_in(up, SIOSTS);
1027 if (--tmout == 0)
1028 break;
1029 udelay(1);
1030 } while ((status & UART_EMPTY) != UART_EMPTY);
1032 /* Wait up to 1s for flow control if necessary */
1033 if (up->port.flags & UPF_CONS_FLOW) {
1034 tmout = 1000000;
1035 while (--tmout)
1036 udelay(1);
1040 static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1042 struct uart_sio_port *up = (struct uart_sio_port *)port;
1044 wait_for_xmitr(up);
1045 sio_out(up, SIOTXB, ch);
1048 /*
1049 * Print a string to the serial port trying not to disturb
1050 * any possible real use of the port...
1052 * The console_lock must be held when we get here.
1053 */
1054 static void m32r_sio_console_write(struct console *co, const char *s,
1055 unsigned int count)
1057 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1058 unsigned int ier;
1060 /*
1061 * First save the UER then disable the interrupts
1062 */
1063 ier = sio_in(up, SIOTRCR);
1064 sio_out(up, SIOTRCR, 0);
1066 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1068 /*
1069 * Finally, wait for transmitter to become empty
1070 * and restore the IER
1071 */
1072 wait_for_xmitr(up);
1073 sio_out(up, SIOTRCR, ier);
1076 static int __init m32r_sio_console_setup(struct console *co, char *options)
1078 struct uart_port *port;
1079 int baud = 9600;
1080 int bits = 8;
1081 int parity = 'n';
1082 int flow = 'n';
1084 /*
1085 * Check whether an invalid uart number has been specified, and
1086 * if so, search for the first available port that does have
1087 * console support.
1088 */
1089 if (co->index >= UART_NR)
1090 co->index = 0;
1091 port = &m32r_sio_ports[co->index].port;
1093 /*
1094 * Temporary fix.
1095 */
1096 spin_lock_init(&port->lock);
1098 if (options)
1099 uart_parse_options(options, &baud, &parity, &bits, &flow);
1101 return uart_set_options(port, co, baud, parity, bits, flow);
1104 static struct uart_driver m32r_sio_reg;
1105 static struct console m32r_sio_console = {
1106 .name = "ttyS",
1107 .write = m32r_sio_console_write,
1108 .device = uart_console_device,
1109 .setup = m32r_sio_console_setup,
1110 .flags = CON_PRINTBUFFER,
1111 .index = -1,
1112 .data = &m32r_sio_reg,
1113 };
1115 static int __init m32r_sio_console_init(void)
1117 sio_reset();
1118 sio_init();
1119 m32r_sio_init_ports();
1120 register_console(&m32r_sio_console);
1121 return 0;
1123 console_initcall(m32r_sio_console_init);
1125 #define M32R_SIO_CONSOLE &m32r_sio_console
1126 #else
1127 #define M32R_SIO_CONSOLE NULL
1128 #endif
1130 static struct uart_driver m32r_sio_reg = {
1131 .owner = THIS_MODULE,
1132 .driver_name = "sio",
1133 .dev_name = "ttyS",
1134 .major = TTY_MAJOR,
1135 .minor = 64,
1136 .nr = UART_NR,
1137 .cons = M32R_SIO_CONSOLE,
1138 };
1140 /**
1141 * m32r_sio_suspend_port - suspend one serial port
1142 * @line: serial line number
1144 * Suspend one serial port.
1145 */
1146 void m32r_sio_suspend_port(int line)
1148 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1151 /**
1152 * m32r_sio_resume_port - resume one serial port
1153 * @line: serial line number
1155 * Resume one serial port.
1156 */
1157 void m32r_sio_resume_port(int line)
1159 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1162 static int __init m32r_sio_init(void)
1164 int ret, i;
1166 printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.11 $ ");
1168 for (i = 0; i < NR_IRQS; i++)
1169 spin_lock_init(&irq_lists[i].lock);
1171 ret = uart_register_driver(&m32r_sio_reg);
1172 if (ret >= 0)
1173 m32r_sio_register_ports(&m32r_sio_reg);
1175 return ret;
1178 static void __exit m32r_sio_exit(void)
1180 int i;
1182 for (i = 0; i < UART_NR; i++)
1183 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1185 uart_unregister_driver(&m32r_sio_reg);
1188 module_init(m32r_sio_init);
1189 module_exit(m32r_sio_exit);
1191 EXPORT_SYMBOL(m32r_sio_suspend_port);
1192 EXPORT_SYMBOL(m32r_sio_resume_port);
1194 MODULE_LICENSE("GPL");
1195 MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.11 $");