ia64/linux-2.6.18-xen.hg

view drivers/serial/ip22zilog.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/major.h>
23 #include <linux/string.h>
24 #include <linux/ptrace.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #include <linux/init.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/sgialib.h>
37 #include <asm/sgi/ioc.h>
38 #include <asm/sgi/hpc3.h>
39 #include <asm/sgi/ip22.h>
41 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42 #define SUPPORT_SYSRQ
43 #endif
45 #include <linux/serial_core.h>
47 #include "ip22zilog.h"
49 void ip22_do_break(void);
51 /*
52 * On IP22 we need to delay after register accesses but we do not need to
53 * flush writes.
54 */
55 #define ZSDELAY() udelay(5)
56 #define ZSDELAY_LONG() udelay(20)
57 #define ZS_WSYNC(channel) do { } while (0)
59 #define NUM_IP22ZILOG 1
60 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
62 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */
63 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
65 /*
66 * We wrap our port structure around the generic uart_port.
67 */
68 struct uart_ip22zilog_port {
69 struct uart_port port;
71 /* IRQ servicing chain. */
72 struct uart_ip22zilog_port *next;
74 /* Current values of Zilog write registers. */
75 unsigned char curregs[NUM_ZSREGS];
77 unsigned int flags;
78 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
79 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
80 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
81 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
82 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
83 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
84 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
86 unsigned int cflag;
88 /* L1-A keyboard break state. */
89 int kbd_id;
90 int l1_down;
92 unsigned char parity_mask;
93 unsigned char prev_status;
94 };
96 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
97 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
98 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
99 (UART_ZILOG(PORT)->curregs[REGNUM])
100 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
101 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
102 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
103 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
104 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
105 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
106 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
107 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
108 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
110 /* Reading and writing Zilog8530 registers. The delays are to make this
111 * driver work on the IP22 which needs a settling delay after each chip
112 * register access, other machines handle this in hardware via auxiliary
113 * flip-flops which implement the settle time we do in software.
114 *
115 * The port lock must be held and local IRQs must be disabled
116 * when {read,write}_zsreg is invoked.
117 */
118 static unsigned char read_zsreg(struct zilog_channel *channel,
119 unsigned char reg)
120 {
121 unsigned char retval;
123 writeb(reg, &channel->control);
124 ZSDELAY();
125 retval = readb(&channel->control);
126 ZSDELAY();
128 return retval;
129 }
131 static void write_zsreg(struct zilog_channel *channel,
132 unsigned char reg, unsigned char value)
133 {
134 writeb(reg, &channel->control);
135 ZSDELAY();
136 writeb(value, &channel->control);
137 ZSDELAY();
138 }
140 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
141 {
142 int i;
144 for (i = 0; i < 32; i++) {
145 unsigned char regval;
147 regval = readb(&channel->control);
148 ZSDELAY();
149 if (regval & Rx_CH_AV)
150 break;
152 regval = read_zsreg(channel, R1);
153 readb(&channel->data);
154 ZSDELAY();
156 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
157 writeb(ERR_RES, &channel->control);
158 ZSDELAY();
159 ZS_WSYNC(channel);
160 }
161 }
162 }
164 /* This function must only be called when the TX is not busy. The UART
165 * port lock must be held and local interrupts disabled.
166 */
167 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
168 {
169 int i;
171 /* Let pending transmits finish. */
172 for (i = 0; i < 1000; i++) {
173 unsigned char stat = read_zsreg(channel, R1);
174 if (stat & ALL_SNT)
175 break;
176 udelay(100);
177 }
179 writeb(ERR_RES, &channel->control);
180 ZSDELAY();
181 ZS_WSYNC(channel);
183 ip22zilog_clear_fifo(channel);
185 /* Disable all interrupts. */
186 write_zsreg(channel, R1,
187 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
189 /* Set parity, sync config, stop bits, and clock divisor. */
190 write_zsreg(channel, R4, regs[R4]);
192 /* Set misc. TX/RX control bits. */
193 write_zsreg(channel, R10, regs[R10]);
195 /* Set TX/RX controls sans the enable bits. */
196 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
197 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
199 /* Synchronous mode config. */
200 write_zsreg(channel, R6, regs[R6]);
201 write_zsreg(channel, R7, regs[R7]);
203 /* Don't mess with the interrupt vector (R2, unused by us) and
204 * master interrupt control (R9). We make sure this is setup
205 * properly at probe time then never touch it again.
206 */
208 /* Disable baud generator. */
209 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
211 /* Clock mode control. */
212 write_zsreg(channel, R11, regs[R11]);
214 /* Lower and upper byte of baud rate generator divisor. */
215 write_zsreg(channel, R12, regs[R12]);
216 write_zsreg(channel, R13, regs[R13]);
218 /* Now rewrite R14, with BRENAB (if set). */
219 write_zsreg(channel, R14, regs[R14]);
221 /* External status interrupt control. */
222 write_zsreg(channel, R15, regs[R15]);
224 /* Reset external status interrupts. */
225 write_zsreg(channel, R0, RES_EXT_INT);
226 write_zsreg(channel, R0, RES_EXT_INT);
228 /* Rewrite R3/R5, this time without enables masked. */
229 write_zsreg(channel, R3, regs[R3]);
230 write_zsreg(channel, R5, regs[R5]);
232 /* Rewrite R1, this time without IRQ enabled masked. */
233 write_zsreg(channel, R1, regs[R1]);
234 }
236 /* Reprogram the Zilog channel HW registers with the copies found in the
237 * software state struct. If the transmitter is busy, we defer this update
238 * until the next TX complete interrupt. Else, we do it right now.
239 *
240 * The UART port lock must be held and local interrupts disabled.
241 */
242 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
243 struct zilog_channel *channel)
244 {
245 if (!ZS_REGS_HELD(up)) {
246 if (ZS_TX_ACTIVE(up)) {
247 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
248 } else {
249 __load_zsregs(channel, up->curregs);
250 }
251 }
252 }
254 static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
255 struct zilog_channel *channel,
256 struct pt_regs *regs)
257 {
258 struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */
260 while (1) {
261 unsigned char ch, r1, flag;
263 r1 = read_zsreg(channel, R1);
264 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
265 writeb(ERR_RES, &channel->control);
266 ZSDELAY();
267 ZS_WSYNC(channel);
268 }
270 ch = readb(&channel->control);
271 ZSDELAY();
273 /* This funny hack depends upon BRK_ABRT not interfering
274 * with the other bits we care about in R1.
275 */
276 if (ch & BRK_ABRT)
277 r1 |= BRK_ABRT;
279 ch = readb(&channel->data);
280 ZSDELAY();
282 ch &= up->parity_mask;
284 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) {
285 /* Wait for BREAK to deassert to avoid potentially
286 * confusing the PROM.
287 */
288 while (1) {
289 ch = readb(&channel->control);
290 ZSDELAY();
291 if (!(ch & BRK_ABRT))
292 break;
293 }
294 ip22_do_break();
295 return;
296 }
298 /* A real serial line, record the character and status. */
299 flag = TTY_NORMAL;
300 up->port.icount.rx++;
301 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
302 if (r1 & BRK_ABRT) {
303 r1 &= ~(PAR_ERR | CRC_ERR);
304 up->port.icount.brk++;
305 if (uart_handle_break(&up->port))
306 goto next_char;
307 }
308 else if (r1 & PAR_ERR)
309 up->port.icount.parity++;
310 else if (r1 & CRC_ERR)
311 up->port.icount.frame++;
312 if (r1 & Rx_OVR)
313 up->port.icount.overrun++;
314 r1 &= up->port.read_status_mask;
315 if (r1 & BRK_ABRT)
316 flag = TTY_BREAK;
317 else if (r1 & PAR_ERR)
318 flag = TTY_PARITY;
319 else if (r1 & CRC_ERR)
320 flag = TTY_FRAME;
321 }
322 if (uart_handle_sysrq_char(&up->port, ch, regs))
323 goto next_char;
325 if (up->port.ignore_status_mask == 0xff ||
326 (r1 & up->port.ignore_status_mask) == 0)
327 tty_insert_flip_char(tty, ch, flag);
329 if (r1 & Rx_OVR)
330 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
331 next_char:
332 ch = readb(&channel->control);
333 ZSDELAY();
334 if (!(ch & Rx_CH_AV))
335 break;
336 }
338 tty_flip_buffer_push(tty);
339 }
341 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
342 struct zilog_channel *channel,
343 struct pt_regs *regs)
344 {
345 unsigned char status;
347 status = readb(&channel->control);
348 ZSDELAY();
350 writeb(RES_EXT_INT, &channel->control);
351 ZSDELAY();
352 ZS_WSYNC(channel);
354 if (ZS_WANTS_MODEM_STATUS(up)) {
355 if (status & SYNC)
356 up->port.icount.dsr++;
358 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
359 * But it does not tell us which bit has changed, we have to keep
360 * track of this ourselves.
361 */
362 if ((status & DCD) ^ up->prev_status)
363 uart_handle_dcd_change(&up->port,
364 (status & DCD));
365 if ((status & CTS) ^ up->prev_status)
366 uart_handle_cts_change(&up->port,
367 (status & CTS));
369 wake_up_interruptible(&up->port.info->delta_msr_wait);
370 }
372 up->prev_status = status;
373 }
375 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
376 struct zilog_channel *channel)
377 {
378 struct circ_buf *xmit;
380 if (ZS_IS_CONS(up)) {
381 unsigned char status = readb(&channel->control);
382 ZSDELAY();
384 /* TX still busy? Just wait for the next TX done interrupt.
385 *
386 * It can occur because of how we do serial console writes. It would
387 * be nice to transmit console writes just like we normally would for
388 * a TTY line. (ie. buffered and TX interrupt driven). That is not
389 * easy because console writes cannot sleep. One solution might be
390 * to poll on enough port->xmit space becomming free. -DaveM
391 */
392 if (!(status & Tx_BUF_EMP))
393 return;
394 }
396 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
398 if (ZS_REGS_HELD(up)) {
399 __load_zsregs(channel, up->curregs);
400 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
401 }
403 if (ZS_TX_STOPPED(up)) {
404 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
405 goto ack_tx_int;
406 }
408 if (up->port.x_char) {
409 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
410 writeb(up->port.x_char, &channel->data);
411 ZSDELAY();
412 ZS_WSYNC(channel);
414 up->port.icount.tx++;
415 up->port.x_char = 0;
416 return;
417 }
419 if (up->port.info == NULL)
420 goto ack_tx_int;
421 xmit = &up->port.info->xmit;
422 if (uart_circ_empty(xmit))
423 goto ack_tx_int;
424 if (uart_tx_stopped(&up->port))
425 goto ack_tx_int;
427 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
428 writeb(xmit->buf[xmit->tail], &channel->data);
429 ZSDELAY();
430 ZS_WSYNC(channel);
432 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
433 up->port.icount.tx++;
435 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
436 uart_write_wakeup(&up->port);
438 return;
440 ack_tx_int:
441 writeb(RES_Tx_P, &channel->control);
442 ZSDELAY();
443 ZS_WSYNC(channel);
444 }
446 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
447 {
448 struct uart_ip22zilog_port *up = dev_id;
450 while (up) {
451 struct zilog_channel *channel
452 = ZILOG_CHANNEL_FROM_PORT(&up->port);
453 unsigned char r3;
455 spin_lock(&up->port.lock);
456 r3 = read_zsreg(channel, R3);
458 /* Channel A */
459 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
460 writeb(RES_H_IUS, &channel->control);
461 ZSDELAY();
462 ZS_WSYNC(channel);
464 if (r3 & CHARxIP)
465 ip22zilog_receive_chars(up, channel, regs);
466 if (r3 & CHAEXT)
467 ip22zilog_status_handle(up, channel, regs);
468 if (r3 & CHATxIP)
469 ip22zilog_transmit_chars(up, channel);
470 }
471 spin_unlock(&up->port.lock);
473 /* Channel B */
474 up = up->next;
475 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
477 spin_lock(&up->port.lock);
478 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
479 writeb(RES_H_IUS, &channel->control);
480 ZSDELAY();
481 ZS_WSYNC(channel);
483 if (r3 & CHBRxIP)
484 ip22zilog_receive_chars(up, channel, regs);
485 if (r3 & CHBEXT)
486 ip22zilog_status_handle(up, channel, regs);
487 if (r3 & CHBTxIP)
488 ip22zilog_transmit_chars(up, channel);
489 }
490 spin_unlock(&up->port.lock);
492 up = up->next;
493 }
495 return IRQ_HANDLED;
496 }
498 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
499 * port lock, it is acquired here.
500 */
501 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
502 {
503 struct zilog_channel *channel;
504 unsigned char status;
506 channel = ZILOG_CHANNEL_FROM_PORT(port);
507 status = readb(&channel->control);
508 ZSDELAY();
510 return status;
511 }
513 /* The port lock is not held. */
514 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
515 {
516 unsigned long flags;
517 unsigned char status;
518 unsigned int ret;
520 spin_lock_irqsave(&port->lock, flags);
522 status = ip22zilog_read_channel_status(port);
524 spin_unlock_irqrestore(&port->lock, flags);
526 if (status & Tx_BUF_EMP)
527 ret = TIOCSER_TEMT;
528 else
529 ret = 0;
531 return ret;
532 }
534 /* The port lock is held and interrupts are disabled. */
535 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
536 {
537 unsigned char status;
538 unsigned int ret;
540 status = ip22zilog_read_channel_status(port);
542 ret = 0;
543 if (status & DCD)
544 ret |= TIOCM_CAR;
545 if (status & SYNC)
546 ret |= TIOCM_DSR;
547 if (status & CTS)
548 ret |= TIOCM_CTS;
550 return ret;
551 }
553 /* The port lock is held and interrupts are disabled. */
554 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
555 {
556 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
557 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
558 unsigned char set_bits, clear_bits;
560 set_bits = clear_bits = 0;
562 if (mctrl & TIOCM_RTS)
563 set_bits |= RTS;
564 else
565 clear_bits |= RTS;
566 if (mctrl & TIOCM_DTR)
567 set_bits |= DTR;
568 else
569 clear_bits |= DTR;
571 /* NOTE: Not subject to 'transmitter active' rule. */
572 up->curregs[R5] |= set_bits;
573 up->curregs[R5] &= ~clear_bits;
574 write_zsreg(channel, R5, up->curregs[R5]);
575 }
577 /* The port lock is held and interrupts are disabled. */
578 static void ip22zilog_stop_tx(struct uart_port *port)
579 {
580 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
582 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
583 }
585 /* The port lock is held and interrupts are disabled. */
586 static void ip22zilog_start_tx(struct uart_port *port)
587 {
588 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
589 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
590 unsigned char status;
592 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
593 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
595 status = readb(&channel->control);
596 ZSDELAY();
598 /* TX busy? Just wait for the TX done interrupt. */
599 if (!(status & Tx_BUF_EMP))
600 return;
602 /* Send the first character to jump-start the TX done
603 * IRQ sending engine.
604 */
605 if (port->x_char) {
606 writeb(port->x_char, &channel->data);
607 ZSDELAY();
608 ZS_WSYNC(channel);
610 port->icount.tx++;
611 port->x_char = 0;
612 } else {
613 struct circ_buf *xmit = &port->info->xmit;
615 writeb(xmit->buf[xmit->tail], &channel->data);
616 ZSDELAY();
617 ZS_WSYNC(channel);
619 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
620 port->icount.tx++;
622 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
623 uart_write_wakeup(&up->port);
624 }
625 }
627 /* The port lock is held and interrupts are disabled. */
628 static void ip22zilog_stop_rx(struct uart_port *port)
629 {
630 struct uart_ip22zilog_port *up = UART_ZILOG(port);
631 struct zilog_channel *channel;
633 if (ZS_IS_CONS(up))
634 return;
636 channel = ZILOG_CHANNEL_FROM_PORT(port);
638 /* Disable all RX interrupts. */
639 up->curregs[R1] &= ~RxINT_MASK;
640 ip22zilog_maybe_update_regs(up, channel);
641 }
643 /* The port lock is held. */
644 static void ip22zilog_enable_ms(struct uart_port *port)
645 {
646 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
647 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
648 unsigned char new_reg;
650 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
651 if (new_reg != up->curregs[R15]) {
652 up->curregs[R15] = new_reg;
654 /* NOTE: Not subject to 'transmitter active' rule. */
655 write_zsreg(channel, R15, up->curregs[R15]);
656 }
657 }
659 /* The port lock is not held. */
660 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
661 {
662 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
663 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
664 unsigned char set_bits, clear_bits, new_reg;
665 unsigned long flags;
667 set_bits = clear_bits = 0;
669 if (break_state)
670 set_bits |= SND_BRK;
671 else
672 clear_bits |= SND_BRK;
674 spin_lock_irqsave(&port->lock, flags);
676 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
677 if (new_reg != up->curregs[R5]) {
678 up->curregs[R5] = new_reg;
680 /* NOTE: Not subject to 'transmitter active' rule. */
681 write_zsreg(channel, R5, up->curregs[R5]);
682 }
684 spin_unlock_irqrestore(&port->lock, flags);
685 }
687 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
688 {
689 struct zilog_channel *channel;
691 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
692 up->prev_status = readb(&channel->control);
694 /* Enable receiver and transmitter. */
695 up->curregs[R3] |= RxENAB;
696 up->curregs[R5] |= TxENAB;
698 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
699 ip22zilog_maybe_update_regs(up, channel);
700 }
702 static int ip22zilog_startup(struct uart_port *port)
703 {
704 struct uart_ip22zilog_port *up = UART_ZILOG(port);
705 unsigned long flags;
707 if (ZS_IS_CONS(up))
708 return 0;
710 spin_lock_irqsave(&port->lock, flags);
711 __ip22zilog_startup(up);
712 spin_unlock_irqrestore(&port->lock, flags);
713 return 0;
714 }
716 /*
717 * The test for ZS_IS_CONS is explained by the following e-mail:
718 *****
719 * From: Russell King <rmk@arm.linux.org.uk>
720 * Date: Sun, 8 Dec 2002 10:18:38 +0000
721 *
722 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
723 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
724 * > and I noticed that something is not right with reference
725 * > counting in this case. It seems that when the console
726 * > is open by kernel initially, this is not accounted
727 * > as an open, and uart_startup is not called.
728 *
729 * That is correct. We are unable to call uart_startup when the serial
730 * console is initialised because it may need to allocate memory (as
731 * request_irq does) and the memory allocators may not have been
732 * initialised.
733 *
734 * 1. initialise the port into a state where it can send characters in the
735 * console write method.
736 *
737 * 2. don't do the actual hardware shutdown in your shutdown() method (but
738 * do the normal software shutdown - ie, free irqs etc)
739 *****
740 */
741 static void ip22zilog_shutdown(struct uart_port *port)
742 {
743 struct uart_ip22zilog_port *up = UART_ZILOG(port);
744 struct zilog_channel *channel;
745 unsigned long flags;
747 if (ZS_IS_CONS(up))
748 return;
750 spin_lock_irqsave(&port->lock, flags);
752 channel = ZILOG_CHANNEL_FROM_PORT(port);
754 /* Disable receiver and transmitter. */
755 up->curregs[R3] &= ~RxENAB;
756 up->curregs[R5] &= ~TxENAB;
758 /* Disable all interrupts and BRK assertion. */
759 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
760 up->curregs[R5] &= ~SND_BRK;
761 ip22zilog_maybe_update_regs(up, channel);
763 spin_unlock_irqrestore(&port->lock, flags);
764 }
766 /* Shared by TTY driver and serial console setup. The port lock is held
767 * and local interrupts are disabled.
768 */
769 static void
770 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
771 unsigned int iflag, int brg)
772 {
774 up->curregs[R10] = NRZ;
775 up->curregs[R11] = TCBR | RCBR;
777 /* Program BAUD and clock source. */
778 up->curregs[R4] &= ~XCLK_MASK;
779 up->curregs[R4] |= X16CLK;
780 up->curregs[R12] = brg & 0xff;
781 up->curregs[R13] = (brg >> 8) & 0xff;
782 up->curregs[R14] = BRENAB;
784 /* Character size, stop bits, and parity. */
785 up->curregs[3] &= ~RxN_MASK;
786 up->curregs[5] &= ~TxN_MASK;
787 switch (cflag & CSIZE) {
788 case CS5:
789 up->curregs[3] |= Rx5;
790 up->curregs[5] |= Tx5;
791 up->parity_mask = 0x1f;
792 break;
793 case CS6:
794 up->curregs[3] |= Rx6;
795 up->curregs[5] |= Tx6;
796 up->parity_mask = 0x3f;
797 break;
798 case CS7:
799 up->curregs[3] |= Rx7;
800 up->curregs[5] |= Tx7;
801 up->parity_mask = 0x7f;
802 break;
803 case CS8:
804 default:
805 up->curregs[3] |= Rx8;
806 up->curregs[5] |= Tx8;
807 up->parity_mask = 0xff;
808 break;
809 };
810 up->curregs[4] &= ~0x0c;
811 if (cflag & CSTOPB)
812 up->curregs[4] |= SB2;
813 else
814 up->curregs[4] |= SB1;
815 if (cflag & PARENB)
816 up->curregs[4] |= PAR_ENAB;
817 else
818 up->curregs[4] &= ~PAR_ENAB;
819 if (!(cflag & PARODD))
820 up->curregs[4] |= PAR_EVEN;
821 else
822 up->curregs[4] &= ~PAR_EVEN;
824 up->port.read_status_mask = Rx_OVR;
825 if (iflag & INPCK)
826 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
827 if (iflag & (BRKINT | PARMRK))
828 up->port.read_status_mask |= BRK_ABRT;
830 up->port.ignore_status_mask = 0;
831 if (iflag & IGNPAR)
832 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
833 if (iflag & IGNBRK) {
834 up->port.ignore_status_mask |= BRK_ABRT;
835 if (iflag & IGNPAR)
836 up->port.ignore_status_mask |= Rx_OVR;
837 }
839 if ((cflag & CREAD) == 0)
840 up->port.ignore_status_mask = 0xff;
841 }
843 /* The port lock is not held. */
844 static void
845 ip22zilog_set_termios(struct uart_port *port, struct termios *termios,
846 struct termios *old)
847 {
848 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
849 unsigned long flags;
850 int baud, brg;
852 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
854 spin_lock_irqsave(&up->port.lock, flags);
856 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
858 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
860 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
861 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
862 else
863 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
865 up->cflag = termios->c_cflag;
867 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
869 spin_unlock_irqrestore(&up->port.lock, flags);
870 }
872 static const char *ip22zilog_type(struct uart_port *port)
873 {
874 return "IP22-Zilog";
875 }
877 /* We do not request/release mappings of the registers here, this
878 * happens at early serial probe time.
879 */
880 static void ip22zilog_release_port(struct uart_port *port)
881 {
882 }
884 static int ip22zilog_request_port(struct uart_port *port)
885 {
886 return 0;
887 }
889 /* These do not need to do anything interesting either. */
890 static void ip22zilog_config_port(struct uart_port *port, int flags)
891 {
892 }
894 /* We do not support letting the user mess with the divisor, IRQ, etc. */
895 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
896 {
897 return -EINVAL;
898 }
900 static struct uart_ops ip22zilog_pops = {
901 .tx_empty = ip22zilog_tx_empty,
902 .set_mctrl = ip22zilog_set_mctrl,
903 .get_mctrl = ip22zilog_get_mctrl,
904 .stop_tx = ip22zilog_stop_tx,
905 .start_tx = ip22zilog_start_tx,
906 .stop_rx = ip22zilog_stop_rx,
907 .enable_ms = ip22zilog_enable_ms,
908 .break_ctl = ip22zilog_break_ctl,
909 .startup = ip22zilog_startup,
910 .shutdown = ip22zilog_shutdown,
911 .set_termios = ip22zilog_set_termios,
912 .type = ip22zilog_type,
913 .release_port = ip22zilog_release_port,
914 .request_port = ip22zilog_request_port,
915 .config_port = ip22zilog_config_port,
916 .verify_port = ip22zilog_verify_port,
917 };
919 static struct uart_ip22zilog_port *ip22zilog_port_table;
920 static struct zilog_layout **ip22zilog_chip_regs;
922 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
923 static int zilog_irq = -1;
925 static void * __init alloc_one_table(unsigned long size)
926 {
927 void *ret;
929 ret = kmalloc(size, GFP_KERNEL);
930 if (ret != NULL)
931 memset(ret, 0, size);
933 return ret;
934 }
936 static void __init ip22zilog_alloc_tables(void)
937 {
938 ip22zilog_port_table = (struct uart_ip22zilog_port *)
939 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
940 ip22zilog_chip_regs = (struct zilog_layout **)
941 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
943 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
944 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
945 }
946 }
948 /* Get the address of the registers for IP22-Zilog instance CHIP. */
949 static struct zilog_layout * __init get_zs(int chip)
950 {
951 unsigned long base;
953 if (chip < 0 || chip >= NUM_IP22ZILOG) {
954 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
955 }
957 /* Not probe-able, hard code it. */
958 base = (unsigned long) &sgioc->uart;
960 zilog_irq = SGI_SERIAL_IRQ;
961 request_mem_region(base, 8, "IP22-Zilog");
963 return (struct zilog_layout *) base;
964 }
966 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
968 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
969 static void ip22zilog_put_char(struct uart_port *port, int ch)
970 {
971 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
972 int loops = ZS_PUT_CHAR_MAX_DELAY;
974 /* This is a timed polling loop so do not switch the explicit
975 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
976 */
977 do {
978 unsigned char val = readb(&channel->control);
979 if (val & Tx_BUF_EMP) {
980 ZSDELAY();
981 break;
982 }
983 udelay(5);
984 } while (--loops);
986 writeb(ch, &channel->data);
987 ZSDELAY();
988 ZS_WSYNC(channel);
989 }
991 static void
992 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
993 {
994 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
995 unsigned long flags;
997 spin_lock_irqsave(&up->port.lock, flags);
998 uart_console_write(&up->port, s, count, ip22zilog_put_char);
999 udelay(2);
1000 spin_unlock_irqrestore(&up->port.lock, flags);
1003 void
1004 ip22serial_console_termios(struct console *con, char *options)
1006 int baud = 9600, bits = 8, cflag;
1007 int parity = 'n';
1008 int flow = 'n';
1010 if (options)
1011 uart_parse_options(options, &baud, &parity, &bits, &flow);
1013 cflag = CREAD | HUPCL | CLOCAL;
1015 switch (baud) {
1016 case 150: cflag |= B150; break;
1017 case 300: cflag |= B300; break;
1018 case 600: cflag |= B600; break;
1019 case 1200: cflag |= B1200; break;
1020 case 2400: cflag |= B2400; break;
1021 case 4800: cflag |= B4800; break;
1022 case 9600: cflag |= B9600; break;
1023 case 19200: cflag |= B19200; break;
1024 case 38400: cflag |= B38400; break;
1025 default: baud = 9600; cflag |= B9600; break;
1028 con->cflag = cflag | CS8; /* 8N1 */
1031 static int __init ip22zilog_console_setup(struct console *con, char *options)
1033 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1034 unsigned long flags;
1035 int baud, brg;
1037 printk("Console: ttyS%d (IP22-Zilog)\n", con->index);
1039 /* Get firmware console settings. */
1040 ip22serial_console_termios(con, options);
1042 /* Firmware console speed is limited to 150-->38400 baud so
1043 * this hackish cflag thing is OK.
1044 */
1045 switch (con->cflag & CBAUD) {
1046 case B150: baud = 150; break;
1047 case B300: baud = 300; break;
1048 case B600: baud = 600; break;
1049 case B1200: baud = 1200; break;
1050 case B2400: baud = 2400; break;
1051 case B4800: baud = 4800; break;
1052 default: case B9600: baud = 9600; break;
1053 case B19200: baud = 19200; break;
1054 case B38400: baud = 38400; break;
1055 };
1057 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1059 spin_lock_irqsave(&up->port.lock, flags);
1061 up->curregs[R15] = BRKIE;
1062 ip22zilog_convert_to_zs(up, con->cflag, 0, brg);
1064 __ip22zilog_startup(up);
1066 spin_unlock_irqrestore(&up->port.lock, flags);
1068 return 0;
1071 static struct uart_driver ip22zilog_reg;
1073 static struct console ip22zilog_console = {
1074 .name = "ttyS",
1075 .write = ip22zilog_console_write,
1076 .device = uart_console_device,
1077 .setup = ip22zilog_console_setup,
1078 .flags = CON_PRINTBUFFER,
1079 .index = -1,
1080 .data = &ip22zilog_reg,
1081 };
1082 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1084 static struct uart_driver ip22zilog_reg = {
1085 .owner = THIS_MODULE,
1086 .driver_name = "serial",
1087 .dev_name = "ttyS",
1088 .major = TTY_MAJOR,
1089 .minor = 64,
1090 .nr = NUM_CHANNELS,
1091 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1092 .cons = &ip22zilog_console,
1093 #endif
1094 };
1096 static void __init ip22zilog_prepare(void)
1098 struct uart_ip22zilog_port *up;
1099 struct zilog_layout *rp;
1100 int channel, chip;
1102 /*
1103 * Temporary fix.
1104 */
1105 for (channel = 0; channel < NUM_CHANNELS; channel++)
1106 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1108 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1109 up = &ip22zilog_port_table[0];
1110 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1111 up[channel].next = &up[channel - 1];
1112 up[channel].next = NULL;
1114 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1115 if (!ip22zilog_chip_regs[chip]) {
1116 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1118 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1119 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1121 /* In theory mapbase is the physical address ... */
1122 up[(chip * 2) + 0].port.mapbase =
1123 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1124 up[(chip * 2) + 1].port.mapbase =
1125 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1128 /* Channel A */
1129 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1130 up[(chip * 2) + 0].port.irq = zilog_irq;
1131 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1132 up[(chip * 2) + 0].port.fifosize = 1;
1133 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1134 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1135 up[(chip * 2) + 0].port.flags = 0;
1136 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1137 up[(chip * 2) + 0].flags = 0;
1139 /* Channel B */
1140 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1141 up[(chip * 2) + 1].port.irq = zilog_irq;
1142 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1143 up[(chip * 2) + 1].port.fifosize = 1;
1144 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1145 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1146 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1147 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1151 static void __init ip22zilog_init_hw(void)
1153 int i;
1155 for (i = 0; i < NUM_CHANNELS; i++) {
1156 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1157 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1158 unsigned long flags;
1159 int baud, brg;
1161 spin_lock_irqsave(&up->port.lock, flags);
1163 if (ZS_IS_CHANNEL_A(up)) {
1164 write_zsreg(channel, R9, FHWRES);
1165 ZSDELAY_LONG();
1166 (void) read_zsreg(channel, R0);
1169 /* Normal serial TTY. */
1170 up->parity_mask = 0xff;
1171 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1172 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1173 up->curregs[R3] = RxENAB | Rx8;
1174 up->curregs[R5] = TxENAB | Tx8;
1175 up->curregs[R9] = NV | MIE;
1176 up->curregs[R10] = NRZ;
1177 up->curregs[R11] = TCBR | RCBR;
1178 baud = 9600;
1179 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1180 up->curregs[R12] = (brg & 0xff);
1181 up->curregs[R13] = (brg >> 8) & 0xff;
1182 up->curregs[R14] = BRENAB;
1183 __load_zsregs(channel, up->curregs);
1184 /* set master interrupt enable */
1185 write_zsreg(channel, R9, up->curregs[R9]);
1187 spin_unlock_irqrestore(&up->port.lock, flags);
1191 static int __init ip22zilog_ports_init(void)
1193 int ret;
1195 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1197 ip22zilog_prepare();
1199 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1200 "IP22-Zilog", ip22zilog_irq_chain)) {
1201 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1204 ip22zilog_init_hw();
1206 ret = uart_register_driver(&ip22zilog_reg);
1207 if (ret == 0) {
1208 int i;
1210 for (i = 0; i < NUM_CHANNELS; i++) {
1211 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1213 uart_add_one_port(&ip22zilog_reg, &up->port);
1217 return ret;
1220 static int __init ip22zilog_init(void)
1222 /* IP22 Zilog setup is hard coded, no probing to do. */
1223 ip22zilog_alloc_tables();
1224 ip22zilog_ports_init();
1226 return 0;
1229 static void __exit ip22zilog_exit(void)
1231 int i;
1233 for (i = 0; i < NUM_CHANNELS; i++) {
1234 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1236 uart_remove_one_port(&ip22zilog_reg, &up->port);
1239 uart_unregister_driver(&ip22zilog_reg);
1242 module_init(ip22zilog_init);
1243 module_exit(ip22zilog_exit);
1245 /* David wrote it but I'm to blame for the bugs ... */
1246 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1247 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1248 MODULE_LICENSE("GPL");