ia64/linux-2.6.18-xen.hg

view drivers/serial/8250.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
44 #include <asm/io.h>
45 #include <asm/irq.h>
47 #include "8250.h"
49 /*
50 * Configuration:
51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58 /*
59 * Debugging.
60 */
61 #if 0
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
63 #else
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
65 #endif
67 #if 0
68 #define DEBUG_INTR(fmt...) printk(fmt)
69 #else
70 #define DEBUG_INTR(fmt...) do { } while (0)
71 #endif
73 #define PASS_LIMIT 256
75 /*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80 #define is_real_interrupt(irq) ((irq) != 0)
82 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83 #define CONFIG_SERIAL_DETECT_IRQ 1
84 #endif
85 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
86 #define CONFIG_SERIAL_MANY_PORTS 1
87 #endif
89 /*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93 #define CONFIG_HUB6 1
95 #include <asm/serial.h>
97 /*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102 #ifndef SERIAL_PORT_DFNS
103 #define SERIAL_PORT_DFNS
104 #endif
106 static const struct old_serial_port old_serial_port[] = {
107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108 };
110 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
112 #ifdef CONFIG_SERIAL_8250_RSA
114 #define PORT_RSA_MAX 4
115 static unsigned long probe_rsa[PORT_RSA_MAX];
116 static unsigned int probe_rsa_count;
117 #endif /* CONFIG_SERIAL_8250_RSA */
119 struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
125 unsigned int tx_loadsz; /* transmit fifo load size */
126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139 };
141 struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144 };
146 static struct irq_info irq_lists[NR_IRQS];
148 /*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151 static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
254 };
256 #ifdef CONFIG_SERIAL_8250_AU1X00
258 /* Au1x00 UART hardware has a weird register layout */
259 static const u8 au_io_in_map[] = {
260 [UART_RX] = 0,
261 [UART_IER] = 2,
262 [UART_IIR] = 3,
263 [UART_LCR] = 5,
264 [UART_MCR] = 6,
265 [UART_LSR] = 7,
266 [UART_MSR] = 8,
267 };
269 static const u8 au_io_out_map[] = {
270 [UART_TX] = 1,
271 [UART_IER] = 2,
272 [UART_FCR] = 4,
273 [UART_LCR] = 5,
274 [UART_MCR] = 6,
275 };
277 /* sane hardware needs no mapping */
278 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
279 {
280 if (up->port.iotype != UPIO_AU)
281 return offset;
282 return au_io_in_map[offset];
283 }
285 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
286 {
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_out_map[offset];
290 }
292 #else
294 /* sane hardware needs no mapping */
295 #define map_8250_in_reg(up, offset) (offset)
296 #define map_8250_out_reg(up, offset) (offset)
298 #endif
300 static unsigned int serial_in(struct uart_8250_port *up, int offset)
301 {
302 unsigned int tmp;
303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
316 #ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319 #endif
321 case UPIO_TSI:
322 if (offset == UART_IIR) {
323 tmp = readl((u32 *)(up->port.membase + UART_RX));
324 return (cpu_to_le32(tmp) >> 8) & 0xff;
325 } else
326 return readb(up->port.membase + offset);
328 default:
329 return inb(up->port.iobase + offset);
330 }
331 }
333 static void
334 serial_out(struct uart_8250_port *up, int offset, int value)
335 {
336 offset = map_8250_out_reg(up, offset) << up->port.regshift;
338 switch (up->port.iotype) {
339 case UPIO_HUB6:
340 outb(up->port.hub6 - 1 + offset, up->port.iobase);
341 outb(value, up->port.iobase + 1);
342 break;
344 case UPIO_MEM:
345 writeb(value, up->port.membase + offset);
346 break;
348 case UPIO_MEM32:
349 writel(value, up->port.membase + offset);
350 break;
352 #ifdef CONFIG_SERIAL_8250_AU1X00
353 case UPIO_AU:
354 __raw_writel(value, up->port.membase + offset);
355 break;
356 #endif
357 case UPIO_TSI:
358 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
359 writeb(value, up->port.membase + offset);
360 break;
362 default:
363 outb(value, up->port.iobase + offset);
364 }
365 }
367 /*
368 * We used to support using pause I/O for certain machines. We
369 * haven't supported this for a while, but just in case it's badly
370 * needed for certain old 386 machines, I've left these #define's
371 * in....
372 */
373 #define serial_inp(up, offset) serial_in(up, offset)
374 #define serial_outp(up, offset, value) serial_out(up, offset, value)
376 /* Uart divisor latch read */
377 static inline int _serial_dl_read(struct uart_8250_port *up)
378 {
379 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
380 }
382 /* Uart divisor latch write */
383 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
384 {
385 serial_outp(up, UART_DLL, value & 0xff);
386 serial_outp(up, UART_DLM, value >> 8 & 0xff);
387 }
389 #ifdef CONFIG_SERIAL_8250_AU1X00
390 /* Au1x00 haven't got a standard divisor latch */
391 static int serial_dl_read(struct uart_8250_port *up)
392 {
393 if (up->port.iotype == UPIO_AU)
394 return __raw_readl(up->port.membase + 0x28);
395 else
396 return _serial_dl_read(up);
397 }
399 static void serial_dl_write(struct uart_8250_port *up, int value)
400 {
401 if (up->port.iotype == UPIO_AU)
402 __raw_writel(value, up->port.membase + 0x28);
403 else
404 _serial_dl_write(up, value);
405 }
406 #else
407 #define serial_dl_read(up) _serial_dl_read(up)
408 #define serial_dl_write(up, value) _serial_dl_write(up, value)
409 #endif
411 /*
412 * For the 16C950
413 */
414 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
415 {
416 serial_out(up, UART_SCR, offset);
417 serial_out(up, UART_ICR, value);
418 }
420 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
421 {
422 unsigned int value;
424 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
425 serial_out(up, UART_SCR, offset);
426 value = serial_in(up, UART_ICR);
427 serial_icr_write(up, UART_ACR, up->acr);
429 return value;
430 }
432 /*
433 * FIFO support.
434 */
435 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
436 {
437 if (p->capabilities & UART_CAP_FIFO) {
438 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
439 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
440 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
441 serial_outp(p, UART_FCR, 0);
442 }
443 }
445 /*
446 * IER sleep support. UARTs which have EFRs need the "extended
447 * capability" bit enabled. Note that on XR16C850s, we need to
448 * reset LCR to write to IER.
449 */
450 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
451 {
452 if (p->capabilities & UART_CAP_SLEEP) {
453 if (p->capabilities & UART_CAP_EFR) {
454 serial_outp(p, UART_LCR, 0xBF);
455 serial_outp(p, UART_EFR, UART_EFR_ECB);
456 serial_outp(p, UART_LCR, 0);
457 }
458 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
459 if (p->capabilities & UART_CAP_EFR) {
460 serial_outp(p, UART_LCR, 0xBF);
461 serial_outp(p, UART_EFR, 0);
462 serial_outp(p, UART_LCR, 0);
463 }
464 }
465 }
467 #ifdef CONFIG_SERIAL_8250_RSA
468 /*
469 * Attempts to turn on the RSA FIFO. Returns zero on failure.
470 * We set the port uart clock rate if we succeed.
471 */
472 static int __enable_rsa(struct uart_8250_port *up)
473 {
474 unsigned char mode;
475 int result;
477 mode = serial_inp(up, UART_RSA_MSR);
478 result = mode & UART_RSA_MSR_FIFO;
480 if (!result) {
481 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
482 mode = serial_inp(up, UART_RSA_MSR);
483 result = mode & UART_RSA_MSR_FIFO;
484 }
486 if (result)
487 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
489 return result;
490 }
492 static void enable_rsa(struct uart_8250_port *up)
493 {
494 if (up->port.type == PORT_RSA) {
495 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
496 spin_lock_irq(&up->port.lock);
497 __enable_rsa(up);
498 spin_unlock_irq(&up->port.lock);
499 }
500 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
501 serial_outp(up, UART_RSA_FRR, 0);
502 }
503 }
505 /*
506 * Attempts to turn off the RSA FIFO. Returns zero on failure.
507 * It is unknown why interrupts were disabled in here. However,
508 * the caller is expected to preserve this behaviour by grabbing
509 * the spinlock before calling this function.
510 */
511 static void disable_rsa(struct uart_8250_port *up)
512 {
513 unsigned char mode;
514 int result;
516 if (up->port.type == PORT_RSA &&
517 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
518 spin_lock_irq(&up->port.lock);
520 mode = serial_inp(up, UART_RSA_MSR);
521 result = !(mode & UART_RSA_MSR_FIFO);
523 if (!result) {
524 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
525 mode = serial_inp(up, UART_RSA_MSR);
526 result = !(mode & UART_RSA_MSR_FIFO);
527 }
529 if (result)
530 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
531 spin_unlock_irq(&up->port.lock);
532 }
533 }
534 #endif /* CONFIG_SERIAL_8250_RSA */
536 /*
537 * This is a quickie test to see how big the FIFO is.
538 * It doesn't work at all the time, more's the pity.
539 */
540 static int size_fifo(struct uart_8250_port *up)
541 {
542 unsigned char old_fcr, old_mcr, old_lcr;
543 unsigned short old_dl;
544 int count;
546 old_lcr = serial_inp(up, UART_LCR);
547 serial_outp(up, UART_LCR, 0);
548 old_fcr = serial_inp(up, UART_FCR);
549 old_mcr = serial_inp(up, UART_MCR);
550 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
551 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
552 serial_outp(up, UART_MCR, UART_MCR_LOOP);
553 serial_outp(up, UART_LCR, UART_LCR_DLAB);
554 old_dl = serial_dl_read(up);
555 serial_dl_write(up, 0x0001);
556 serial_outp(up, UART_LCR, 0x03);
557 for (count = 0; count < 256; count++)
558 serial_outp(up, UART_TX, count);
559 mdelay(20);/* FIXME - schedule_timeout */
560 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
561 (count < 256); count++)
562 serial_inp(up, UART_RX);
563 serial_outp(up, UART_FCR, old_fcr);
564 serial_outp(up, UART_MCR, old_mcr);
565 serial_outp(up, UART_LCR, UART_LCR_DLAB);
566 serial_dl_write(up, old_dl);
567 serial_outp(up, UART_LCR, old_lcr);
569 return count;
570 }
572 /*
573 * Read UART ID using the divisor method - set DLL and DLM to zero
574 * and the revision will be in DLL and device type in DLM. We
575 * preserve the device state across this.
576 */
577 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
578 {
579 unsigned char old_dll, old_dlm, old_lcr;
580 unsigned int id;
582 old_lcr = serial_inp(p, UART_LCR);
583 serial_outp(p, UART_LCR, UART_LCR_DLAB);
585 old_dll = serial_inp(p, UART_DLL);
586 old_dlm = serial_inp(p, UART_DLM);
588 serial_outp(p, UART_DLL, 0);
589 serial_outp(p, UART_DLM, 0);
591 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
593 serial_outp(p, UART_DLL, old_dll);
594 serial_outp(p, UART_DLM, old_dlm);
595 serial_outp(p, UART_LCR, old_lcr);
597 return id;
598 }
600 /*
601 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
602 * When this function is called we know it is at least a StarTech
603 * 16650 V2, but it might be one of several StarTech UARTs, or one of
604 * its clones. (We treat the broken original StarTech 16650 V1 as a
605 * 16550, and why not? Startech doesn't seem to even acknowledge its
606 * existence.)
607 *
608 * What evil have men's minds wrought...
609 */
610 static void autoconfig_has_efr(struct uart_8250_port *up)
611 {
612 unsigned int id1, id2, id3, rev;
614 /*
615 * Everything with an EFR has SLEEP
616 */
617 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
619 /*
620 * First we check to see if it's an Oxford Semiconductor UART.
621 *
622 * If we have to do this here because some non-National
623 * Semiconductor clone chips lock up if you try writing to the
624 * LSR register (which serial_icr_read does)
625 */
627 /*
628 * Check for Oxford Semiconductor 16C950.
629 *
630 * EFR [4] must be set else this test fails.
631 *
632 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
633 * claims that it's needed for 952 dual UART's (which are not
634 * recommended for new designs).
635 */
636 up->acr = 0;
637 serial_out(up, UART_LCR, 0xBF);
638 serial_out(up, UART_EFR, UART_EFR_ECB);
639 serial_out(up, UART_LCR, 0x00);
640 id1 = serial_icr_read(up, UART_ID1);
641 id2 = serial_icr_read(up, UART_ID2);
642 id3 = serial_icr_read(up, UART_ID3);
643 rev = serial_icr_read(up, UART_REV);
645 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
647 if (id1 == 0x16 && id2 == 0xC9 &&
648 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
649 up->port.type = PORT_16C950;
651 /*
652 * Enable work around for the Oxford Semiconductor 952 rev B
653 * chip which causes it to seriously miscalculate baud rates
654 * when DLL is 0.
655 */
656 if (id3 == 0x52 && rev == 0x01)
657 up->bugs |= UART_BUG_QUOT;
658 return;
659 }
661 /*
662 * We check for a XR16C850 by setting DLL and DLM to 0, and then
663 * reading back DLL and DLM. The chip type depends on the DLM
664 * value read back:
665 * 0x10 - XR16C850 and the DLL contains the chip revision.
666 * 0x12 - XR16C2850.
667 * 0x14 - XR16C854.
668 */
669 id1 = autoconfig_read_divisor_id(up);
670 DEBUG_AUTOCONF("850id=%04x ", id1);
672 id2 = id1 >> 8;
673 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
674 up->port.type = PORT_16850;
675 return;
676 }
678 /*
679 * It wasn't an XR16C850.
680 *
681 * We distinguish between the '654 and the '650 by counting
682 * how many bytes are in the FIFO. I'm using this for now,
683 * since that's the technique that was sent to me in the
684 * serial driver update, but I'm not convinced this works.
685 * I've had problems doing this in the past. -TYT
686 */
687 if (size_fifo(up) == 64)
688 up->port.type = PORT_16654;
689 else
690 up->port.type = PORT_16650V2;
691 }
693 /*
694 * We detected a chip without a FIFO. Only two fall into
695 * this category - the original 8250 and the 16450. The
696 * 16450 has a scratch register (accessible with LCR=0)
697 */
698 static void autoconfig_8250(struct uart_8250_port *up)
699 {
700 unsigned char scratch, status1, status2;
702 up->port.type = PORT_8250;
704 scratch = serial_in(up, UART_SCR);
705 serial_outp(up, UART_SCR, 0xa5);
706 status1 = serial_in(up, UART_SCR);
707 serial_outp(up, UART_SCR, 0x5a);
708 status2 = serial_in(up, UART_SCR);
709 serial_outp(up, UART_SCR, scratch);
711 if (status1 == 0xa5 && status2 == 0x5a)
712 up->port.type = PORT_16450;
713 }
715 static int broken_efr(struct uart_8250_port *up)
716 {
717 /*
718 * Exar ST16C2550 "A2" devices incorrectly detect as
719 * having an EFR, and report an ID of 0x0201. See
720 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
721 */
722 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
723 return 1;
725 return 0;
726 }
728 /*
729 * We know that the chip has FIFOs. Does it have an EFR? The
730 * EFR is located in the same register position as the IIR and
731 * we know the top two bits of the IIR are currently set. The
732 * EFR should contain zero. Try to read the EFR.
733 */
734 static void autoconfig_16550a(struct uart_8250_port *up)
735 {
736 unsigned char status1, status2;
737 unsigned int iersave;
739 up->port.type = PORT_16550A;
740 up->capabilities |= UART_CAP_FIFO;
742 /*
743 * Check for presence of the EFR when DLAB is set.
744 * Only ST16C650V1 UARTs pass this test.
745 */
746 serial_outp(up, UART_LCR, UART_LCR_DLAB);
747 if (serial_in(up, UART_EFR) == 0) {
748 serial_outp(up, UART_EFR, 0xA8);
749 if (serial_in(up, UART_EFR) != 0) {
750 DEBUG_AUTOCONF("EFRv1 ");
751 up->port.type = PORT_16650;
752 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
753 } else {
754 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
755 }
756 serial_outp(up, UART_EFR, 0);
757 return;
758 }
760 /*
761 * Maybe it requires 0xbf to be written to the LCR.
762 * (other ST16C650V2 UARTs, TI16C752A, etc)
763 */
764 serial_outp(up, UART_LCR, 0xBF);
765 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
766 DEBUG_AUTOCONF("EFRv2 ");
767 autoconfig_has_efr(up);
768 return;
769 }
771 /*
772 * Check for a National Semiconductor SuperIO chip.
773 * Attempt to switch to bank 2, read the value of the LOOP bit
774 * from EXCR1. Switch back to bank 0, change it in MCR. Then
775 * switch back to bank 2, read it from EXCR1 again and check
776 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
777 */
778 serial_outp(up, UART_LCR, 0);
779 status1 = serial_in(up, UART_MCR);
780 serial_outp(up, UART_LCR, 0xE0);
781 status2 = serial_in(up, 0x02); /* EXCR1 */
783 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
784 serial_outp(up, UART_LCR, 0);
785 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
786 serial_outp(up, UART_LCR, 0xE0);
787 status2 = serial_in(up, 0x02); /* EXCR1 */
788 serial_outp(up, UART_LCR, 0);
789 serial_outp(up, UART_MCR, status1);
791 if ((status2 ^ status1) & UART_MCR_LOOP) {
792 unsigned short quot;
794 serial_outp(up, UART_LCR, 0xE0);
796 quot = serial_dl_read(up);
797 quot <<= 3;
799 status1 = serial_in(up, 0x04); /* EXCR1 */
800 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
801 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
802 serial_outp(up, 0x04, status1);
804 serial_dl_write(up, quot);
806 serial_outp(up, UART_LCR, 0);
808 up->port.uartclk = 921600*16;
809 up->port.type = PORT_NS16550A;
810 up->capabilities |= UART_NATSEMI;
811 return;
812 }
813 }
815 /*
816 * No EFR. Try to detect a TI16750, which only sets bit 5 of
817 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
818 * Try setting it with and without DLAB set. Cheap clones
819 * set bit 5 without DLAB set.
820 */
821 serial_outp(up, UART_LCR, 0);
822 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
823 status1 = serial_in(up, UART_IIR) >> 5;
824 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
825 serial_outp(up, UART_LCR, UART_LCR_DLAB);
826 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
827 status2 = serial_in(up, UART_IIR) >> 5;
828 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
829 serial_outp(up, UART_LCR, 0);
831 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
833 if (status1 == 6 && status2 == 7) {
834 up->port.type = PORT_16750;
835 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
836 return;
837 }
839 /*
840 * Try writing and reading the UART_IER_UUE bit (b6).
841 * If it works, this is probably one of the Xscale platform's
842 * internal UARTs.
843 * We're going to explicitly set the UUE bit to 0 before
844 * trying to write and read a 1 just to make sure it's not
845 * already a 1 and maybe locked there before we even start start.
846 */
847 iersave = serial_in(up, UART_IER);
848 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
849 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
850 /*
851 * OK it's in a known zero state, try writing and reading
852 * without disturbing the current state of the other bits.
853 */
854 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
855 if (serial_in(up, UART_IER) & UART_IER_UUE) {
856 /*
857 * It's an Xscale.
858 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
859 */
860 DEBUG_AUTOCONF("Xscale ");
861 up->port.type = PORT_XSCALE;
862 up->capabilities |= UART_CAP_UUE;
863 return;
864 }
865 } else {
866 /*
867 * If we got here we couldn't force the IER_UUE bit to 0.
868 * Log it and continue.
869 */
870 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
871 }
872 serial_outp(up, UART_IER, iersave);
873 }
875 /*
876 * This routine is called by rs_init() to initialize a specific serial
877 * port. It determines what type of UART chip this serial port is
878 * using: 8250, 16450, 16550, 16550A. The important question is
879 * whether or not this UART is a 16550A or not, since this will
880 * determine whether or not we can use its FIFO features or not.
881 */
882 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
883 {
884 unsigned char status1, scratch, scratch2, scratch3;
885 unsigned char save_lcr, save_mcr;
886 unsigned long flags;
888 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
889 return;
891 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
892 up->port.line, up->port.iobase, up->port.membase);
894 /*
895 * We really do need global IRQs disabled here - we're going to
896 * be frobbing the chips IRQ enable register to see if it exists.
897 */
898 spin_lock_irqsave(&up->port.lock, flags);
899 // save_flags(flags); cli();
901 up->capabilities = 0;
902 up->bugs = 0;
904 if (!(up->port.flags & UPF_BUGGY_UART)) {
905 /*
906 * Do a simple existence test first; if we fail this,
907 * there's no point trying anything else.
908 *
909 * 0x80 is used as a nonsense port to prevent against
910 * false positives due to ISA bus float. The
911 * assumption is that 0x80 is a non-existent port;
912 * which should be safe since include/asm/io.h also
913 * makes this assumption.
914 *
915 * Note: this is safe as long as MCR bit 4 is clear
916 * and the device is in "PC" mode.
917 */
918 scratch = serial_inp(up, UART_IER);
919 serial_outp(up, UART_IER, 0);
920 #ifdef __i386__
921 outb(0xff, 0x080);
922 #endif
923 scratch2 = serial_inp(up, UART_IER);
924 serial_outp(up, UART_IER, 0x0F);
925 #ifdef __i386__
926 outb(0, 0x080);
927 #endif
928 scratch3 = serial_inp(up, UART_IER);
929 serial_outp(up, UART_IER, scratch);
930 if (scratch2 != 0 || scratch3 != 0x0F) {
931 /*
932 * We failed; there's nothing here
933 */
934 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
935 scratch2, scratch3);
936 goto out;
937 }
938 }
940 save_mcr = serial_in(up, UART_MCR);
941 save_lcr = serial_in(up, UART_LCR);
943 /*
944 * Check to see if a UART is really there. Certain broken
945 * internal modems based on the Rockwell chipset fail this
946 * test, because they apparently don't implement the loopback
947 * test mode. So this test is skipped on the COM 1 through
948 * COM 4 ports. This *should* be safe, since no board
949 * manufacturer would be stupid enough to design a board
950 * that conflicts with COM 1-4 --- we hope!
951 */
952 if (!(up->port.flags & UPF_SKIP_TEST)) {
953 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
954 status1 = serial_inp(up, UART_MSR) & 0xF0;
955 serial_outp(up, UART_MCR, save_mcr);
956 if (status1 != 0x90) {
957 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
958 status1);
959 goto out;
960 }
961 }
963 /*
964 * We're pretty sure there's a port here. Lets find out what
965 * type of port it is. The IIR top two bits allows us to find
966 * out if it's 8250 or 16450, 16550, 16550A or later. This
967 * determines what we test for next.
968 *
969 * We also initialise the EFR (if any) to zero for later. The
970 * EFR occupies the same register location as the FCR and IIR.
971 */
972 serial_outp(up, UART_LCR, 0xBF);
973 serial_outp(up, UART_EFR, 0);
974 serial_outp(up, UART_LCR, 0);
976 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
977 scratch = serial_in(up, UART_IIR) >> 6;
979 DEBUG_AUTOCONF("iir=%d ", scratch);
981 switch (scratch) {
982 case 0:
983 autoconfig_8250(up);
984 break;
985 case 1:
986 up->port.type = PORT_UNKNOWN;
987 break;
988 case 2:
989 up->port.type = PORT_16550;
990 break;
991 case 3:
992 autoconfig_16550a(up);
993 break;
994 }
996 #ifdef CONFIG_SERIAL_8250_RSA
997 /*
998 * Only probe for RSA ports if we got the region.
999 */
1000 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1001 int i;
1003 for (i = 0 ; i < probe_rsa_count; ++i) {
1004 if (probe_rsa[i] == up->port.iobase &&
1005 __enable_rsa(up)) {
1006 up->port.type = PORT_RSA;
1007 break;
1011 #endif
1013 #ifdef CONFIG_SERIAL_8250_AU1X00
1014 /* if access method is AU, it is a 16550 with a quirk */
1015 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1016 up->bugs |= UART_BUG_NOMSR;
1017 #endif
1019 serial_outp(up, UART_LCR, save_lcr);
1021 if (up->capabilities != uart_config[up->port.type].flags) {
1022 printk(KERN_WARNING
1023 "ttyS%d: detected caps %08x should be %08x\n",
1024 up->port.line, up->capabilities,
1025 uart_config[up->port.type].flags);
1028 up->port.fifosize = uart_config[up->port.type].fifo_size;
1029 up->capabilities = uart_config[up->port.type].flags;
1030 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1032 if (up->port.type == PORT_UNKNOWN)
1033 goto out;
1035 /*
1036 * Reset the UART.
1037 */
1038 #ifdef CONFIG_SERIAL_8250_RSA
1039 if (up->port.type == PORT_RSA)
1040 serial_outp(up, UART_RSA_FRR, 0);
1041 #endif
1042 serial_outp(up, UART_MCR, save_mcr);
1043 serial8250_clear_fifos(up);
1044 (void)serial_in(up, UART_RX);
1045 if (up->capabilities & UART_CAP_UUE)
1046 serial_outp(up, UART_IER, UART_IER_UUE);
1047 else
1048 serial_outp(up, UART_IER, 0);
1050 out:
1051 spin_unlock_irqrestore(&up->port.lock, flags);
1052 // restore_flags(flags);
1053 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1056 static void autoconfig_irq(struct uart_8250_port *up)
1058 unsigned char save_mcr, save_ier;
1059 unsigned char save_ICP = 0;
1060 unsigned int ICP = 0;
1061 unsigned long irqs;
1062 int irq;
1064 if (up->port.flags & UPF_FOURPORT) {
1065 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1066 save_ICP = inb_p(ICP);
1067 outb_p(0x80, ICP);
1068 (void) inb_p(ICP);
1071 /* forget possible initially masked and pending IRQ */
1072 probe_irq_off(probe_irq_on());
1073 save_mcr = serial_inp(up, UART_MCR);
1074 save_ier = serial_inp(up, UART_IER);
1075 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1077 irqs = probe_irq_on();
1078 serial_outp(up, UART_MCR, 0);
1079 udelay (10);
1080 if (up->port.flags & UPF_FOURPORT) {
1081 serial_outp(up, UART_MCR,
1082 UART_MCR_DTR | UART_MCR_RTS);
1083 } else {
1084 serial_outp(up, UART_MCR,
1085 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1087 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1088 (void)serial_inp(up, UART_LSR);
1089 (void)serial_inp(up, UART_RX);
1090 (void)serial_inp(up, UART_IIR);
1091 (void)serial_inp(up, UART_MSR);
1092 serial_outp(up, UART_TX, 0xFF);
1093 udelay (20);
1094 irq = probe_irq_off(irqs);
1096 serial_outp(up, UART_MCR, save_mcr);
1097 serial_outp(up, UART_IER, save_ier);
1099 if (up->port.flags & UPF_FOURPORT)
1100 outb_p(save_ICP, ICP);
1102 up->port.irq = (irq > 0) ? irq : 0;
1105 static inline void __stop_tx(struct uart_8250_port *p)
1107 if (p->ier & UART_IER_THRI) {
1108 p->ier &= ~UART_IER_THRI;
1109 serial_out(p, UART_IER, p->ier);
1113 static void serial8250_stop_tx(struct uart_port *port)
1115 struct uart_8250_port *up = (struct uart_8250_port *)port;
1117 __stop_tx(up);
1119 /*
1120 * We really want to stop the transmitter from sending.
1121 */
1122 if (up->port.type == PORT_16C950) {
1123 up->acr |= UART_ACR_TXDIS;
1124 serial_icr_write(up, UART_ACR, up->acr);
1128 static void transmit_chars(struct uart_8250_port *up);
1130 static void serial8250_start_tx(struct uart_port *port)
1132 struct uart_8250_port *up = (struct uart_8250_port *)port;
1134 if (!(up->ier & UART_IER_THRI)) {
1135 up->ier |= UART_IER_THRI;
1136 serial_out(up, UART_IER, up->ier);
1138 if (up->bugs & UART_BUG_TXEN) {
1139 unsigned char lsr, iir;
1140 lsr = serial_in(up, UART_LSR);
1141 iir = serial_in(up, UART_IIR);
1142 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1143 transmit_chars(up);
1147 /*
1148 * Re-enable the transmitter if we disabled it.
1149 */
1150 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1151 up->acr &= ~UART_ACR_TXDIS;
1152 serial_icr_write(up, UART_ACR, up->acr);
1156 static void serial8250_stop_rx(struct uart_port *port)
1158 struct uart_8250_port *up = (struct uart_8250_port *)port;
1160 up->ier &= ~UART_IER_RLSI;
1161 up->port.read_status_mask &= ~UART_LSR_DR;
1162 serial_out(up, UART_IER, up->ier);
1165 static void serial8250_enable_ms(struct uart_port *port)
1167 struct uart_8250_port *up = (struct uart_8250_port *)port;
1169 /* no MSR capabilities */
1170 if (up->bugs & UART_BUG_NOMSR)
1171 return;
1173 up->ier |= UART_IER_MSI;
1174 serial_out(up, UART_IER, up->ier);
1177 static void
1178 receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1180 struct tty_struct *tty = up->port.info->tty;
1181 unsigned char ch, lsr = *status;
1182 int max_count = 256;
1183 char flag;
1185 do {
1186 ch = serial_inp(up, UART_RX);
1187 flag = TTY_NORMAL;
1188 up->port.icount.rx++;
1190 #ifdef CONFIG_SERIAL_8250_CONSOLE
1191 /*
1192 * Recover the break flag from console xmit
1193 */
1194 if (up->port.line == up->port.cons->index) {
1195 lsr |= up->lsr_break_flag;
1196 up->lsr_break_flag = 0;
1198 #endif
1200 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1201 UART_LSR_FE | UART_LSR_OE))) {
1202 /*
1203 * For statistics only
1204 */
1205 if (lsr & UART_LSR_BI) {
1206 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1207 up->port.icount.brk++;
1208 /*
1209 * We do the SysRQ and SAK checking
1210 * here because otherwise the break
1211 * may get masked by ignore_status_mask
1212 * or read_status_mask.
1213 */
1214 if (uart_handle_break(&up->port))
1215 goto ignore_char;
1216 } else if (lsr & UART_LSR_PE)
1217 up->port.icount.parity++;
1218 else if (lsr & UART_LSR_FE)
1219 up->port.icount.frame++;
1220 if (lsr & UART_LSR_OE)
1221 up->port.icount.overrun++;
1223 /*
1224 * Mask off conditions which should be ignored.
1225 */
1226 lsr &= up->port.read_status_mask;
1228 if (lsr & UART_LSR_BI) {
1229 DEBUG_INTR("handling break....");
1230 flag = TTY_BREAK;
1231 } else if (lsr & UART_LSR_PE)
1232 flag = TTY_PARITY;
1233 else if (lsr & UART_LSR_FE)
1234 flag = TTY_FRAME;
1236 if (uart_handle_sysrq_char(&up->port, ch, regs))
1237 goto ignore_char;
1239 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1241 ignore_char:
1242 lsr = serial_inp(up, UART_LSR);
1243 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1244 spin_unlock(&up->port.lock);
1245 tty_flip_buffer_push(tty);
1246 spin_lock(&up->port.lock);
1247 *status = lsr;
1250 static void transmit_chars(struct uart_8250_port *up)
1252 struct circ_buf *xmit = &up->port.info->xmit;
1253 int count;
1255 if (up->port.x_char) {
1256 serial_outp(up, UART_TX, up->port.x_char);
1257 up->port.icount.tx++;
1258 up->port.x_char = 0;
1259 return;
1261 if (uart_tx_stopped(&up->port)) {
1262 serial8250_stop_tx(&up->port);
1263 return;
1265 if (uart_circ_empty(xmit)) {
1266 __stop_tx(up);
1267 return;
1270 count = up->tx_loadsz;
1271 do {
1272 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1273 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1274 up->port.icount.tx++;
1275 if (uart_circ_empty(xmit))
1276 break;
1277 } while (--count > 0);
1279 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1280 uart_write_wakeup(&up->port);
1282 DEBUG_INTR("THRE...");
1284 if (uart_circ_empty(xmit))
1285 __stop_tx(up);
1288 static unsigned int check_modem_status(struct uart_8250_port *up)
1290 unsigned int status = serial_in(up, UART_MSR);
1292 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1293 if (status & UART_MSR_TERI)
1294 up->port.icount.rng++;
1295 if (status & UART_MSR_DDSR)
1296 up->port.icount.dsr++;
1297 if (status & UART_MSR_DDCD)
1298 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1299 if (status & UART_MSR_DCTS)
1300 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1302 wake_up_interruptible(&up->port.info->delta_msr_wait);
1305 return status;
1308 /*
1309 * This handles the interrupt from one port.
1310 */
1311 static inline void
1312 serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1314 unsigned int status;
1316 spin_lock(&up->port.lock);
1318 status = serial_inp(up, UART_LSR);
1320 DEBUG_INTR("status = %x...", status);
1322 if (status & UART_LSR_DR)
1323 receive_chars(up, &status, regs);
1324 check_modem_status(up);
1325 if (status & UART_LSR_THRE)
1326 transmit_chars(up);
1328 spin_unlock(&up->port.lock);
1331 /*
1332 * This is the serial driver's interrupt routine.
1334 * Arjan thinks the old way was overly complex, so it got simplified.
1335 * Alan disagrees, saying that need the complexity to handle the weird
1336 * nature of ISA shared interrupts. (This is a special exception.)
1338 * In order to handle ISA shared interrupts properly, we need to check
1339 * that all ports have been serviced, and therefore the ISA interrupt
1340 * line has been de-asserted.
1342 * This means we need to loop through all ports. checking that they
1343 * don't have an interrupt pending.
1344 */
1345 static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1347 struct irq_info *i = dev_id;
1348 struct list_head *l, *end = NULL;
1349 int pass_counter = 0, handled = 0;
1351 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1353 spin_lock(&i->lock);
1355 l = i->head;
1356 do {
1357 struct uart_8250_port *up;
1358 unsigned int iir;
1360 up = list_entry(l, struct uart_8250_port, list);
1362 iir = serial_in(up, UART_IIR);
1363 if (!(iir & UART_IIR_NO_INT)) {
1364 serial8250_handle_port(up, regs);
1366 handled = 1;
1368 end = NULL;
1369 } else if (end == NULL)
1370 end = l;
1372 l = l->next;
1374 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1375 /* If we hit this, we're dead. */
1376 printk(KERN_ERR "serial8250: too much work for "
1377 "irq%d\n", irq);
1378 break;
1380 } while (l != end);
1382 spin_unlock(&i->lock);
1384 DEBUG_INTR("end.\n");
1386 return IRQ_RETVAL(handled);
1389 /*
1390 * To support ISA shared interrupts, we need to have one interrupt
1391 * handler that ensures that the IRQ line has been deasserted
1392 * before returning. Failing to do this will result in the IRQ
1393 * line being stuck active, and, since ISA irqs are edge triggered,
1394 * no more IRQs will be seen.
1395 */
1396 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1398 spin_lock_irq(&i->lock);
1400 if (!list_empty(i->head)) {
1401 if (i->head == &up->list)
1402 i->head = i->head->next;
1403 list_del(&up->list);
1404 } else {
1405 BUG_ON(i->head != &up->list);
1406 i->head = NULL;
1409 spin_unlock_irq(&i->lock);
1412 static int serial_link_irq_chain(struct uart_8250_port *up)
1414 struct irq_info *i = irq_lists + up->port.irq;
1415 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1417 spin_lock_irq(&i->lock);
1419 if (i->head) {
1420 list_add(&up->list, i->head);
1421 spin_unlock_irq(&i->lock);
1423 ret = 0;
1424 } else {
1425 INIT_LIST_HEAD(&up->list);
1426 i->head = &up->list;
1427 spin_unlock_irq(&i->lock);
1429 ret = request_irq(up->port.irq, serial8250_interrupt,
1430 irq_flags, "serial", i);
1431 if (ret < 0)
1432 serial_do_unlink(i, up);
1435 return ret;
1438 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1440 struct irq_info *i = irq_lists + up->port.irq;
1442 BUG_ON(i->head == NULL);
1444 if (list_empty(i->head))
1445 free_irq(up->port.irq, i);
1447 serial_do_unlink(i, up);
1450 /*
1451 * This function is used to handle ports that do not have an
1452 * interrupt. This doesn't work very well for 16450's, but gives
1453 * barely passable results for a 16550A. (Although at the expense
1454 * of much CPU overhead).
1455 */
1456 static void serial8250_timeout(unsigned long data)
1458 struct uart_8250_port *up = (struct uart_8250_port *)data;
1459 unsigned int timeout;
1460 unsigned int iir;
1462 iir = serial_in(up, UART_IIR);
1463 if (!(iir & UART_IIR_NO_INT))
1464 serial8250_handle_port(up, NULL);
1466 timeout = up->port.timeout;
1467 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1468 mod_timer(&up->timer, jiffies + timeout);
1471 static unsigned int serial8250_tx_empty(struct uart_port *port)
1473 struct uart_8250_port *up = (struct uart_8250_port *)port;
1474 unsigned long flags;
1475 unsigned int ret;
1477 spin_lock_irqsave(&up->port.lock, flags);
1478 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1479 spin_unlock_irqrestore(&up->port.lock, flags);
1481 return ret;
1484 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1486 struct uart_8250_port *up = (struct uart_8250_port *)port;
1487 unsigned int status;
1488 unsigned int ret;
1490 status = check_modem_status(up);
1492 ret = 0;
1493 if (status & UART_MSR_DCD)
1494 ret |= TIOCM_CAR;
1495 if (status & UART_MSR_RI)
1496 ret |= TIOCM_RNG;
1497 if (status & UART_MSR_DSR)
1498 ret |= TIOCM_DSR;
1499 if (status & UART_MSR_CTS)
1500 ret |= TIOCM_CTS;
1501 return ret;
1504 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1506 struct uart_8250_port *up = (struct uart_8250_port *)port;
1507 unsigned char mcr = 0;
1509 if (mctrl & TIOCM_RTS)
1510 mcr |= UART_MCR_RTS;
1511 if (mctrl & TIOCM_DTR)
1512 mcr |= UART_MCR_DTR;
1513 if (mctrl & TIOCM_OUT1)
1514 mcr |= UART_MCR_OUT1;
1515 if (mctrl & TIOCM_OUT2)
1516 mcr |= UART_MCR_OUT2;
1517 if (mctrl & TIOCM_LOOP)
1518 mcr |= UART_MCR_LOOP;
1520 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1522 serial_out(up, UART_MCR, mcr);
1525 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1527 struct uart_8250_port *up = (struct uart_8250_port *)port;
1528 unsigned long flags;
1530 spin_lock_irqsave(&up->port.lock, flags);
1531 if (break_state == -1)
1532 up->lcr |= UART_LCR_SBC;
1533 else
1534 up->lcr &= ~UART_LCR_SBC;
1535 serial_out(up, UART_LCR, up->lcr);
1536 spin_unlock_irqrestore(&up->port.lock, flags);
1539 static int serial8250_startup(struct uart_port *port)
1541 struct uart_8250_port *up = (struct uart_8250_port *)port;
1542 unsigned long flags;
1543 unsigned char lsr, iir;
1544 int retval;
1546 up->capabilities = uart_config[up->port.type].flags;
1547 up->mcr = 0;
1549 if (up->port.type == PORT_16C950) {
1550 /* Wake up and initialize UART */
1551 up->acr = 0;
1552 serial_outp(up, UART_LCR, 0xBF);
1553 serial_outp(up, UART_EFR, UART_EFR_ECB);
1554 serial_outp(up, UART_IER, 0);
1555 serial_outp(up, UART_LCR, 0);
1556 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1557 serial_outp(up, UART_LCR, 0xBF);
1558 serial_outp(up, UART_EFR, UART_EFR_ECB);
1559 serial_outp(up, UART_LCR, 0);
1562 #ifdef CONFIG_SERIAL_8250_RSA
1563 /*
1564 * If this is an RSA port, see if we can kick it up to the
1565 * higher speed clock.
1566 */
1567 enable_rsa(up);
1568 #endif
1570 /*
1571 * Clear the FIFO buffers and disable them.
1572 * (they will be reenabled in set_termios())
1573 */
1574 serial8250_clear_fifos(up);
1576 /*
1577 * Clear the interrupt registers.
1578 */
1579 (void) serial_inp(up, UART_LSR);
1580 (void) serial_inp(up, UART_RX);
1581 (void) serial_inp(up, UART_IIR);
1582 (void) serial_inp(up, UART_MSR);
1584 /*
1585 * At this point, there's no way the LSR could still be 0xff;
1586 * if it is, then bail out, because there's likely no UART
1587 * here.
1588 */
1589 if (!(up->port.flags & UPF_BUGGY_UART) &&
1590 (serial_inp(up, UART_LSR) == 0xff)) {
1591 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1592 return -ENODEV;
1595 /*
1596 * For a XR16C850, we need to set the trigger levels
1597 */
1598 if (up->port.type == PORT_16850) {
1599 unsigned char fctr;
1601 serial_outp(up, UART_LCR, 0xbf);
1603 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1604 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1605 serial_outp(up, UART_TRG, UART_TRG_96);
1606 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1607 serial_outp(up, UART_TRG, UART_TRG_96);
1609 serial_outp(up, UART_LCR, 0);
1612 /*
1613 * If the "interrupt" for this port doesn't correspond with any
1614 * hardware interrupt, we use a timer-based system. The original
1615 * driver used to do this with IRQ0.
1616 */
1617 if (!is_real_interrupt(up->port.irq)) {
1618 unsigned int timeout = up->port.timeout;
1620 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1622 up->timer.data = (unsigned long)up;
1623 mod_timer(&up->timer, jiffies + timeout);
1624 } else {
1625 retval = serial_link_irq_chain(up);
1626 if (retval)
1627 return retval;
1630 /*
1631 * Now, initialize the UART
1632 */
1633 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1635 spin_lock_irqsave(&up->port.lock, flags);
1636 if (up->port.flags & UPF_FOURPORT) {
1637 if (!is_real_interrupt(up->port.irq))
1638 up->port.mctrl |= TIOCM_OUT1;
1639 } else
1640 /*
1641 * Most PC uarts need OUT2 raised to enable interrupts.
1642 */
1643 if (is_real_interrupt(up->port.irq))
1644 up->port.mctrl |= TIOCM_OUT2;
1646 serial8250_set_mctrl(&up->port, up->port.mctrl);
1648 /*
1649 * Do a quick test to see if we receive an
1650 * interrupt when we enable the TX irq.
1651 */
1652 serial_outp(up, UART_IER, UART_IER_THRI);
1653 lsr = serial_in(up, UART_LSR);
1654 iir = serial_in(up, UART_IIR);
1655 serial_outp(up, UART_IER, 0);
1657 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1658 if (!(up->bugs & UART_BUG_TXEN)) {
1659 up->bugs |= UART_BUG_TXEN;
1660 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1661 port->line);
1663 } else {
1664 up->bugs &= ~UART_BUG_TXEN;
1667 spin_unlock_irqrestore(&up->port.lock, flags);
1669 /*
1670 * Finally, enable interrupts. Note: Modem status interrupts
1671 * are set via set_termios(), which will be occurring imminently
1672 * anyway, so we don't enable them here.
1673 */
1674 up->ier = UART_IER_RLSI | UART_IER_RDI;
1675 serial_outp(up, UART_IER, up->ier);
1677 if (up->port.flags & UPF_FOURPORT) {
1678 unsigned int icp;
1679 /*
1680 * Enable interrupts on the AST Fourport board
1681 */
1682 icp = (up->port.iobase & 0xfe0) | 0x01f;
1683 outb_p(0x80, icp);
1684 (void) inb_p(icp);
1687 /*
1688 * And clear the interrupt registers again for luck.
1689 */
1690 (void) serial_inp(up, UART_LSR);
1691 (void) serial_inp(up, UART_RX);
1692 (void) serial_inp(up, UART_IIR);
1693 (void) serial_inp(up, UART_MSR);
1695 return 0;
1698 static void serial8250_shutdown(struct uart_port *port)
1700 struct uart_8250_port *up = (struct uart_8250_port *)port;
1701 unsigned long flags;
1703 /*
1704 * Disable interrupts from this port
1705 */
1706 up->ier = 0;
1707 serial_outp(up, UART_IER, 0);
1709 spin_lock_irqsave(&up->port.lock, flags);
1710 if (up->port.flags & UPF_FOURPORT) {
1711 /* reset interrupts on the AST Fourport board */
1712 inb((up->port.iobase & 0xfe0) | 0x1f);
1713 up->port.mctrl |= TIOCM_OUT1;
1714 } else
1715 up->port.mctrl &= ~TIOCM_OUT2;
1717 serial8250_set_mctrl(&up->port, up->port.mctrl);
1718 spin_unlock_irqrestore(&up->port.lock, flags);
1720 /*
1721 * Disable break condition and FIFOs
1722 */
1723 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1724 serial8250_clear_fifos(up);
1726 #ifdef CONFIG_SERIAL_8250_RSA
1727 /*
1728 * Reset the RSA board back to 115kbps compat mode.
1729 */
1730 disable_rsa(up);
1731 #endif
1733 /*
1734 * Read data port to reset things, and then unlink from
1735 * the IRQ chain.
1736 */
1737 (void) serial_in(up, UART_RX);
1739 if (!is_real_interrupt(up->port.irq))
1740 del_timer_sync(&up->timer);
1741 else
1742 serial_unlink_irq_chain(up);
1745 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1747 unsigned int quot;
1749 /*
1750 * Handle magic divisors for baud rates above baud_base on
1751 * SMSC SuperIO chips.
1752 */
1753 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1754 baud == (port->uartclk/4))
1755 quot = 0x8001;
1756 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1757 baud == (port->uartclk/8))
1758 quot = 0x8002;
1759 else
1760 quot = uart_get_divisor(port, baud);
1762 return quot;
1765 static void
1766 serial8250_set_termios(struct uart_port *port, struct termios *termios,
1767 struct termios *old)
1769 struct uart_8250_port *up = (struct uart_8250_port *)port;
1770 unsigned char cval, fcr = 0;
1771 unsigned long flags;
1772 unsigned int baud, quot;
1774 switch (termios->c_cflag & CSIZE) {
1775 case CS5:
1776 cval = UART_LCR_WLEN5;
1777 break;
1778 case CS6:
1779 cval = UART_LCR_WLEN6;
1780 break;
1781 case CS7:
1782 cval = UART_LCR_WLEN7;
1783 break;
1784 default:
1785 case CS8:
1786 cval = UART_LCR_WLEN8;
1787 break;
1790 if (termios->c_cflag & CSTOPB)
1791 cval |= UART_LCR_STOP;
1792 if (termios->c_cflag & PARENB)
1793 cval |= UART_LCR_PARITY;
1794 if (!(termios->c_cflag & PARODD))
1795 cval |= UART_LCR_EPAR;
1796 #ifdef CMSPAR
1797 if (termios->c_cflag & CMSPAR)
1798 cval |= UART_LCR_SPAR;
1799 #endif
1801 /*
1802 * Ask the core to calculate the divisor for us.
1803 */
1804 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1805 quot = serial8250_get_divisor(port, baud);
1807 /*
1808 * Oxford Semi 952 rev B workaround
1809 */
1810 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1811 quot ++;
1813 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1814 if (baud < 2400)
1815 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1816 else
1817 fcr = uart_config[up->port.type].fcr;
1820 /*
1821 * MCR-based auto flow control. When AFE is enabled, RTS will be
1822 * deasserted when the receive FIFO contains more characters than
1823 * the trigger, or the MCR RTS bit is cleared. In the case where
1824 * the remote UART is not using CTS auto flow control, we must
1825 * have sufficient FIFO entries for the latency of the remote
1826 * UART to respond. IOW, at least 32 bytes of FIFO.
1827 */
1828 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1829 up->mcr &= ~UART_MCR_AFE;
1830 if (termios->c_cflag & CRTSCTS)
1831 up->mcr |= UART_MCR_AFE;
1834 /*
1835 * Ok, we're now changing the port state. Do it with
1836 * interrupts disabled.
1837 */
1838 spin_lock_irqsave(&up->port.lock, flags);
1840 /*
1841 * Update the per-port timeout.
1842 */
1843 uart_update_timeout(port, termios->c_cflag, baud);
1845 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1846 if (termios->c_iflag & INPCK)
1847 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1848 if (termios->c_iflag & (BRKINT | PARMRK))
1849 up->port.read_status_mask |= UART_LSR_BI;
1851 /*
1852 * Characteres to ignore
1853 */
1854 up->port.ignore_status_mask = 0;
1855 if (termios->c_iflag & IGNPAR)
1856 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1857 if (termios->c_iflag & IGNBRK) {
1858 up->port.ignore_status_mask |= UART_LSR_BI;
1859 /*
1860 * If we're ignoring parity and break indicators,
1861 * ignore overruns too (for real raw support).
1862 */
1863 if (termios->c_iflag & IGNPAR)
1864 up->port.ignore_status_mask |= UART_LSR_OE;
1867 /*
1868 * ignore all characters if CREAD is not set
1869 */
1870 if ((termios->c_cflag & CREAD) == 0)
1871 up->port.ignore_status_mask |= UART_LSR_DR;
1873 /*
1874 * CTS flow control flag and modem status interrupts
1875 */
1876 up->ier &= ~UART_IER_MSI;
1877 if (!(up->bugs & UART_BUG_NOMSR) &&
1878 UART_ENABLE_MS(&up->port, termios->c_cflag))
1879 up->ier |= UART_IER_MSI;
1880 if (up->capabilities & UART_CAP_UUE)
1881 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1883 serial_out(up, UART_IER, up->ier);
1885 if (up->capabilities & UART_CAP_EFR) {
1886 unsigned char efr = 0;
1887 /*
1888 * TI16C752/Startech hardware flow control. FIXME:
1889 * - TI16C752 requires control thresholds to be set.
1890 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1891 */
1892 if (termios->c_cflag & CRTSCTS)
1893 efr |= UART_EFR_CTS;
1895 serial_outp(up, UART_LCR, 0xBF);
1896 serial_outp(up, UART_EFR, efr);
1899 if (up->capabilities & UART_NATSEMI) {
1900 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1901 serial_outp(up, UART_LCR, 0xe0);
1902 } else {
1903 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1906 serial_dl_write(up, quot);
1908 /*
1909 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1910 * is written without DLAB set, this mode will be disabled.
1911 */
1912 if (up->port.type == PORT_16750)
1913 serial_outp(up, UART_FCR, fcr);
1915 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1916 up->lcr = cval; /* Save LCR */
1917 if (up->port.type != PORT_16750) {
1918 if (fcr & UART_FCR_ENABLE_FIFO) {
1919 /* emulated UARTs (Lucent Venus 167x) need two steps */
1920 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1922 serial_outp(up, UART_FCR, fcr); /* set fcr */
1924 serial8250_set_mctrl(&up->port, up->port.mctrl);
1925 spin_unlock_irqrestore(&up->port.lock, flags);
1928 static void
1929 serial8250_pm(struct uart_port *port, unsigned int state,
1930 unsigned int oldstate)
1932 struct uart_8250_port *p = (struct uart_8250_port *)port;
1934 serial8250_set_sleep(p, state != 0);
1936 if (p->pm)
1937 p->pm(port, state, oldstate);
1940 /*
1941 * Resource handling.
1942 */
1943 static int serial8250_request_std_resource(struct uart_8250_port *up)
1945 unsigned int size = 8 << up->port.regshift;
1946 int ret = 0;
1948 switch (up->port.iotype) {
1949 case UPIO_AU:
1950 size = 0x100000;
1951 /* fall thru */
1952 case UPIO_MEM:
1953 if (!up->port.mapbase)
1954 break;
1956 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1957 ret = -EBUSY;
1958 break;
1961 if (up->port.flags & UPF_IOREMAP) {
1962 up->port.membase = ioremap(up->port.mapbase, size);
1963 if (!up->port.membase) {
1964 release_mem_region(up->port.mapbase, size);
1965 ret = -ENOMEM;
1968 break;
1970 case UPIO_HUB6:
1971 case UPIO_PORT:
1972 if (!request_region(up->port.iobase, size, "serial"))
1973 ret = -EBUSY;
1974 break;
1976 return ret;
1979 static void serial8250_release_std_resource(struct uart_8250_port *up)
1981 unsigned int size = 8 << up->port.regshift;
1983 switch (up->port.iotype) {
1984 case UPIO_AU:
1985 size = 0x100000;
1986 /* fall thru */
1987 case UPIO_MEM:
1988 if (!up->port.mapbase)
1989 break;
1991 if (up->port.flags & UPF_IOREMAP) {
1992 iounmap(up->port.membase);
1993 up->port.membase = NULL;
1996 release_mem_region(up->port.mapbase, size);
1997 break;
1999 case UPIO_HUB6:
2000 case UPIO_PORT:
2001 release_region(up->port.iobase, size);
2002 break;
2006 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2008 unsigned long start = UART_RSA_BASE << up->port.regshift;
2009 unsigned int size = 8 << up->port.regshift;
2010 int ret = 0;
2012 switch (up->port.iotype) {
2013 case UPIO_MEM:
2014 ret = -EINVAL;
2015 break;
2017 case UPIO_HUB6:
2018 case UPIO_PORT:
2019 start += up->port.iobase;
2020 if (!request_region(start, size, "serial-rsa"))
2021 ret = -EBUSY;
2022 break;
2025 return ret;
2028 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2030 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2031 unsigned int size = 8 << up->port.regshift;
2033 switch (up->port.iotype) {
2034 case UPIO_MEM:
2035 break;
2037 case UPIO_HUB6:
2038 case UPIO_PORT:
2039 release_region(up->port.iobase + offset, size);
2040 break;
2044 static void serial8250_release_port(struct uart_port *port)
2046 struct uart_8250_port *up = (struct uart_8250_port *)port;
2048 serial8250_release_std_resource(up);
2049 if (up->port.type == PORT_RSA)
2050 serial8250_release_rsa_resource(up);
2053 static int serial8250_request_port(struct uart_port *port)
2055 struct uart_8250_port *up = (struct uart_8250_port *)port;
2056 int ret = 0;
2058 ret = serial8250_request_std_resource(up);
2059 if (ret == 0 && up->port.type == PORT_RSA) {
2060 ret = serial8250_request_rsa_resource(up);
2061 if (ret < 0)
2062 serial8250_release_std_resource(up);
2065 return ret;
2068 static void serial8250_config_port(struct uart_port *port, int flags)
2070 struct uart_8250_port *up = (struct uart_8250_port *)port;
2071 int probeflags = PROBE_ANY;
2072 int ret;
2074 /*
2075 * Find the region that we can probe for. This in turn
2076 * tells us whether we can probe for the type of port.
2077 */
2078 ret = serial8250_request_std_resource(up);
2079 if (ret < 0)
2080 return;
2082 ret = serial8250_request_rsa_resource(up);
2083 if (ret < 0)
2084 probeflags &= ~PROBE_RSA;
2086 if (flags & UART_CONFIG_TYPE)
2087 autoconfig(up, probeflags);
2088 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2089 autoconfig_irq(up);
2091 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2092 serial8250_release_rsa_resource(up);
2093 if (up->port.type == PORT_UNKNOWN)
2094 serial8250_release_std_resource(up);
2097 static int
2098 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2100 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2101 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2102 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2103 ser->type == PORT_STARTECH)
2104 return -EINVAL;
2105 return 0;
2108 static const char *
2109 serial8250_type(struct uart_port *port)
2111 int type = port->type;
2113 if (type >= ARRAY_SIZE(uart_config))
2114 type = 0;
2115 return uart_config[type].name;
2118 static struct uart_ops serial8250_pops = {
2119 .tx_empty = serial8250_tx_empty,
2120 .set_mctrl = serial8250_set_mctrl,
2121 .get_mctrl = serial8250_get_mctrl,
2122 .stop_tx = serial8250_stop_tx,
2123 .start_tx = serial8250_start_tx,
2124 .stop_rx = serial8250_stop_rx,
2125 .enable_ms = serial8250_enable_ms,
2126 .break_ctl = serial8250_break_ctl,
2127 .startup = serial8250_startup,
2128 .shutdown = serial8250_shutdown,
2129 .set_termios = serial8250_set_termios,
2130 .pm = serial8250_pm,
2131 .type = serial8250_type,
2132 .release_port = serial8250_release_port,
2133 .request_port = serial8250_request_port,
2134 .config_port = serial8250_config_port,
2135 .verify_port = serial8250_verify_port,
2136 };
2138 static struct uart_8250_port serial8250_ports[UART_NR];
2140 static void __init serial8250_isa_init_ports(void)
2142 struct uart_8250_port *up;
2143 static int first = 1;
2144 int i;
2146 if (!first)
2147 return;
2148 first = 0;
2150 for (i = 0; i < nr_uarts; i++) {
2151 struct uart_8250_port *up = &serial8250_ports[i];
2153 up->port.line = i;
2154 spin_lock_init(&up->port.lock);
2156 init_timer(&up->timer);
2157 up->timer.function = serial8250_timeout;
2159 /*
2160 * ALPHA_KLUDGE_MCR needs to be killed.
2161 */
2162 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2163 up->mcr_force = ALPHA_KLUDGE_MCR;
2165 up->port.ops = &serial8250_pops;
2168 for (i = 0, up = serial8250_ports;
2169 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2170 i++, up++) {
2171 up->port.iobase = old_serial_port[i].port;
2172 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2173 up->port.uartclk = old_serial_port[i].baud_base * 16;
2174 up->port.flags = old_serial_port[i].flags;
2175 up->port.hub6 = old_serial_port[i].hub6;
2176 up->port.membase = old_serial_port[i].iomem_base;
2177 up->port.iotype = old_serial_port[i].io_type;
2178 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2179 if (share_irqs)
2180 up->port.flags |= UPF_SHARE_IRQ;
2184 static void __init
2185 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2187 int i;
2189 serial8250_isa_init_ports();
2191 for (i = 0; i < nr_uarts; i++) {
2192 struct uart_8250_port *up = &serial8250_ports[i];
2194 up->port.dev = dev;
2195 uart_add_one_port(drv, &up->port);
2199 #ifdef CONFIG_SERIAL_8250_CONSOLE
2201 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2203 /*
2204 * Wait for transmitter & holding register to empty
2205 */
2206 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
2208 unsigned int status, tmout = 10000;
2210 /* Wait up to 10ms for the character(s) to be sent. */
2211 do {
2212 status = serial_in(up, UART_LSR);
2214 if (status & UART_LSR_BI)
2215 up->lsr_break_flag = UART_LSR_BI;
2217 if (--tmout == 0)
2218 break;
2219 udelay(1);
2220 } while ((status & bits) != bits);
2222 /* Wait up to 1s for flow control if necessary */
2223 if (up->port.flags & UPF_CONS_FLOW) {
2224 tmout = 1000000;
2225 while (--tmout &&
2226 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2227 udelay(1);
2231 static void serial8250_console_putchar(struct uart_port *port, int ch)
2233 struct uart_8250_port *up = (struct uart_8250_port *)port;
2235 wait_for_xmitr(up, UART_LSR_THRE);
2236 serial_out(up, UART_TX, ch);
2239 /*
2240 * Print a string to the serial port trying not to disturb
2241 * any possible real use of the port...
2243 * The console_lock must be held when we get here.
2244 */
2245 static void
2246 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2248 struct uart_8250_port *up = &serial8250_ports[co->index];
2249 unsigned long flags;
2250 unsigned int ier;
2251 int locked = 1;
2253 touch_nmi_watchdog();
2255 local_irq_save(flags);
2256 if (up->port.sysrq) {
2257 /* serial8250_handle_port() already took the lock */
2258 locked = 0;
2259 } else if (oops_in_progress) {
2260 locked = spin_trylock(&up->port.lock);
2261 } else
2262 spin_lock(&up->port.lock);
2264 /*
2265 * First save the IER then disable the interrupts
2266 */
2267 ier = serial_in(up, UART_IER);
2269 if (up->capabilities & UART_CAP_UUE)
2270 serial_out(up, UART_IER, UART_IER_UUE);
2271 else
2272 serial_out(up, UART_IER, 0);
2274 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2276 /*
2277 * Finally, wait for transmitter to become empty
2278 * and restore the IER
2279 */
2280 wait_for_xmitr(up, BOTH_EMPTY);
2281 serial_out(up, UART_IER, ier);
2283 if (locked)
2284 spin_unlock(&up->port.lock);
2285 local_irq_restore(flags);
2288 static int serial8250_console_setup(struct console *co, char *options)
2290 struct uart_port *port;
2291 int baud = 9600;
2292 int bits = 8;
2293 int parity = 'n';
2294 int flow = 'n';
2296 /*
2297 * Check whether an invalid uart number has been specified, and
2298 * if so, search for the first available port that does have
2299 * console support.
2300 */
2301 if (co->index >= nr_uarts)
2302 co->index = 0;
2303 port = &serial8250_ports[co->index].port;
2304 if (!port->iobase && !port->membase)
2305 return -ENODEV;
2307 if (options)
2308 uart_parse_options(options, &baud, &parity, &bits, &flow);
2310 return uart_set_options(port, co, baud, parity, bits, flow);
2313 static struct uart_driver serial8250_reg;
2314 static struct console serial8250_console = {
2315 .name = "ttyS",
2316 .write = serial8250_console_write,
2317 .device = uart_console_device,
2318 .setup = serial8250_console_setup,
2319 .flags = CON_PRINTBUFFER,
2320 .index = -1,
2321 .data = &serial8250_reg,
2322 };
2324 static int __init serial8250_console_init(void)
2326 serial8250_isa_init_ports();
2327 register_console(&serial8250_console);
2328 return 0;
2330 console_initcall(serial8250_console_init);
2332 static int __init find_port(struct uart_port *p)
2334 int line;
2335 struct uart_port *port;
2337 for (line = 0; line < nr_uarts; line++) {
2338 port = &serial8250_ports[line].port;
2339 if (uart_match_port(p, port))
2340 return line;
2342 return -ENODEV;
2345 int __init serial8250_start_console(struct uart_port *port, char *options)
2347 int line;
2349 line = find_port(port);
2350 if (line < 0)
2351 return -ENODEV;
2353 add_preferred_console("ttyS", line, options);
2354 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2355 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2356 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2357 (unsigned long) port->iobase, options);
2358 if (!(serial8250_console.flags & CON_ENABLED)) {
2359 serial8250_console.flags &= ~CON_PRINTBUFFER;
2360 register_console(&serial8250_console);
2362 return line;
2365 #define SERIAL8250_CONSOLE &serial8250_console
2366 #else
2367 #define SERIAL8250_CONSOLE NULL
2368 #endif
2370 static struct uart_driver serial8250_reg = {
2371 .owner = THIS_MODULE,
2372 .driver_name = "serial",
2373 .dev_name = "ttyS",
2374 .major = TTY_MAJOR,
2375 .minor = 64,
2376 .nr = UART_NR,
2377 .cons = SERIAL8250_CONSOLE,
2378 };
2380 /*
2381 * early_serial_setup - early registration for 8250 ports
2383 * Setup an 8250 port structure prior to console initialisation. Use
2384 * after console initialisation will cause undefined behaviour.
2385 */
2386 int __init early_serial_setup(struct uart_port *port)
2388 if (port->line >= ARRAY_SIZE(serial8250_ports))
2389 return -ENODEV;
2391 serial8250_isa_init_ports();
2392 serial8250_ports[port->line].port = *port;
2393 serial8250_ports[port->line].port.ops = &serial8250_pops;
2394 return 0;
2397 /**
2398 * serial8250_suspend_port - suspend one serial port
2399 * @line: serial line number
2400 * @level: the level of port suspension, as per uart_suspend_port
2402 * Suspend one serial port.
2403 */
2404 void serial8250_suspend_port(int line)
2406 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2409 /**
2410 * serial8250_resume_port - resume one serial port
2411 * @line: serial line number
2412 * @level: the level of port resumption, as per uart_resume_port
2414 * Resume one serial port.
2415 */
2416 void serial8250_resume_port(int line)
2418 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2421 /*
2422 * Register a set of serial devices attached to a platform device. The
2423 * list is terminated with a zero flags entry, which means we expect
2424 * all entries to have at least UPF_BOOT_AUTOCONF set.
2425 */
2426 static int __devinit serial8250_probe(struct platform_device *dev)
2428 struct plat_serial8250_port *p = dev->dev.platform_data;
2429 struct uart_port port;
2430 int ret, i;
2432 memset(&port, 0, sizeof(struct uart_port));
2434 for (i = 0; p && p->flags != 0; p++, i++) {
2435 port.iobase = p->iobase;
2436 port.membase = p->membase;
2437 port.irq = p->irq;
2438 port.uartclk = p->uartclk;
2439 port.regshift = p->regshift;
2440 port.iotype = p->iotype;
2441 port.flags = p->flags;
2442 port.mapbase = p->mapbase;
2443 port.hub6 = p->hub6;
2444 port.dev = &dev->dev;
2445 if (share_irqs)
2446 port.flags |= UPF_SHARE_IRQ;
2447 ret = serial8250_register_port(&port);
2448 if (ret < 0) {
2449 dev_err(&dev->dev, "unable to register port at index %d "
2450 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2451 p->iobase, p->mapbase, p->irq, ret);
2454 return 0;
2457 /*
2458 * Remove serial ports registered against a platform device.
2459 */
2460 static int __devexit serial8250_remove(struct platform_device *dev)
2462 int i;
2464 for (i = 0; i < nr_uarts; i++) {
2465 struct uart_8250_port *up = &serial8250_ports[i];
2467 if (up->port.dev == &dev->dev)
2468 serial8250_unregister_port(i);
2470 return 0;
2473 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2475 int i;
2477 for (i = 0; i < UART_NR; i++) {
2478 struct uart_8250_port *up = &serial8250_ports[i];
2480 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2481 uart_suspend_port(&serial8250_reg, &up->port);
2484 return 0;
2487 static int serial8250_resume(struct platform_device *dev)
2489 int i;
2491 for (i = 0; i < UART_NR; i++) {
2492 struct uart_8250_port *up = &serial8250_ports[i];
2494 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2495 uart_resume_port(&serial8250_reg, &up->port);
2498 return 0;
2501 static struct platform_driver serial8250_isa_driver = {
2502 .probe = serial8250_probe,
2503 .remove = __devexit_p(serial8250_remove),
2504 .suspend = serial8250_suspend,
2505 .resume = serial8250_resume,
2506 .driver = {
2507 .name = "serial8250",
2508 .owner = THIS_MODULE,
2509 },
2510 };
2512 /*
2513 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2514 * in the table in include/asm/serial.h
2515 */
2516 static struct platform_device *serial8250_isa_devs;
2518 /*
2519 * serial8250_register_port and serial8250_unregister_port allows for
2520 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2521 * modems and PCI multiport cards.
2522 */
2523 static DEFINE_MUTEX(serial_mutex);
2525 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2527 int i;
2529 /*
2530 * First, find a port entry which matches.
2531 */
2532 for (i = 0; i < nr_uarts; i++)
2533 if (uart_match_port(&serial8250_ports[i].port, port))
2534 return &serial8250_ports[i];
2536 /*
2537 * We didn't find a matching entry, so look for the first
2538 * free entry. We look for one which hasn't been previously
2539 * used (indicated by zero iobase).
2540 */
2541 for (i = 0; i < nr_uarts; i++)
2542 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2543 serial8250_ports[i].port.iobase == 0)
2544 return &serial8250_ports[i];
2546 /*
2547 * That also failed. Last resort is to find any entry which
2548 * doesn't have a real port associated with it.
2549 */
2550 for (i = 0; i < nr_uarts; i++)
2551 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2552 return &serial8250_ports[i];
2554 return NULL;
2557 /**
2558 * serial8250_register_port - register a serial port
2559 * @port: serial port template
2561 * Configure the serial port specified by the request. If the
2562 * port exists and is in use, it is hung up and unregistered
2563 * first.
2565 * The port is then probed and if necessary the IRQ is autodetected
2566 * If this fails an error is returned.
2568 * On success the port is ready to use and the line number is returned.
2569 */
2570 int serial8250_register_port(struct uart_port *port)
2572 struct uart_8250_port *uart;
2573 int ret = -ENOSPC;
2575 if (port->uartclk == 0)
2576 return -EINVAL;
2578 mutex_lock(&serial_mutex);
2580 uart = serial8250_find_match_or_unused(port);
2581 if (uart) {
2582 uart_remove_one_port(&serial8250_reg, &uart->port);
2584 uart->port.iobase = port->iobase;
2585 uart->port.membase = port->membase;
2586 uart->port.irq = port->irq;
2587 uart->port.uartclk = port->uartclk;
2588 uart->port.fifosize = port->fifosize;
2589 uart->port.regshift = port->regshift;
2590 uart->port.iotype = port->iotype;
2591 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2592 uart->port.mapbase = port->mapbase;
2593 if (port->dev)
2594 uart->port.dev = port->dev;
2596 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2597 if (ret == 0)
2598 ret = uart->port.line;
2600 mutex_unlock(&serial_mutex);
2602 return ret;
2604 EXPORT_SYMBOL(serial8250_register_port);
2606 /**
2607 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2608 * @line: serial line number
2610 * Remove one serial port. This may not be called from interrupt
2611 * context. We hand the port back to the our control.
2612 */
2613 void serial8250_unregister_port(int line)
2615 struct uart_8250_port *uart = &serial8250_ports[line];
2617 mutex_lock(&serial_mutex);
2618 uart_remove_one_port(&serial8250_reg, &uart->port);
2619 if (serial8250_isa_devs) {
2620 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2621 uart->port.type = PORT_UNKNOWN;
2622 uart->port.dev = &serial8250_isa_devs->dev;
2623 uart_add_one_port(&serial8250_reg, &uart->port);
2624 } else {
2625 uart->port.dev = NULL;
2627 mutex_unlock(&serial_mutex);
2629 EXPORT_SYMBOL(serial8250_unregister_port);
2631 static int __init serial8250_init(void)
2633 int ret, i;
2635 if (nr_uarts > UART_NR)
2636 nr_uarts = UART_NR;
2638 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2639 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2640 share_irqs ? "en" : "dis");
2642 for (i = 0; i < NR_IRQS; i++)
2643 spin_lock_init(&irq_lists[i].lock);
2645 ret = uart_register_driver(&serial8250_reg);
2646 if (ret)
2647 goto out;
2649 serial8250_isa_devs = platform_device_alloc("serial8250",
2650 PLAT8250_DEV_LEGACY);
2651 if (!serial8250_isa_devs) {
2652 ret = -ENOMEM;
2653 goto unreg_uart_drv;
2656 ret = platform_device_add(serial8250_isa_devs);
2657 if (ret)
2658 goto put_dev;
2660 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2662 ret = platform_driver_register(&serial8250_isa_driver);
2663 if (ret == 0)
2664 goto out;
2666 platform_device_del(serial8250_isa_devs);
2667 put_dev:
2668 platform_device_put(serial8250_isa_devs);
2669 unreg_uart_drv:
2670 uart_unregister_driver(&serial8250_reg);
2671 out:
2672 return ret;
2675 static void __exit serial8250_exit(void)
2677 struct platform_device *isa_dev = serial8250_isa_devs;
2679 /*
2680 * This tells serial8250_unregister_port() not to re-register
2681 * the ports (thereby making serial8250_isa_driver permanently
2682 * in use.)
2683 */
2684 serial8250_isa_devs = NULL;
2686 platform_driver_unregister(&serial8250_isa_driver);
2687 platform_device_unregister(isa_dev);
2689 uart_unregister_driver(&serial8250_reg);
2692 module_init(serial8250_init);
2693 module_exit(serial8250_exit);
2695 EXPORT_SYMBOL(serial8250_suspend_port);
2696 EXPORT_SYMBOL(serial8250_resume_port);
2698 MODULE_LICENSE("GPL");
2699 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2701 module_param(share_irqs, uint, 0644);
2702 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2703 " (unsafe)");
2705 module_param(nr_uarts, uint, 0644);
2706 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2708 #ifdef CONFIG_SERIAL_8250_RSA
2709 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2710 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2711 #endif
2712 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);