ia64/linux-2.6.18-xen.hg

view drivers/pci/msi-apic.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * MSI hooks for standard x86 apic
3 */
5 #include <linux/pci.h>
6 #include <linux/irq.h>
7 #include <asm/smp.h>
9 #include "msi.h"
11 /*
12 * Shifts for APIC-based data
13 */
15 #define MSI_DATA_VECTOR_SHIFT 0
16 #define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
18 #define MSI_DATA_DELIVERY_SHIFT 8
19 #define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
20 #define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
22 #define MSI_DATA_LEVEL_SHIFT 14
23 #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
24 #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
26 #define MSI_DATA_TRIGGER_SHIFT 15
27 #define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
28 #define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
30 /*
31 * Shift/mask fields for APIC-based bus address
32 */
34 #define MSI_ADDR_HEADER 0xfee00000
36 #define MSI_ADDR_DESTID_MASK 0xfff0000f
37 #define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
39 #define MSI_ADDR_DESTMODE_SHIFT 2
40 #define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
41 #define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
43 #define MSI_ADDR_REDIRECTION_SHIFT 3
44 #define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
45 #define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
48 static void
49 msi_target_apic(unsigned int vector,
50 unsigned int dest_cpu,
51 u32 *address_hi, /* in/out */
52 u32 *address_lo) /* in/out */
53 {
54 u32 addr = *address_lo;
56 addr &= MSI_ADDR_DESTID_MASK;
57 addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(dest_cpu));
59 *address_lo = addr;
60 }
62 static int
63 msi_setup_apic(struct pci_dev *pdev, /* unused in generic */
64 unsigned int vector,
65 u32 *address_hi,
66 u32 *address_lo,
67 u32 *data)
68 {
69 unsigned long dest_phys_id;
71 dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
73 *address_hi = 0;
74 *address_lo = MSI_ADDR_HEADER |
75 MSI_ADDR_DESTMODE_PHYS |
76 MSI_ADDR_REDIRECTION_CPU |
77 MSI_ADDR_DESTID_CPU(dest_phys_id);
79 *data = MSI_DATA_TRIGGER_EDGE |
80 MSI_DATA_LEVEL_ASSERT |
81 MSI_DATA_DELIVERY_FIXED |
82 MSI_DATA_VECTOR(vector);
84 return 0;
85 }
87 static void
88 msi_teardown_apic(unsigned int vector)
89 {
90 return; /* no-op */
91 }
93 /*
94 * Generic ops used on most IA archs/platforms. Set with msi_register()
95 */
97 struct msi_ops msi_apic_ops = {
98 .setup = msi_setup_apic,
99 .teardown = msi_teardown_apic,
100 .target = msi_target_apic,
101 };