ia64/linux-2.6.18-xen.hg

view drivers/net/via-velocity.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 */
25 #ifndef VELOCITY_H
26 #define VELOCITY_H
28 #define VELOCITY_TX_CSUM_SUPPORT
30 #define VELOCITY_NAME "via-velocity"
31 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
32 #define VELOCITY_VERSION "1.13"
34 #define VELOCITY_IO_SIZE 256
36 #define PKT_BUF_SZ 1540
38 #define MAX_UNITS 8
39 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
41 #define REV_ID_VT6110 (0)
43 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
44 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
45 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
47 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
48 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
49 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
51 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
52 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
53 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
55 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
56 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
57 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
59 #define VAR_USED(p) do {(p)=(p);} while (0)
61 /*
62 * Purpose: Structures for MAX RX/TX descriptors.
63 */
66 #define B_OWNED_BY_CHIP 1
67 #define B_OWNED_BY_HOST 0
69 /*
70 * Bits in the RSR0 register
71 */
73 #define RSR_DETAG 0x0080
74 #define RSR_SNTAG 0x0040
75 #define RSR_RXER 0x0020
76 #define RSR_RL 0x0010
77 #define RSR_CE 0x0008
78 #define RSR_FAE 0x0004
79 #define RSR_CRC 0x0002
80 #define RSR_VIDM 0x0001
82 /*
83 * Bits in the RSR1 register
84 */
86 #define RSR_RXOK 0x8000 // rx OK
87 #define RSR_PFT 0x4000 // Perfect filtering address match
88 #define RSR_MAR 0x2000 // MAC accept multicast address packet
89 #define RSR_BAR 0x1000 // MAC accept broadcast address packet
90 #define RSR_PHY 0x0800 // MAC accept physical address packet
91 #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
92 #define RSR_STP 0x0200 // start of packet
93 #define RSR_EDP 0x0100 // end of packet
95 /*
96 * Bits in the RSR1 register
97 */
99 #define RSR1_RXOK 0x80 // rx OK
100 #define RSR1_PFT 0x40 // Perfect filtering address match
101 #define RSR1_MAR 0x20 // MAC accept multicast address packet
102 #define RSR1_BAR 0x10 // MAC accept broadcast address packet
103 #define RSR1_PHY 0x08 // MAC accept physical address packet
104 #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
105 #define RSR1_STP 0x02 // start of packet
106 #define RSR1_EDP 0x01 // end of packet
108 /*
109 * Bits in the CSM register
110 */
112 #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
113 #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
114 #define CSM_FRAG 0x10 //Fragment IP datagram
115 #define CSM_IPKT 0x04 //Received an IP packet
116 #define CSM_TCPKT 0x02 //Received a TCP packet
117 #define CSM_UDPKT 0x01 //Received a UDP packet
119 /*
120 * Bits in the TSR0 register
121 */
123 #define TSR0_ABT 0x0080 // Tx abort because of excessive collision
124 #define TSR0_OWT 0x0040 // Jumbo frame Tx abort
125 #define TSR0_OWC 0x0020 // Out of window collision
126 #define TSR0_COLS 0x0010 // experience collision in this transmit event
127 #define TSR0_NCR3 0x0008 // collision retry counter[3]
128 #define TSR0_NCR2 0x0004 // collision retry counter[2]
129 #define TSR0_NCR1 0x0002 // collision retry counter[1]
130 #define TSR0_NCR0 0x0001 // collision retry counter[0]
131 #define TSR0_TERR 0x8000 //
132 #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
133 #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
134 #define TSR0_LNKFL 0x1000 // packet serviced during link down
135 #define TSR0_SHDN 0x0400 // shutdown case
136 #define TSR0_CRS 0x0200 // carrier sense lost
137 #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
139 /*
140 * Bits in the TSR1 register
141 */
143 #define TSR1_TERR 0x80 //
144 #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
145 #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
146 #define TSR1_LNKFL 0x10 // packet serviced during link down
147 #define TSR1_SHDN 0x04 // shutdown case
148 #define TSR1_CRS 0x02 // carrier sense lost
149 #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
151 //
152 // Bits in the TCR0 register
153 //
154 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
155 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
156 #define TCR0_VETAG 0x20 // enable VLAN tag
157 #define TCR0_IPCK 0x10 // request IP checksum calculation.
158 #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
159 #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
160 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
161 #define TCR0_CRC 0x01 // disable CRC generation
163 #define TCPLS_NORMAL 3
164 #define TCPLS_START 2
165 #define TCPLS_END 1
166 #define TCPLS_MED 0
169 // max transmit or receive buffer size
170 #define CB_RX_BUF_SIZE 2048UL // max buffer size
171 // NOTE: must be multiple of 4
173 #define CB_MAX_RD_NUM 512 // MAX # of RD
174 #define CB_MAX_TD_NUM 256 // MAX # of TD
176 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
177 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
179 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
180 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
182 // for 3119
183 #define CB_TD_RING_NUM 4 // # of TD rings.
184 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
187 /*
188 * If collisions excess 15 times , tx will abort, and
189 * if tx fifo underflow, tx will fail
190 * we should try to resend it
191 */
193 #define CB_MAX_TX_ABORT_RETRY 3
195 /*
196 * Receive descriptor
197 */
199 struct rdesc0 {
200 u16 RSR; /* Receive status */
201 u16 len:14; /* Received packet length */
202 u16 reserved:1;
203 u16 owner:1; /* Who owns this buffer ? */
204 };
206 struct rdesc1 {
207 u16 PQTAG;
208 u8 CSM;
209 u8 IPKT;
210 };
212 struct rx_desc {
213 struct rdesc0 rdesc0;
214 struct rdesc1 rdesc1;
215 u32 pa_low; /* Low 32 bit PCI address */
216 u16 pa_high; /* Next 16 bit PCI address (48 total) */
217 u16 len:15; /* Frame size */
218 u16 inten:1; /* Enable interrupt */
219 } __attribute__ ((__packed__));
221 /*
222 * Transmit descriptor
223 */
225 struct tdesc0 {
226 u16 TSR; /* Transmit status register */
227 u16 pktsize:14; /* Size of frame */
228 u16 reserved:1;
229 u16 owner:1; /* Who owns the buffer */
230 };
232 struct pqinf { /* Priority queue info */
233 u16 VID:12;
234 u16 CFI:1;
235 u16 priority:3;
236 } __attribute__ ((__packed__));
238 struct tdesc1 {
239 struct pqinf pqinf;
240 u8 TCR;
241 u8 TCPLS:2;
242 u8 reserved:2;
243 u8 CMDZ:4;
244 } __attribute__ ((__packed__));
246 struct td_buf {
247 u32 pa_low;
248 u16 pa_high;
249 u16 bufsize:14;
250 u16 reserved:1;
251 u16 queue:1;
252 } __attribute__ ((__packed__));
254 struct tx_desc {
255 struct tdesc0 tdesc0;
256 struct tdesc1 tdesc1;
257 struct td_buf td_buf[7];
258 };
260 struct velocity_rd_info {
261 struct sk_buff *skb;
262 dma_addr_t skb_dma;
263 };
265 /**
266 * alloc_rd_info - allocate an rd info block
267 *
268 * Alocate and initialize a receive info structure used for keeping
269 * track of kernel side information related to each receive
270 * descriptor we are using
271 */
273 static inline struct velocity_rd_info *alloc_rd_info(void)
274 {
275 struct velocity_rd_info *ptr;
276 if ((ptr = kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
277 return NULL;
278 else {
279 memset(ptr, 0, sizeof(struct velocity_rd_info));
280 return ptr;
281 }
282 }
284 /*
285 * Used to track transmit side buffers.
286 */
288 struct velocity_td_info {
289 struct sk_buff *skb;
290 u8 *buf;
291 int nskb_dma;
292 dma_addr_t skb_dma[7];
293 dma_addr_t buf_dma;
294 };
296 enum velocity_owner {
297 OWNED_BY_HOST = 0,
298 OWNED_BY_NIC = 1
299 };
302 /*
303 * MAC registers and macros.
304 */
307 #define MCAM_SIZE 64
308 #define VCAM_SIZE 64
309 #define TX_QUEUE_NO 4
311 #define MAX_HW_MIB_COUNTER 32
312 #define VELOCITY_MIN_MTU (64)
313 #define VELOCITY_MAX_MTU (9000)
315 /*
316 * Registers in the MAC
317 */
319 #define MAC_REG_PAR 0x00 // physical address
320 #define MAC_REG_RCR 0x06
321 #define MAC_REG_TCR 0x07
322 #define MAC_REG_CR0_SET 0x08
323 #define MAC_REG_CR1_SET 0x09
324 #define MAC_REG_CR2_SET 0x0A
325 #define MAC_REG_CR3_SET 0x0B
326 #define MAC_REG_CR0_CLR 0x0C
327 #define MAC_REG_CR1_CLR 0x0D
328 #define MAC_REG_CR2_CLR 0x0E
329 #define MAC_REG_CR3_CLR 0x0F
330 #define MAC_REG_MAR 0x10
331 #define MAC_REG_CAM 0x10
332 #define MAC_REG_DEC_BASE_HI 0x18
333 #define MAC_REG_DBF_BASE_HI 0x1C
334 #define MAC_REG_ISR_CTL 0x20
335 #define MAC_REG_ISR_HOTMR 0x20
336 #define MAC_REG_ISR_TSUPTHR 0x20
337 #define MAC_REG_ISR_RSUPTHR 0x20
338 #define MAC_REG_ISR_CTL1 0x21
339 #define MAC_REG_TXE_SR 0x22
340 #define MAC_REG_RXE_SR 0x23
341 #define MAC_REG_ISR 0x24
342 #define MAC_REG_ISR0 0x24
343 #define MAC_REG_ISR1 0x25
344 #define MAC_REG_ISR2 0x26
345 #define MAC_REG_ISR3 0x27
346 #define MAC_REG_IMR 0x28
347 #define MAC_REG_IMR0 0x28
348 #define MAC_REG_IMR1 0x29
349 #define MAC_REG_IMR2 0x2A
350 #define MAC_REG_IMR3 0x2B
351 #define MAC_REG_TDCSR_SET 0x30
352 #define MAC_REG_RDCSR_SET 0x32
353 #define MAC_REG_TDCSR_CLR 0x34
354 #define MAC_REG_RDCSR_CLR 0x36
355 #define MAC_REG_RDBASE_LO 0x38
356 #define MAC_REG_RDINDX 0x3C
357 #define MAC_REG_TDBASE_LO 0x40
358 #define MAC_REG_RDCSIZE 0x50
359 #define MAC_REG_TDCSIZE 0x52
360 #define MAC_REG_TDINDX 0x54
361 #define MAC_REG_TDIDX0 0x54
362 #define MAC_REG_TDIDX1 0x56
363 #define MAC_REG_TDIDX2 0x58
364 #define MAC_REG_TDIDX3 0x5A
365 #define MAC_REG_PAUSE_TIMER 0x5C
366 #define MAC_REG_RBRDU 0x5E
367 #define MAC_REG_FIFO_TEST0 0x60
368 #define MAC_REG_FIFO_TEST1 0x64
369 #define MAC_REG_CAMADDR 0x68
370 #define MAC_REG_CAMCR 0x69
371 #define MAC_REG_GFTEST 0x6A
372 #define MAC_REG_FTSTCMD 0x6B
373 #define MAC_REG_MIICFG 0x6C
374 #define MAC_REG_MIISR 0x6D
375 #define MAC_REG_PHYSR0 0x6E
376 #define MAC_REG_PHYSR1 0x6F
377 #define MAC_REG_MIICR 0x70
378 #define MAC_REG_MIIADR 0x71
379 #define MAC_REG_MIIDATA 0x72
380 #define MAC_REG_SOFT_TIMER0 0x74
381 #define MAC_REG_SOFT_TIMER1 0x76
382 #define MAC_REG_CFGA 0x78
383 #define MAC_REG_CFGB 0x79
384 #define MAC_REG_CFGC 0x7A
385 #define MAC_REG_CFGD 0x7B
386 #define MAC_REG_DCFG0 0x7C
387 #define MAC_REG_DCFG1 0x7D
388 #define MAC_REG_MCFG0 0x7E
389 #define MAC_REG_MCFG1 0x7F
391 #define MAC_REG_TBIST 0x80
392 #define MAC_REG_RBIST 0x81
393 #define MAC_REG_PMCC 0x82
394 #define MAC_REG_STICKHW 0x83
395 #define MAC_REG_MIBCR 0x84
396 #define MAC_REG_EERSV 0x85
397 #define MAC_REG_REVID 0x86
398 #define MAC_REG_MIBREAD 0x88
399 #define MAC_REG_BPMA 0x8C
400 #define MAC_REG_EEWR_DATA 0x8C
401 #define MAC_REG_BPMD_WR 0x8F
402 #define MAC_REG_BPCMD 0x90
403 #define MAC_REG_BPMD_RD 0x91
404 #define MAC_REG_EECHKSUM 0x92
405 #define MAC_REG_EECSR 0x93
406 #define MAC_REG_EERD_DATA 0x94
407 #define MAC_REG_EADDR 0x96
408 #define MAC_REG_EMBCMD 0x97
409 #define MAC_REG_JMPSR0 0x98
410 #define MAC_REG_JMPSR1 0x99
411 #define MAC_REG_JMPSR2 0x9A
412 #define MAC_REG_JMPSR3 0x9B
413 #define MAC_REG_CHIPGSR 0x9C
414 #define MAC_REG_TESTCFG 0x9D
415 #define MAC_REG_DEBUG 0x9E
416 #define MAC_REG_CHIPGCR 0x9F
417 #define MAC_REG_WOLCR0_SET 0xA0
418 #define MAC_REG_WOLCR1_SET 0xA1
419 #define MAC_REG_PWCFG_SET 0xA2
420 #define MAC_REG_WOLCFG_SET 0xA3
421 #define MAC_REG_WOLCR0_CLR 0xA4
422 #define MAC_REG_WOLCR1_CLR 0xA5
423 #define MAC_REG_PWCFG_CLR 0xA6
424 #define MAC_REG_WOLCFG_CLR 0xA7
425 #define MAC_REG_WOLSR0_SET 0xA8
426 #define MAC_REG_WOLSR1_SET 0xA9
427 #define MAC_REG_WOLSR0_CLR 0xAC
428 #define MAC_REG_WOLSR1_CLR 0xAD
429 #define MAC_REG_PATRN_CRC0 0xB0
430 #define MAC_REG_PATRN_CRC1 0xB2
431 #define MAC_REG_PATRN_CRC2 0xB4
432 #define MAC_REG_PATRN_CRC3 0xB6
433 #define MAC_REG_PATRN_CRC4 0xB8
434 #define MAC_REG_PATRN_CRC5 0xBA
435 #define MAC_REG_PATRN_CRC6 0xBC
436 #define MAC_REG_PATRN_CRC7 0xBE
437 #define MAC_REG_BYTEMSK0_0 0xC0
438 #define MAC_REG_BYTEMSK0_1 0xC4
439 #define MAC_REG_BYTEMSK0_2 0xC8
440 #define MAC_REG_BYTEMSK0_3 0xCC
441 #define MAC_REG_BYTEMSK1_0 0xD0
442 #define MAC_REG_BYTEMSK1_1 0xD4
443 #define MAC_REG_BYTEMSK1_2 0xD8
444 #define MAC_REG_BYTEMSK1_3 0xDC
445 #define MAC_REG_BYTEMSK2_0 0xE0
446 #define MAC_REG_BYTEMSK2_1 0xE4
447 #define MAC_REG_BYTEMSK2_2 0xE8
448 #define MAC_REG_BYTEMSK2_3 0xEC
449 #define MAC_REG_BYTEMSK3_0 0xF0
450 #define MAC_REG_BYTEMSK3_1 0xF4
451 #define MAC_REG_BYTEMSK3_2 0xF8
452 #define MAC_REG_BYTEMSK3_3 0xFC
454 /*
455 * Bits in the RCR register
456 */
458 #define RCR_AS 0x80
459 #define RCR_AP 0x40
460 #define RCR_AL 0x20
461 #define RCR_PROM 0x10
462 #define RCR_AB 0x08
463 #define RCR_AM 0x04
464 #define RCR_AR 0x02
465 #define RCR_SEP 0x01
467 /*
468 * Bits in the TCR register
469 */
471 #define TCR_TB2BDIS 0x80
472 #define TCR_COLTMC1 0x08
473 #define TCR_COLTMC0 0x04
474 #define TCR_LB1 0x02 /* loopback[1] */
475 #define TCR_LB0 0x01 /* loopback[0] */
477 /*
478 * Bits in the CR0 register
479 */
481 #define CR0_TXON 0x00000008UL
482 #define CR0_RXON 0x00000004UL
483 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
484 #define CR0_STRT 0x00000001UL /* start MAC */
485 #define CR0_SFRST 0x00008000UL /* software reset */
486 #define CR0_TM1EN 0x00004000UL
487 #define CR0_TM0EN 0x00002000UL
488 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
489 #define CR0_DISAU 0x00000100UL
490 #define CR0_XONEN 0x00800000UL
491 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
492 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
493 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
494 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
495 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
496 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
497 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
498 #define CR0_GSPRST 0x80000000UL
499 #define CR0_FORSRST 0x40000000UL
500 #define CR0_FPHYRST 0x20000000UL
501 #define CR0_DIAG 0x10000000UL
502 #define CR0_INTPCTL 0x04000000UL
503 #define CR0_GINTMSK1 0x02000000UL
504 #define CR0_GINTMSK0 0x01000000UL
506 /*
507 * Bits in the CR1 register
508 */
510 #define CR1_SFRST 0x80 /* software reset */
511 #define CR1_TM1EN 0x40
512 #define CR1_TM0EN 0x20
513 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
514 #define CR1_DISAU 0x01
516 /*
517 * Bits in the CR2 register
518 */
520 #define CR2_XONEN 0x80
521 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
522 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
523 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
524 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
525 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
526 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
527 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
529 /*
530 * Bits in the CR3 register
531 */
533 #define CR3_GSPRST 0x80
534 #define CR3_FORSRST 0x40
535 #define CR3_FPHYRST 0x20
536 #define CR3_DIAG 0x10
537 #define CR3_INTPCTL 0x04
538 #define CR3_GINTMSK1 0x02
539 #define CR3_GINTMSK0 0x01
541 #define ISRCTL_UDPINT 0x8000
542 #define ISRCTL_TSUPDIS 0x4000
543 #define ISRCTL_RSUPDIS 0x2000
544 #define ISRCTL_PMSK1 0x1000
545 #define ISRCTL_PMSK0 0x0800
546 #define ISRCTL_INTPD 0x0400
547 #define ISRCTL_HCRLD 0x0200
548 #define ISRCTL_SCRLD 0x0100
550 /*
551 * Bits in the ISR_CTL1 register
552 */
554 #define ISRCTL1_UDPINT 0x80
555 #define ISRCTL1_TSUPDIS 0x40
556 #define ISRCTL1_RSUPDIS 0x20
557 #define ISRCTL1_PMSK1 0x10
558 #define ISRCTL1_PMSK0 0x08
559 #define ISRCTL1_INTPD 0x04
560 #define ISRCTL1_HCRLD 0x02
561 #define ISRCTL1_SCRLD 0x01
563 /*
564 * Bits in the TXE_SR register
565 */
567 #define TXESR_TFDBS 0x08
568 #define TXESR_TDWBS 0x04
569 #define TXESR_TDRBS 0x02
570 #define TXESR_TDSTR 0x01
572 /*
573 * Bits in the RXE_SR register
574 */
576 #define RXESR_RFDBS 0x08
577 #define RXESR_RDWBS 0x04
578 #define RXESR_RDRBS 0x02
579 #define RXESR_RDSTR 0x01
581 /*
582 * Bits in the ISR register
583 */
585 #define ISR_ISR3 0x80000000UL
586 #define ISR_ISR2 0x40000000UL
587 #define ISR_ISR1 0x20000000UL
588 #define ISR_ISR0 0x10000000UL
589 #define ISR_TXSTLI 0x02000000UL
590 #define ISR_RXSTLI 0x01000000UL
591 #define ISR_HFLD 0x00800000UL
592 #define ISR_UDPI 0x00400000UL
593 #define ISR_MIBFI 0x00200000UL
594 #define ISR_SHDNI 0x00100000UL
595 #define ISR_PHYI 0x00080000UL
596 #define ISR_PWEI 0x00040000UL
597 #define ISR_TMR1I 0x00020000UL
598 #define ISR_TMR0I 0x00010000UL
599 #define ISR_SRCI 0x00008000UL
600 #define ISR_LSTPEI 0x00004000UL
601 #define ISR_LSTEI 0x00002000UL
602 #define ISR_OVFI 0x00001000UL
603 #define ISR_FLONI 0x00000800UL
604 #define ISR_RACEI 0x00000400UL
605 #define ISR_TXWB1I 0x00000200UL
606 #define ISR_TXWB0I 0x00000100UL
607 #define ISR_PTX3I 0x00000080UL
608 #define ISR_PTX2I 0x00000040UL
609 #define ISR_PTX1I 0x00000020UL
610 #define ISR_PTX0I 0x00000010UL
611 #define ISR_PTXI 0x00000008UL
612 #define ISR_PRXI 0x00000004UL
613 #define ISR_PPTXI 0x00000002UL
614 #define ISR_PPRXI 0x00000001UL
616 /*
617 * Bits in the IMR register
618 */
620 #define IMR_TXSTLM 0x02000000UL
621 #define IMR_UDPIM 0x00400000UL
622 #define IMR_MIBFIM 0x00200000UL
623 #define IMR_SHDNIM 0x00100000UL
624 #define IMR_PHYIM 0x00080000UL
625 #define IMR_PWEIM 0x00040000UL
626 #define IMR_TMR1IM 0x00020000UL
627 #define IMR_TMR0IM 0x00010000UL
629 #define IMR_SRCIM 0x00008000UL
630 #define IMR_LSTPEIM 0x00004000UL
631 #define IMR_LSTEIM 0x00002000UL
632 #define IMR_OVFIM 0x00001000UL
633 #define IMR_FLONIM 0x00000800UL
634 #define IMR_RACEIM 0x00000400UL
635 #define IMR_TXWB1IM 0x00000200UL
636 #define IMR_TXWB0IM 0x00000100UL
638 #define IMR_PTX3IM 0x00000080UL
639 #define IMR_PTX2IM 0x00000040UL
640 #define IMR_PTX1IM 0x00000020UL
641 #define IMR_PTX0IM 0x00000010UL
642 #define IMR_PTXIM 0x00000008UL
643 #define IMR_PRXIM 0x00000004UL
644 #define IMR_PPTXIM 0x00000002UL
645 #define IMR_PPRXIM 0x00000001UL
647 /* 0x0013FB0FUL = initial value of IMR */
649 #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
650 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
651 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
652 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
654 /*
655 * Bits in the TDCSR0/1, RDCSR0 register
656 */
658 #define TRDCSR_DEAD 0x0008
659 #define TRDCSR_WAK 0x0004
660 #define TRDCSR_ACT 0x0002
661 #define TRDCSR_RUN 0x0001
663 /*
664 * Bits in the CAMADDR register
665 */
667 #define CAMADDR_CAMEN 0x80
668 #define CAMADDR_VCAMSL 0x40
670 /*
671 * Bits in the CAMCR register
672 */
674 #define CAMCR_PS1 0x80
675 #define CAMCR_PS0 0x40
676 #define CAMCR_AITRPKT 0x20
677 #define CAMCR_AITR16 0x10
678 #define CAMCR_CAMRD 0x08
679 #define CAMCR_CAMWR 0x04
680 #define CAMCR_PS_CAM_MASK 0x40
681 #define CAMCR_PS_CAM_DATA 0x80
682 #define CAMCR_PS_MAR 0x00
684 /*
685 * Bits in the MIICFG register
686 */
688 #define MIICFG_MPO1 0x80
689 #define MIICFG_MPO0 0x40
690 #define MIICFG_MFDC 0x20
692 /*
693 * Bits in the MIISR register
694 */
696 #define MIISR_MIDLE 0x80
698 /*
699 * Bits in the PHYSR0 register
700 */
702 #define PHYSR0_PHYRST 0x80
703 #define PHYSR0_LINKGD 0x40
704 #define PHYSR0_FDPX 0x10
705 #define PHYSR0_SPDG 0x08
706 #define PHYSR0_SPD10 0x04
707 #define PHYSR0_RXFLC 0x02
708 #define PHYSR0_TXFLC 0x01
710 /*
711 * Bits in the PHYSR1 register
712 */
714 #define PHYSR1_PHYTBI 0x01
716 /*
717 * Bits in the MIICR register
718 */
720 #define MIICR_MAUTO 0x80
721 #define MIICR_RCMD 0x40
722 #define MIICR_WCMD 0x20
723 #define MIICR_MDPM 0x10
724 #define MIICR_MOUT 0x08
725 #define MIICR_MDO 0x04
726 #define MIICR_MDI 0x02
727 #define MIICR_MDC 0x01
729 /*
730 * Bits in the MIIADR register
731 */
733 #define MIIADR_SWMPL 0x80
735 /*
736 * Bits in the CFGA register
737 */
739 #define CFGA_PMHCTG 0x08
740 #define CFGA_GPIO1PD 0x04
741 #define CFGA_ABSHDN 0x02
742 #define CFGA_PACPI 0x01
744 /*
745 * Bits in the CFGB register
746 */
748 #define CFGB_GTCKOPT 0x80
749 #define CFGB_MIIOPT 0x40
750 #define CFGB_CRSEOPT 0x20
751 #define CFGB_OFSET 0x10
752 #define CFGB_CRANDOM 0x08
753 #define CFGB_CAP 0x04
754 #define CFGB_MBA 0x02
755 #define CFGB_BAKOPT 0x01
757 /*
758 * Bits in the CFGC register
759 */
761 #define CFGC_EELOAD 0x80
762 #define CFGC_BROPT 0x40
763 #define CFGC_DLYEN 0x20
764 #define CFGC_DTSEL 0x10
765 #define CFGC_BTSEL 0x08
766 #define CFGC_BPS2 0x04 /* bootrom select[2] */
767 #define CFGC_BPS1 0x02 /* bootrom select[1] */
768 #define CFGC_BPS0 0x01 /* bootrom select[0] */
770 /*
771 * Bits in the CFGD register
772 */
774 #define CFGD_IODIS 0x80
775 #define CFGD_MSLVDACEN 0x40
776 #define CFGD_CFGDACEN 0x20
777 #define CFGD_PCI64EN 0x10
778 #define CFGD_HTMRL4 0x08
780 /*
781 * Bits in the DCFG1 register
782 */
784 #define DCFG_XMWI 0x8000
785 #define DCFG_XMRM 0x4000
786 #define DCFG_XMRL 0x2000
787 #define DCFG_PERDIS 0x1000
788 #define DCFG_MRWAIT 0x0400
789 #define DCFG_MWWAIT 0x0200
790 #define DCFG_LATMEN 0x0100
792 /*
793 * Bits in the MCFG0 register
794 */
796 #define MCFG_RXARB 0x0080
797 #define MCFG_RFT1 0x0020
798 #define MCFG_RFT0 0x0010
799 #define MCFG_LOWTHOPT 0x0008
800 #define MCFG_PQEN 0x0004
801 #define MCFG_RTGOPT 0x0002
802 #define MCFG_VIDFR 0x0001
804 /*
805 * Bits in the MCFG1 register
806 */
808 #define MCFG_TXARB 0x8000
809 #define MCFG_TXQBK1 0x0800
810 #define MCFG_TXQBK0 0x0400
811 #define MCFG_TXQNOBK 0x0200
812 #define MCFG_SNAPOPT 0x0100
814 /*
815 * Bits in the PMCC register
816 */
818 #define PMCC_DSI 0x80
819 #define PMCC_D2_DIS 0x40
820 #define PMCC_D1_DIS 0x20
821 #define PMCC_D3C_EN 0x10
822 #define PMCC_D3H_EN 0x08
823 #define PMCC_D2_EN 0x04
824 #define PMCC_D1_EN 0x02
825 #define PMCC_D0_EN 0x01
827 /*
828 * Bits in STICKHW
829 */
831 #define STICKHW_SWPTAG 0x10
832 #define STICKHW_WOLSR 0x08
833 #define STICKHW_WOLEN 0x04
834 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
835 #define STICKHW_DS0 0x01 /* suspend well DS write port */
837 /*
838 * Bits in the MIBCR register
839 */
841 #define MIBCR_MIBISTOK 0x80
842 #define MIBCR_MIBISTGO 0x40
843 #define MIBCR_MIBINC 0x20
844 #define MIBCR_MIBHI 0x10
845 #define MIBCR_MIBFRZ 0x08
846 #define MIBCR_MIBFLSH 0x04
847 #define MIBCR_MPTRINI 0x02
848 #define MIBCR_MIBCLR 0x01
850 /*
851 * Bits in the EERSV register
852 */
854 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
856 #define EERSV_BOOT_MASK ((u8) 0x06)
857 #define EERSV_BOOT_INT19 ((u8) 0x00)
858 #define EERSV_BOOT_INT18 ((u8) 0x02)
859 #define EERSV_BOOT_LOCAL ((u8) 0x04)
860 #define EERSV_BOOT_BEV ((u8) 0x06)
863 /*
864 * Bits in BPCMD
865 */
867 #define BPCMD_BPDNE 0x80
868 #define BPCMD_EBPWR 0x02
869 #define BPCMD_EBPRD 0x01
871 /*
872 * Bits in the EECSR register
873 */
875 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
876 #define EECSR_RELOAD 0x20 /* eeprom content reload */
877 #define EECSR_DPM 0x10 /* eeprom direct programming */
878 #define EECSR_ECS 0x08 /* eeprom CS pin */
879 #define EECSR_ECK 0x04 /* eeprom CK pin */
880 #define EECSR_EDI 0x02 /* eeprom DI pin */
881 #define EECSR_EDO 0x01 /* eeprom DO pin */
883 /*
884 * Bits in the EMBCMD register
885 */
887 #define EMBCMD_EDONE 0x80
888 #define EMBCMD_EWDIS 0x08
889 #define EMBCMD_EWEN 0x04
890 #define EMBCMD_EWR 0x02
891 #define EMBCMD_ERD 0x01
893 /*
894 * Bits in TESTCFG register
895 */
897 #define TESTCFG_HBDIS 0x80
899 /*
900 * Bits in CHIPGCR register
901 */
903 #define CHIPGCR_FCGMII 0x80
904 #define CHIPGCR_FCFDX 0x40
905 #define CHIPGCR_FCRESV 0x20
906 #define CHIPGCR_FCMODE 0x10
907 #define CHIPGCR_LPSOPT 0x08
908 #define CHIPGCR_TM1US 0x04
909 #define CHIPGCR_TM0US 0x02
910 #define CHIPGCR_PHYINTEN 0x01
912 /*
913 * Bits in WOLCR0
914 */
916 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
917 #define WOLCR_MSWOLEN6 0x0040
918 #define WOLCR_MSWOLEN5 0x0020
919 #define WOLCR_MSWOLEN4 0x0010
920 #define WOLCR_MSWOLEN3 0x0008
921 #define WOLCR_MSWOLEN2 0x0004
922 #define WOLCR_MSWOLEN1 0x0002
923 #define WOLCR_MSWOLEN0 0x0001
924 #define WOLCR_ARP_EN 0x0001
926 /*
927 * Bits in WOLCR1
928 */
930 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
931 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
932 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
933 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
936 /*
937 * Bits in PWCFG
938 */
940 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
941 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
942 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
943 #define PWCFG_LEGCY_WOL 0x10
944 #define PWCFG_PMCSR_PME_SR 0x08
945 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
946 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
947 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
949 /*
950 * Bits in WOLCFG
951 */
953 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
954 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
955 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
956 #define WOLCFG_SMIIACC 0x08 /* ?? */
957 #define WOLCFG_SGENWH 0x02
958 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
959 to report status change */
960 /*
961 * Bits in WOLSR1
962 */
964 #define WOLSR_LINKOFF_INT 0x0800
965 #define WOLSR_LINKON_INT 0x0400
966 #define WOLSR_MAGIC_INT 0x0200
967 #define WOLSR_UNICAST_INT 0x0100
969 /*
970 * Ethernet address filter type
971 */
973 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
974 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
975 #define PKT_TYPE_MULTICAST 0x0002
976 #define PKT_TYPE_ALL_MULTICAST 0x0004
977 #define PKT_TYPE_BROADCAST 0x0008
978 #define PKT_TYPE_PROMISCUOUS 0x0020
979 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
980 #define PKT_TYPE_RUNT 0x4000
981 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
983 /*
984 * Loopback mode
985 */
987 #define MAC_LB_NONE 0x00
988 #define MAC_LB_INTERNAL 0x01
989 #define MAC_LB_EXTERNAL 0x02
991 /*
992 * Enabled mask value of irq
993 */
995 #if defined(_SIM)
996 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
997 set IMR0 to 0x0F according to spec */
999 #else
1000 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
1001 ignore MIBFI,RACEI to
1002 reduce intr. frequency
1003 NOTE.... do not enable NoBuf int mask at driver driver
1004 when (1) NoBuf -> RxThreshold = SF
1005 (2) OK -> RxThreshold = original value
1006 */
1007 #endif
1009 /*
1010 * Revision id
1011 */
1013 #define REV_ID_VT3119_A0 0x00
1014 #define REV_ID_VT3119_A1 0x01
1015 #define REV_ID_VT3216_A0 0x10
1017 /*
1018 * Max time out delay time
1019 */
1021 #define W_MAX_TIMEOUT 0x0FFFU
1024 /*
1025 * MAC registers as a structure. Cannot be directly accessed this
1026 * way but generates offsets for readl/writel() calls
1027 */
1029 struct mac_regs {
1030 volatile u8 PAR[6]; /* 0x00 */
1031 volatile u8 RCR;
1032 volatile u8 TCR;
1034 volatile u32 CR0Set; /* 0x08 */
1035 volatile u32 CR0Clr; /* 0x0C */
1037 volatile u8 MARCAM[8]; /* 0x10 */
1039 volatile u32 DecBaseHi; /* 0x18 */
1040 volatile u16 DbfBaseHi; /* 0x1C */
1041 volatile u16 reserved_1E;
1043 volatile u16 ISRCTL; /* 0x20 */
1044 volatile u8 TXESR;
1045 volatile u8 RXESR;
1047 volatile u32 ISR; /* 0x24 */
1048 volatile u32 IMR;
1050 volatile u32 TDStatusPort; /* 0x2C */
1052 volatile u16 TDCSRSet; /* 0x30 */
1053 volatile u8 RDCSRSet;
1054 volatile u8 reserved_33;
1055 volatile u16 TDCSRClr;
1056 volatile u8 RDCSRClr;
1057 volatile u8 reserved_37;
1059 volatile u32 RDBaseLo; /* 0x38 */
1060 volatile u16 RDIdx; /* 0x3C */
1061 volatile u16 reserved_3E;
1063 volatile u32 TDBaseLo[4]; /* 0x40 */
1065 volatile u16 RDCSize; /* 0x50 */
1066 volatile u16 TDCSize; /* 0x52 */
1067 volatile u16 TDIdx[4]; /* 0x54 */
1068 volatile u16 tx_pause_timer; /* 0x5C */
1069 volatile u16 RBRDU; /* 0x5E */
1071 volatile u32 FIFOTest0; /* 0x60 */
1072 volatile u32 FIFOTest1; /* 0x64 */
1074 volatile u8 CAMADDR; /* 0x68 */
1075 volatile u8 CAMCR; /* 0x69 */
1076 volatile u8 GFTEST; /* 0x6A */
1077 volatile u8 FTSTCMD; /* 0x6B */
1079 volatile u8 MIICFG; /* 0x6C */
1080 volatile u8 MIISR;
1081 volatile u8 PHYSR0;
1082 volatile u8 PHYSR1;
1083 volatile u8 MIICR;
1084 volatile u8 MIIADR;
1085 volatile u16 MIIDATA;
1087 volatile u16 SoftTimer0; /* 0x74 */
1088 volatile u16 SoftTimer1;
1090 volatile u8 CFGA; /* 0x78 */
1091 volatile u8 CFGB;
1092 volatile u8 CFGC;
1093 volatile u8 CFGD;
1095 volatile u16 DCFG; /* 0x7C */
1096 volatile u16 MCFG;
1098 volatile u8 TBIST; /* 0x80 */
1099 volatile u8 RBIST;
1100 volatile u8 PMCPORT;
1101 volatile u8 STICKHW;
1103 volatile u8 MIBCR; /* 0x84 */
1104 volatile u8 reserved_85;
1105 volatile u8 rev_id;
1106 volatile u8 PORSTS;
1108 volatile u32 MIBData; /* 0x88 */
1110 volatile u16 EEWrData;
1112 volatile u8 reserved_8E;
1113 volatile u8 BPMDWr;
1114 volatile u8 BPCMD;
1115 volatile u8 BPMDRd;
1117 volatile u8 EECHKSUM; /* 0x92 */
1118 volatile u8 EECSR;
1120 volatile u16 EERdData; /* 0x94 */
1121 volatile u8 EADDR;
1122 volatile u8 EMBCMD;
1125 volatile u8 JMPSR0; /* 0x98 */
1126 volatile u8 JMPSR1;
1127 volatile u8 JMPSR2;
1128 volatile u8 JMPSR3;
1129 volatile u8 CHIPGSR; /* 0x9C */
1130 volatile u8 TESTCFG;
1131 volatile u8 DEBUG;
1132 volatile u8 CHIPGCR;
1134 volatile u16 WOLCRSet; /* 0xA0 */
1135 volatile u8 PWCFGSet;
1136 volatile u8 WOLCFGSet;
1138 volatile u16 WOLCRClr; /* 0xA4 */
1139 volatile u8 PWCFGCLR;
1140 volatile u8 WOLCFGClr;
1142 volatile u16 WOLSRSet; /* 0xA8 */
1143 volatile u16 reserved_AA;
1145 volatile u16 WOLSRClr; /* 0xAC */
1146 volatile u16 reserved_AE;
1148 volatile u16 PatternCRC[8]; /* 0xB0 */
1149 volatile u32 ByteMask[4][4]; /* 0xC0 */
1150 } __attribute__ ((__packed__));
1153 enum hw_mib {
1154 HW_MIB_ifRxAllPkts = 0,
1155 HW_MIB_ifRxOkPkts,
1156 HW_MIB_ifTxOkPkts,
1157 HW_MIB_ifRxErrorPkts,
1158 HW_MIB_ifRxRuntOkPkt,
1159 HW_MIB_ifRxRuntErrPkt,
1160 HW_MIB_ifRx64Pkts,
1161 HW_MIB_ifTx64Pkts,
1162 HW_MIB_ifRx65To127Pkts,
1163 HW_MIB_ifTx65To127Pkts,
1164 HW_MIB_ifRx128To255Pkts,
1165 HW_MIB_ifTx128To255Pkts,
1166 HW_MIB_ifRx256To511Pkts,
1167 HW_MIB_ifTx256To511Pkts,
1168 HW_MIB_ifRx512To1023Pkts,
1169 HW_MIB_ifTx512To1023Pkts,
1170 HW_MIB_ifRx1024To1518Pkts,
1171 HW_MIB_ifTx1024To1518Pkts,
1172 HW_MIB_ifTxEtherCollisions,
1173 HW_MIB_ifRxPktCRCE,
1174 HW_MIB_ifRxJumboPkts,
1175 HW_MIB_ifTxJumboPkts,
1176 HW_MIB_ifRxMacControlFrames,
1177 HW_MIB_ifTxMacControlFrames,
1178 HW_MIB_ifRxPktFAE,
1179 HW_MIB_ifRxLongOkPkt,
1180 HW_MIB_ifRxLongPktErrPkt,
1181 HW_MIB_ifTXSQEErrors,
1182 HW_MIB_ifRxNobuf,
1183 HW_MIB_ifRxSymbolErrors,
1184 HW_MIB_ifInRangeLengthErrors,
1185 HW_MIB_ifLateCollisions,
1186 HW_MIB_SIZE
1187 };
1189 enum chip_type {
1190 CHIP_TYPE_VT6110 = 1,
1191 };
1193 struct velocity_info_tbl {
1194 enum chip_type chip_id;
1195 char *name;
1196 int txqueue;
1197 u32 flags;
1198 };
1200 #define mac_hw_mibs_init(regs) {\
1201 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1202 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1203 do {}\
1204 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1205 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1208 #define mac_read_isr(regs) readl(&((regs)->ISR))
1209 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1210 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1212 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1213 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1214 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1216 #define mac_hw_mibs_read(regs, MIBs) {\
1217 int i;\
1218 BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
1219 for (i=0;i<HW_MIB_SIZE;i++) {\
1220 (MIBs)[i]=readl(&((regs)->MIBData));\
1221 }\
1224 #define mac_set_dma_length(regs, n) {\
1225 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1228 #define mac_set_rx_thresh(regs, n) {\
1229 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1232 #define mac_rx_queue_run(regs) {\
1233 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1236 #define mac_rx_queue_wake(regs) {\
1237 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1240 #define mac_tx_queue_run(regs, n) {\
1241 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1244 #define mac_tx_queue_wake(regs, n) {\
1245 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1248 #define mac_eeprom_reload(regs) {\
1249 int i=0;\
1250 BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
1251 do {\
1252 udelay(10);\
1253 if (i++>0x1000) {\
1254 break;\
1255 }\
1256 }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
1259 enum velocity_cam_type {
1260 VELOCITY_VLAN_ID_CAM = 0,
1261 VELOCITY_MULTICAST_CAM
1262 };
1264 /**
1265 * mac_get_cam_mask - Read a CAM mask
1266 * @regs: register block for this velocity
1267 * @mask: buffer to store mask
1268 * @cam_type: CAM to fetch
1270 * Fetch the mask bits of the selected CAM and store them into the
1271 * provided mask buffer.
1272 */
1274 static inline void mac_get_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
1276 int i;
1277 /* Select CAM mask */
1278 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1280 if (cam_type == VELOCITY_VLAN_ID_CAM)
1281 writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
1282 else
1283 writeb(0, &regs->CAMADDR);
1285 /* read mask */
1286 for (i = 0; i < 8; i++)
1287 *mask++ = readb(&(regs->MARCAM[i]));
1289 /* disable CAMEN */
1290 writeb(0, &regs->CAMADDR);
1292 /* Select mar */
1293 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1297 /**
1298 * mac_set_cam_mask - Set a CAM mask
1299 * @regs: register block for this velocity
1300 * @mask: CAM mask to load
1301 * @cam_type: CAM to store
1303 * Store a new mask into a CAM
1304 */
1306 static inline void mac_set_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
1308 int i;
1309 /* Select CAM mask */
1310 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1312 if (cam_type == VELOCITY_VLAN_ID_CAM)
1313 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
1314 else
1315 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
1317 for (i = 0; i < 8; i++) {
1318 writeb(*mask++, &(regs->MARCAM[i]));
1320 /* disable CAMEN */
1321 writeb(0, &regs->CAMADDR);
1323 /* Select mar */
1324 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1327 /**
1328 * mac_set_cam - set CAM data
1329 * @regs: register block of this velocity
1330 * @idx: Cam index
1331 * @addr: 2 or 6 bytes of CAM data
1332 * @cam_type: CAM to load
1334 * Load an address or vlan tag into a CAM
1335 */
1337 static inline void mac_set_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
1339 int i;
1341 /* Select CAM mask */
1342 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1344 idx &= (64 - 1);
1346 if (cam_type == VELOCITY_VLAN_ID_CAM)
1347 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
1348 else
1349 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1351 if (cam_type == VELOCITY_VLAN_ID_CAM)
1352 writew(*((u16 *) addr), &regs->MARCAM[0]);
1353 else {
1354 for (i = 0; i < 6; i++) {
1355 writeb(*addr++, &(regs->MARCAM[i]));
1358 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
1360 udelay(10);
1362 writeb(0, &regs->CAMADDR);
1364 /* Select mar */
1365 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1368 /**
1369 * mac_get_cam - fetch CAM data
1370 * @regs: register block of this velocity
1371 * @idx: Cam index
1372 * @addr: buffer to hold up to 6 bytes of CAM data
1373 * @cam_type: CAM to load
1375 * Load an address or vlan tag from a CAM into the buffer provided by
1376 * the caller. VLAN tags are 2 bytes the address cam entries are 6.
1377 */
1379 static inline void mac_get_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
1381 int i;
1383 /* Select CAM mask */
1384 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1386 idx &= (64 - 1);
1388 if (cam_type == VELOCITY_VLAN_ID_CAM)
1389 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
1390 else
1391 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1393 BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
1395 udelay(10);
1397 if (cam_type == VELOCITY_VLAN_ID_CAM)
1398 *((u16 *) addr) = readw(&(regs->MARCAM[0]));
1399 else
1400 for (i = 0; i < 6; i++, addr++)
1401 *((u8 *) addr) = readb(&(regs->MARCAM[i]));
1403 writeb(0, &regs->CAMADDR);
1405 /* Select mar */
1406 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1409 /**
1410 * mac_wol_reset - reset WOL after exiting low power
1411 * @regs: register block of this velocity
1413 * Called after we drop out of wake on lan mode in order to
1414 * reset the Wake on lan features. This function doesn't restore
1415 * the rest of the logic from the result of sleep/wakeup
1416 */
1418 static inline void mac_wol_reset(struct mac_regs __iomem * regs)
1421 /* Turn off SWPTAG right after leaving power mode */
1422 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
1423 /* clear sticky bits */
1424 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
1426 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
1427 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
1428 /* disable force PME-enable */
1429 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
1430 /* disable power-event config bit */
1431 writew(0xFFFF, &regs->WOLCRClr);
1432 /* clear power status */
1433 writew(0xFFFF, &regs->WOLSRClr);
1437 /*
1438 * Header for WOL definitions. Used to compute hashes
1439 */
1441 typedef u8 MCAM_ADDR[ETH_ALEN];
1443 struct arp_packet {
1444 u8 dest_mac[ETH_ALEN];
1445 u8 src_mac[ETH_ALEN];
1446 u16 type;
1447 u16 ar_hrd;
1448 u16 ar_pro;
1449 u8 ar_hln;
1450 u8 ar_pln;
1451 u16 ar_op;
1452 u8 ar_sha[ETH_ALEN];
1453 u8 ar_sip[4];
1454 u8 ar_tha[ETH_ALEN];
1455 u8 ar_tip[4];
1456 } __attribute__ ((__packed__));
1458 struct _magic_packet {
1459 u8 dest_mac[6];
1460 u8 src_mac[6];
1461 u16 type;
1462 u8 MAC[16][6];
1463 u8 password[6];
1464 } __attribute__ ((__packed__));
1466 /*
1467 * Store for chip context when saving and restoring status. Not
1468 * all fields are saved/restored currently.
1469 */
1471 struct velocity_context {
1472 u8 mac_reg[256];
1473 MCAM_ADDR cam_addr[MCAM_SIZE];
1474 u16 vcam[VCAM_SIZE];
1475 u32 cammask[2];
1476 u32 patcrc[2];
1477 u32 pattern[8];
1478 };
1481 /*
1482 * MII registers.
1483 */
1486 /*
1487 * Registers in the MII (offset unit is WORD)
1488 */
1490 #define MII_REG_BMCR 0x00 // physical address
1491 #define MII_REG_BMSR 0x01 //
1492 #define MII_REG_PHYID1 0x02 // OUI
1493 #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1494 #define MII_REG_ANAR 0x04 //
1495 #define MII_REG_ANLPAR 0x05 //
1496 #define MII_REG_G1000CR 0x09 //
1497 #define MII_REG_G1000SR 0x0A //
1498 #define MII_REG_MODCFG 0x10 //
1499 #define MII_REG_TCSR 0x16 //
1500 #define MII_REG_PLED 0x1B //
1501 // NS, MYSON only
1502 #define MII_REG_PCR 0x17 //
1503 // ESI only
1504 #define MII_REG_PCSR 0x17 //
1505 #define MII_REG_AUXCR 0x1C //
1507 // Marvell 88E1000/88E1000S
1508 #define MII_REG_PSCR 0x10 // PHY specific control register
1510 //
1511 // Bits in the BMCR register
1512 //
1513 #define BMCR_RESET 0x8000 //
1514 #define BMCR_LBK 0x4000 //
1515 #define BMCR_SPEED100 0x2000 //
1516 #define BMCR_AUTO 0x1000 //
1517 #define BMCR_PD 0x0800 //
1518 #define BMCR_ISO 0x0400 //
1519 #define BMCR_REAUTO 0x0200 //
1520 #define BMCR_FDX 0x0100 //
1521 #define BMCR_SPEED1G 0x0040 //
1522 //
1523 // Bits in the BMSR register
1524 //
1525 #define BMSR_AUTOCM 0x0020 //
1526 #define BMSR_LNK 0x0004 //
1528 //
1529 // Bits in the ANAR register
1530 //
1531 #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1532 #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1533 #define ANAR_T4 0x0200 //
1534 #define ANAR_TXFD 0x0100 //
1535 #define ANAR_TX 0x0080 //
1536 #define ANAR_10FD 0x0040 //
1537 #define ANAR_10 0x0020 //
1538 //
1539 // Bits in the ANLPAR register
1540 //
1541 #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1542 #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1543 #define ANLPAR_T4 0x0200 //
1544 #define ANLPAR_TXFD 0x0100 //
1545 #define ANLPAR_TX 0x0080 //
1546 #define ANLPAR_10FD 0x0040 //
1547 #define ANLPAR_10 0x0020 //
1549 //
1550 // Bits in the G1000CR register
1551 //
1552 #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1553 #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1555 //
1556 // Bits in the G1000SR register
1557 //
1558 #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1559 #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1561 #define TCSR_ECHODIS 0x2000 //
1562 #define AUXCR_MDPPS 0x0004 //
1564 // Bits in the PLED register
1565 #define PLED_LALBE 0x0004 //
1567 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1568 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1570 #define PHYID_CICADA_CS8201 0x000FC410UL
1571 #define PHYID_VT3216_32BIT 0x000FC610UL
1572 #define PHYID_VT3216_64BIT 0x000FC600UL
1573 #define PHYID_MARVELL_1000 0x01410C50UL
1574 #define PHYID_MARVELL_1000S 0x01410C40UL
1576 #define PHYID_REV_ID_MASK 0x0000000FUL
1578 #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1579 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1581 #define MII_REG_BITS_ON(x,i,p) do {\
1582 u16 w;\
1583 velocity_mii_read((p),(i),&(w));\
1584 (w)|=(x);\
1585 velocity_mii_write((p),(i),(w));\
1586 } while (0)
1588 #define MII_REG_BITS_OFF(x,i,p) do {\
1589 u16 w;\
1590 velocity_mii_read((p),(i),&(w));\
1591 (w)&=(~(x));\
1592 velocity_mii_write((p),(i),(w));\
1593 } while (0)
1595 #define MII_REG_BITS_IS_ON(x,i,p) ({\
1596 u16 w;\
1597 velocity_mii_read((p),(i),&(w));\
1598 ((int) ((w) & (x)));})
1600 #define MII_GET_PHY_ID(p) ({\
1601 u32 id;\
1602 velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
1603 velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
1604 (id);})
1606 /*
1607 * Inline debug routine
1608 */
1611 enum velocity_msg_level {
1612 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1613 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1614 MSG_LEVEL_INFO = 2, //Normal message.
1615 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1616 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1617 };
1619 #ifdef VELOCITY_DEBUG
1620 #define ASSERT(x) { \
1621 if (!(x)) { \
1622 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1623 __FUNCTION__, __LINE__);\
1624 BUG(); \
1625 }\
1627 #define VELOCITY_DBG(p,args...) printk(p, ##args)
1628 #else
1629 #define ASSERT(x)
1630 #define VELOCITY_DBG(x)
1631 #endif
1633 #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
1635 #define VELOCITY_PRT_CAMMASK(p,t) {\
1636 int i;\
1637 if ((t)==VELOCITY_MULTICAST_CAM) {\
1638 for (i=0;i<(MCAM_SIZE/8);i++)\
1639 printk("%02X",(p)->mCAMmask[i]);\
1640 }\
1641 else {\
1642 for (i=0;i<(VCAM_SIZE/8);i++)\
1643 printk("%02X",(p)->vCAMmask[i]);\
1644 }\
1645 printk("\n");\
1650 #define VELOCITY_WOL_MAGIC 0x00000000UL
1651 #define VELOCITY_WOL_PHY 0x00000001UL
1652 #define VELOCITY_WOL_ARP 0x00000002UL
1653 #define VELOCITY_WOL_UCAST 0x00000004UL
1654 #define VELOCITY_WOL_BCAST 0x00000010UL
1655 #define VELOCITY_WOL_MCAST 0x00000020UL
1656 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1658 /*
1659 * Flags for options
1660 */
1662 #define VELOCITY_FLAGS_TAGGING 0x00000001UL
1663 #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1664 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1665 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1666 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1668 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1670 /*
1671 * Flags for driver status
1672 */
1674 #define VELOCITY_FLAGS_OPENED 0x00010000UL
1675 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1676 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1677 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1679 /*
1680 * Flags for MII status
1681 */
1683 #define VELOCITY_LINK_FAIL 0x00000001UL
1684 #define VELOCITY_SPEED_10 0x00000002UL
1685 #define VELOCITY_SPEED_100 0x00000004UL
1686 #define VELOCITY_SPEED_1000 0x00000008UL
1687 #define VELOCITY_DUPLEX_FULL 0x00000010UL
1688 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1689 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1691 /*
1692 * For velocity_set_media_duplex
1693 */
1695 #define VELOCITY_LINK_CHANGE 0x00000001UL
1697 enum speed_opt {
1698 SPD_DPX_AUTO = 0,
1699 SPD_DPX_100_HALF = 1,
1700 SPD_DPX_100_FULL = 2,
1701 SPD_DPX_10_HALF = 3,
1702 SPD_DPX_10_FULL = 4
1703 };
1705 enum velocity_init_type {
1706 VELOCITY_INIT_COLD = 0,
1707 VELOCITY_INIT_RESET,
1708 VELOCITY_INIT_WOL
1709 };
1711 enum velocity_flow_cntl_type {
1712 FLOW_CNTL_DEFAULT = 1,
1713 FLOW_CNTL_TX,
1714 FLOW_CNTL_RX,
1715 FLOW_CNTL_TX_RX,
1716 FLOW_CNTL_DISABLE,
1717 };
1719 struct velocity_opt {
1720 int numrx; /* Number of RX descriptors */
1721 int numtx; /* Number of TX descriptors */
1722 enum speed_opt spd_dpx; /* Media link mode */
1723 int vid; /* vlan id */
1724 int DMA_length; /* DMA length */
1725 int rx_thresh; /* RX_THRESH */
1726 int flow_cntl;
1727 int wol_opts; /* Wake on lan options */
1728 int td_int_count;
1729 int int_works;
1730 int rx_bandwidth_hi;
1731 int rx_bandwidth_lo;
1732 int rx_bandwidth_en;
1733 u32 flags;
1734 };
1736 struct velocity_info {
1737 struct list_head list;
1739 struct pci_dev *pdev;
1740 struct net_device *dev;
1741 struct net_device_stats stats;
1743 dma_addr_t rd_pool_dma;
1744 dma_addr_t td_pool_dma[TX_QUEUE_NO];
1746 dma_addr_t tx_bufs_dma;
1747 u8 *tx_bufs;
1749 u8 ip_addr[4];
1750 enum chip_type chip_id;
1752 struct mac_regs __iomem * mac_regs;
1753 unsigned long memaddr;
1754 unsigned long ioaddr;
1756 u8 rev_id;
1758 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
1760 int num_txq;
1762 volatile int td_used[TX_QUEUE_NO];
1763 int td_curr[TX_QUEUE_NO];
1764 int td_tail[TX_QUEUE_NO];
1765 struct tx_desc *td_rings[TX_QUEUE_NO];
1766 struct velocity_td_info *td_infos[TX_QUEUE_NO];
1768 int rd_curr;
1769 int rd_dirty;
1770 u32 rd_filled;
1771 struct rx_desc *rd_ring;
1772 struct velocity_rd_info *rd_info; /* It's an array */
1774 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1775 u32 mib_counter[MAX_HW_MIB_COUNTER];
1776 struct velocity_opt options;
1778 u32 int_mask;
1780 u32 flags;
1782 int rx_buf_sz;
1783 u32 mii_status;
1784 u32 phy_id;
1785 int multicast_limit;
1787 u8 vCAMmask[(VCAM_SIZE / 8)];
1788 u8 mCAMmask[(MCAM_SIZE / 8)];
1790 spinlock_t lock;
1792 int wol_opts;
1793 u8 wol_passwd[6];
1795 struct velocity_context context;
1797 u32 ticks;
1798 u32 rx_bytes;
1800 };
1802 /**
1803 * velocity_get_ip - find an IP address for the device
1804 * @vptr: Velocity to query
1806 * Dig out an IP address for this interface so that we can
1807 * configure wakeup with WOL for ARP. If there are multiple IP
1808 * addresses on this chain then we use the first - multi-IP WOL is not
1809 * supported.
1811 * CHECK ME: locking
1812 */
1814 static inline int velocity_get_ip(struct velocity_info *vptr)
1816 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1817 struct in_ifaddr *ifa;
1819 if (in_dev != NULL) {
1820 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1821 if (ifa != NULL) {
1822 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1823 return 0;
1826 return -ENOENT;
1829 /**
1830 * velocity_update_hw_mibs - fetch MIB counters from chip
1831 * @vptr: velocity to update
1833 * The velocity hardware keeps certain counters in the hardware
1834 * side. We need to read these when the user asks for statistics
1835 * or when they overflow (causing an interrupt). The read of the
1836 * statistic clears it, so we keep running master counters in user
1837 * space.
1838 */
1840 static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1842 u32 tmp;
1843 int i;
1844 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1846 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1848 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1849 for (i = 0; i < HW_MIB_SIZE; i++) {
1850 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1851 vptr->mib_counter[i] += tmp;
1855 /**
1856 * init_flow_control_register - set up flow control
1857 * @vptr: velocity to configure
1859 * Configure the flow control registers for this velocity device.
1860 */
1862 static inline void init_flow_control_register(struct velocity_info *vptr)
1864 struct mac_regs __iomem * regs = vptr->mac_regs;
1866 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1867 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1868 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
1869 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
1871 /* Set TxPauseTimer to 0xFFFF */
1872 writew(0xFFFF, &regs->tx_pause_timer);
1874 /* Initialize RBRDU to Rx buffer count. */
1875 writew(vptr->options.numrx, &regs->RBRDU);
1879 #endif