ia64/linux-2.6.18-xen.hg

view drivers/net/tc35815.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on skelton.c by Donald Becker.
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
31 static const char *version =
32 "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/in.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/errno.h>
44 #include <linux/init.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/proc_fs.h>
51 #include <linux/spinlock.h>
52 #include <linux/bitops.h>
54 #include <asm/system.h>
55 #include <asm/io.h>
56 #include <asm/dma.h>
57 #include <asm/byteorder.h>
59 /*
60 * The name of the card. Is used for messages and in the requests for
61 * io regions, irqs and dma channels
62 */
63 static const char* cardname = "TC35815CF";
64 #define TC35815_PROC_ENTRY "net/tc35815"
66 #define TC35815_MODULE_NAME "TC35815CF"
67 #define TX_TIMEOUT (4*HZ)
69 /* First, a few definitions that the brave might change. */
71 /* use 0 for production, 1 for verification, >2 for debug */
72 #ifndef TC35815_DEBUG
73 #define TC35815_DEBUG 1
74 #endif
75 static unsigned int tc35815_debug = TC35815_DEBUG;
77 #define GATHER_TXINT /* On-Demand Tx Interrupt */
79 #define vtonocache(p) KSEG1ADDR(virt_to_phys(p))
81 /*
82 * Registers
83 */
84 struct tc35815_regs {
85 volatile __u32 DMA_Ctl; /* 0x00 */
86 volatile __u32 TxFrmPtr;
87 volatile __u32 TxThrsh;
88 volatile __u32 TxPollCtr;
89 volatile __u32 BLFrmPtr;
90 volatile __u32 RxFragSize;
91 volatile __u32 Int_En;
92 volatile __u32 FDA_Bas;
93 volatile __u32 FDA_Lim; /* 0x20 */
94 volatile __u32 Int_Src;
95 volatile __u32 unused0[2];
96 volatile __u32 PauseCnt;
97 volatile __u32 RemPauCnt;
98 volatile __u32 TxCtlFrmStat;
99 volatile __u32 unused1;
100 volatile __u32 MAC_Ctl; /* 0x40 */
101 volatile __u32 CAM_Ctl;
102 volatile __u32 Tx_Ctl;
103 volatile __u32 Tx_Stat;
104 volatile __u32 Rx_Ctl;
105 volatile __u32 Rx_Stat;
106 volatile __u32 MD_Data;
107 volatile __u32 MD_CA;
108 volatile __u32 CAM_Adr; /* 0x60 */
109 volatile __u32 CAM_Data;
110 volatile __u32 CAM_Ena;
111 volatile __u32 PROM_Ctl;
112 volatile __u32 PROM_Data;
113 volatile __u32 Algn_Cnt;
114 volatile __u32 CRC_Cnt;
115 volatile __u32 Miss_Cnt;
116 };
118 /*
119 * Bit assignments
120 */
121 /* DMA_Ctl bit asign ------------------------------------------------------- */
122 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
123 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
124 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
125 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
126 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
127 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
128 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
129 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
131 /* RxFragSize bit asign ---------------------------------------------------- */
132 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
133 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
135 /* MAC_Ctl bit asign ------------------------------------------------------- */
136 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
137 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
138 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
139 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
140 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
141 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
142 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
143 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
144 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
145 #define MAC_Reset 0x00000004 /* 1:Software Reset */
146 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
147 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
149 /* PROM_Ctl bit asign ------------------------------------------------------ */
150 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
151 #define PROM_Read 0x00004000 /*10:Read operation */
152 #define PROM_Write 0x00002000 /*01:Write operation */
153 #define PROM_Erase 0x00006000 /*11:Erase operation */
154 /*00:Enable or Disable Writting, */
155 /* as specified in PROM_Addr. */
156 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
157 /*00xxxx: disable */
159 /* CAM_Ctl bit asign ------------------------------------------------------- */
160 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
161 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
162 /* accept other */
163 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
164 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
165 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
167 /* CAM_Ena bit asign ------------------------------------------------------- */
168 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
169 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
170 #define CAM_Ena_Bit(index) (1<<(index))
171 #define CAM_ENTRY_DESTINATION 0
172 #define CAM_ENTRY_SOURCE 1
173 #define CAM_ENTRY_MACCTL 20
175 /* Tx_Ctl bit asign -------------------------------------------------------- */
176 #define Tx_En 0x00000001 /* 1:Transmit enable */
177 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
178 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
179 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
180 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
181 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
182 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
183 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
184 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
185 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
186 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
187 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
189 /* Tx_Stat bit asign ------------------------------------------------------- */
190 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
191 #define Tx_ExColl 0x00000010 /* Excessive Collision */
192 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
193 #define Tx_Paused 0x00000040 /* Transmit Paused */
194 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
195 #define Tx_Under 0x00000100 /* Underrun */
196 #define Tx_Defer 0x00000200 /* Deferral */
197 #define Tx_NCarr 0x00000400 /* No Carrier */
198 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
199 #define Tx_LateColl 0x00001000 /* Late Collision */
200 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
201 #define Tx_Comp 0x00004000 /* Completion */
202 #define Tx_Halted 0x00008000 /* Tx Halted */
203 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
205 /* Rx_Ctl bit asign -------------------------------------------------------- */
206 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
207 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
208 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
209 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
210 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
211 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
212 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
213 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
214 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
215 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
216 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
217 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
219 /* Rx_Stat bit asign ------------------------------------------------------- */
220 #define Rx_Halted 0x00008000 /* Rx Halted */
221 #define Rx_Good 0x00004000 /* Rx Good */
222 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
223 /* 0x00001000 not use */
224 #define Rx_LongErr 0x00000800 /* Rx Long Error */
225 #define Rx_Over 0x00000400 /* Rx Overflow */
226 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
227 #define Rx_Align 0x00000100 /* Rx Alignment Error */
228 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
229 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
230 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
232 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
234 /* Int_En bit asign -------------------------------------------------------- */
235 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
236 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
237 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
238 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
239 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
240 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
241 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
242 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
243 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
244 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
245 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
246 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
247 /* Exhausted Enable */
249 /* Int_Src bit asign ------------------------------------------------------- */
250 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
251 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
252 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
253 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
254 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
255 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
256 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
257 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
258 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
259 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
260 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
261 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
262 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
263 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
264 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
266 /* MD_CA bit asign --------------------------------------------------------- */
267 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
268 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
269 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
272 /* MII register offsets */
273 #define MII_CONTROL 0x0000
274 #define MII_STATUS 0x0001
275 #define MII_PHY_ID0 0x0002
276 #define MII_PHY_ID1 0x0003
277 #define MII_ANAR 0x0004
278 #define MII_ANLPAR 0x0005
279 #define MII_ANER 0x0006
280 /* MII Control register bit definitions. */
281 #define MIICNTL_FDX 0x0100
282 #define MIICNTL_RST_AUTO 0x0200
283 #define MIICNTL_ISOLATE 0x0400
284 #define MIICNTL_PWRDWN 0x0800
285 #define MIICNTL_AUTO 0x1000
286 #define MIICNTL_SPEED 0x2000
287 #define MIICNTL_LPBK 0x4000
288 #define MIICNTL_RESET 0x8000
289 /* MII Status register bit significance. */
290 #define MIISTAT_EXT 0x0001
291 #define MIISTAT_JAB 0x0002
292 #define MIISTAT_LINK 0x0004
293 #define MIISTAT_CAN_AUTO 0x0008
294 #define MIISTAT_FAULT 0x0010
295 #define MIISTAT_AUTO_DONE 0x0020
296 #define MIISTAT_CAN_T 0x0800
297 #define MIISTAT_CAN_T_FDX 0x1000
298 #define MIISTAT_CAN_TX 0x2000
299 #define MIISTAT_CAN_TX_FDX 0x4000
300 #define MIISTAT_CAN_T4 0x8000
301 /* MII Auto-Negotiation Expansion/RemoteEnd Register Bits */
302 #define MII_AN_TX_FDX 0x0100
303 #define MII_AN_TX_HDX 0x0080
304 #define MII_AN_10_FDX 0x0040
305 #define MII_AN_10_HDX 0x0020
308 /*
309 * Descriptors
310 */
312 /* Frame descripter */
313 struct FDesc {
314 volatile __u32 FDNext;
315 volatile __u32 FDSystem;
316 volatile __u32 FDStat;
317 volatile __u32 FDCtl;
318 };
320 /* Buffer descripter */
321 struct BDesc {
322 volatile __u32 BuffData;
323 volatile __u32 BDCtl;
324 };
326 #define FD_ALIGN 16
328 /* Frame Descripter bit asign ---------------------------------------------- */
329 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
330 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
331 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
332 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
333 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
334 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
335 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
336 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
337 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
338 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
339 #define FD_BDCnt_SHIFT 16
341 /* Buffer Descripter bit asign --------------------------------------------- */
342 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
343 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
344 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
345 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
346 #define BD_RxBDID_SHIFT 16
347 #define BD_RxBDSeqN_SHIFT 24
350 /* Some useful constants. */
351 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
353 #ifdef NO_CHECK_CARRIER
354 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
355 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
356 Tx_En) /* maybe 0x7d01 */
357 #else
358 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
359 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
360 Tx_En) /* maybe 0x7f01 */
361 #endif
362 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
363 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
365 #define INT_EN_CMD (Int_NRAbtEn | \
366 Int_DParDEn | Int_DParErrEn | \
367 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
368 Int_STargAbtEn | \
369 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
371 /* Tuning parameters */
372 #define DMA_BURST_SIZE 32
373 #define TX_THRESHOLD 1024
375 #define FD_PAGE_NUM 2
376 #define FD_PAGE_ORDER 1
377 /* 16 + RX_BUF_PAGES * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*2 */
378 #define RX_BUF_PAGES 8 /* >= 2 */
379 #define RX_FD_NUM 250 /* >= 32 */
380 #define TX_FD_NUM 128
382 struct TxFD {
383 struct FDesc fd;
384 struct BDesc bd;
385 struct BDesc unused;
386 };
388 struct RxFD {
389 struct FDesc fd;
390 struct BDesc bd[0]; /* variable length */
391 };
393 struct FrFD {
394 struct FDesc fd;
395 struct BDesc bd[RX_BUF_PAGES];
396 };
399 extern unsigned long tc_readl(volatile __u32 *addr);
400 extern void tc_writel(unsigned long data, volatile __u32 *addr);
402 dma_addr_t priv_dma_handle;
404 /* Information that need to be kept for each board. */
405 struct tc35815_local {
406 struct net_device *next_module;
408 /* statistics */
409 struct net_device_stats stats;
410 struct {
411 int max_tx_qlen;
412 int tx_ints;
413 int rx_ints;
414 } lstats;
416 int tbusy;
417 int option;
418 #define TC35815_OPT_AUTO 0x00
419 #define TC35815_OPT_10M 0x01
420 #define TC35815_OPT_100M 0x02
421 #define TC35815_OPT_FULLDUP 0x04
422 int linkspeed; /* 10 or 100 */
423 int fullduplex;
425 /*
426 * Transmitting: Batch Mode.
427 * 1 BD in 1 TxFD.
428 * Receiving: Packing Mode.
429 * 1 circular FD for Free Buffer List.
430 * RX_BUG_PAGES BD in Free Buffer FD.
431 * One Free Buffer BD has PAGE_SIZE data buffer.
432 */
433 struct pci_dev *pdev;
434 dma_addr_t fd_buf_dma_handle;
435 void * fd_buf; /* for TxFD, TxFD, FrFD */
436 struct TxFD *tfd_base;
437 int tfd_start;
438 int tfd_end;
439 struct RxFD *rfd_base;
440 struct RxFD *rfd_limit;
441 struct RxFD *rfd_cur;
442 struct FrFD *fbl_ptr;
443 unsigned char fbl_curid;
444 dma_addr_t data_buf_dma_handle[RX_BUF_PAGES];
445 void * data_buf[RX_BUF_PAGES]; /* packing */
446 spinlock_t lock;
447 };
449 /* Index to functions, as function prototypes. */
451 static int __devinit tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq);
453 static int tc35815_open(struct net_device *dev);
454 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
455 static void tc35815_tx_timeout(struct net_device *dev);
456 static irqreturn_t tc35815_interrupt(int irq, void *dev_id, struct pt_regs *regs);
457 static void tc35815_rx(struct net_device *dev);
458 static void tc35815_txdone(struct net_device *dev);
459 static int tc35815_close(struct net_device *dev);
460 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
461 static void tc35815_set_multicast_list(struct net_device *dev);
463 static void tc35815_chip_reset(struct net_device *dev);
464 static void tc35815_chip_init(struct net_device *dev);
465 static void tc35815_phy_chip_init(struct net_device *dev);
467 /* A list of all installed tc35815 devices. */
468 static struct net_device *root_tc35815_dev = NULL;
470 /*
471 * PCI device identifiers for "new style" Linux PCI Device Drivers
472 */
473 static struct pci_device_id tc35815_pci_tbl[] = {
474 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
475 { 0, }
476 };
478 MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
480 int
481 tc35815_probe(struct pci_dev *pdev,
482 const struct pci_device_id *ent)
483 {
484 int err = 0;
485 int ret;
486 unsigned long pci_memaddr;
487 unsigned int pci_irq_line;
489 printk(KERN_INFO "tc35815_probe: found device %#08x.%#08x\n", ent->vendor, ent->device);
491 err = pci_enable_device(pdev);
492 if (err)
493 return err;
495 pci_memaddr = pci_resource_start (pdev, 1);
497 printk(KERN_INFO " pci_memaddr=%#08lx resource_flags=%#08lx\n", pci_memaddr, pci_resource_flags (pdev, 0));
499 if (!pci_memaddr) {
500 printk(KERN_WARNING "no PCI MEM resources, aborting\n");
501 ret = -ENODEV;
502 goto err_out;
503 }
504 pci_irq_line = pdev->irq;
505 /* irq disabled. */
506 if (pci_irq_line == 0) {
507 printk(KERN_WARNING "no PCI irq, aborting\n");
508 ret = -ENODEV;
509 goto err_out;
510 }
512 ret = tc35815_probe1(pdev, pci_memaddr, pci_irq_line);
513 if (ret)
514 goto err_out;
516 pci_set_master(pdev);
518 return 0;
520 err_out:
521 pci_disable_device(pdev);
522 return ret;
523 }
525 static int __devinit tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq)
526 {
527 static unsigned version_printed = 0;
528 int i, ret;
529 struct tc35815_local *lp;
530 struct tc35815_regs *tr;
531 struct net_device *dev;
533 /* Allocate a new 'dev' if needed. */
534 dev = alloc_etherdev(sizeof(struct tc35815_local));
535 if (dev == NULL)
536 return -ENOMEM;
538 /*
539 * alloc_etherdev allocs and zeros dev->priv
540 */
541 lp = dev->priv;
543 if (tc35815_debug && version_printed++ == 0)
544 printk(KERN_DEBUG "%s", version);
546 /* Fill in the 'dev' fields. */
547 dev->irq = irq;
548 dev->base_addr = (unsigned long)ioremap(base_addr,
549 sizeof(struct tc35815_regs));
550 if (!dev->base_addr) {
551 ret = -ENOMEM;
552 goto err_out;
553 }
554 tr = (struct tc35815_regs*)dev->base_addr;
556 tc35815_chip_reset(dev);
558 /* Retrieve and print the ethernet address. */
559 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
560 ;
561 for (i = 0; i < 6; i += 2) {
562 unsigned short data;
563 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
564 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
565 ;
566 data = tc_readl(&tr->PROM_Data);
567 dev->dev_addr[i] = data & 0xff;
568 dev->dev_addr[i+1] = data >> 8;
569 }
571 /* Initialize the device structure. */
572 lp->pdev = pdev;
573 lp->next_module = root_tc35815_dev;
574 root_tc35815_dev = dev;
576 spin_lock_init(&lp->lock);
578 if (dev->mem_start > 0) {
579 lp->option = dev->mem_start;
580 if ((lp->option & TC35815_OPT_10M) &&
581 (lp->option & TC35815_OPT_100M)) {
582 /* if both speed speficied, auto select. */
583 lp->option &= ~(TC35815_OPT_10M | TC35815_OPT_100M);
584 }
585 }
586 //XXX fixme
587 lp->option |= TC35815_OPT_10M;
589 /* do auto negotiation */
590 tc35815_phy_chip_init(dev);
592 dev->open = tc35815_open;
593 dev->stop = tc35815_close;
594 dev->tx_timeout = tc35815_tx_timeout;
595 dev->watchdog_timeo = TX_TIMEOUT;
596 dev->hard_start_xmit = tc35815_send_packet;
597 dev->get_stats = tc35815_get_stats;
598 dev->set_multicast_list = tc35815_set_multicast_list;
599 SET_MODULE_OWNER(dev);
600 SET_NETDEV_DEV(dev, &pdev->dev);
602 ret = register_netdev(dev);
603 if (ret)
604 goto err_out_iounmap;
606 printk(KERN_INFO "%s: %s found at %#x, irq %d, MAC",
607 dev->name, cardname, base_addr, irq);
608 for (i = 0; i < 6; i++)
609 printk(" %2.2x", dev->dev_addr[i]);
610 printk("\n");
611 printk(KERN_INFO "%s: linkspeed %dMbps, %s Duplex\n",
612 dev->name, lp->linkspeed, lp->fullduplex ? "Full" : "Half");
614 return 0;
616 err_out_iounmap:
617 iounmap((void *) dev->base_addr);
618 err_out:
619 free_netdev(dev);
620 return ret;
621 }
624 static int
625 tc35815_init_queues(struct net_device *dev)
626 {
627 struct tc35815_local *lp = dev->priv;
628 int i;
629 unsigned long fd_addr;
631 if (!lp->fd_buf) {
632 if (sizeof(struct FDesc) +
633 sizeof(struct BDesc) * RX_BUF_PAGES +
634 sizeof(struct FDesc) * RX_FD_NUM +
635 sizeof(struct TxFD) * TX_FD_NUM > PAGE_SIZE * FD_PAGE_NUM) {
636 printk(KERN_WARNING "%s: Invalid Queue Size.\n", dev->name);
637 return -ENOMEM;
638 }
640 if ((lp->fd_buf = (void *)__get_free_pages(GFP_KERNEL, FD_PAGE_ORDER)) == 0)
641 return -ENOMEM;
642 for (i = 0; i < RX_BUF_PAGES; i++) {
643 if ((lp->data_buf[i] = (void *)get_zeroed_page(GFP_KERNEL)) == 0) {
644 while (--i >= 0) {
645 free_page((unsigned long)lp->data_buf[i]);
646 lp->data_buf[i] = 0;
647 }
648 free_page((unsigned long)lp->fd_buf);
649 lp->fd_buf = 0;
650 return -ENOMEM;
651 }
652 #ifdef __mips__
653 dma_cache_wback_inv((unsigned long)lp->data_buf[i], PAGE_SIZE * FD_PAGE_NUM);
654 #endif
655 }
656 #ifdef __mips__
657 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
658 #endif
659 } else {
660 clear_page(lp->fd_buf);
661 #ifdef __mips__
662 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
663 #endif
664 }
665 #ifdef __mips__
666 fd_addr = (unsigned long)vtonocache(lp->fd_buf);
667 #else
668 fd_addr = (unsigned long)lp->fd_buf;
669 #endif
671 /* Free Descriptors (for Receive) */
672 lp->rfd_base = (struct RxFD *)fd_addr;
673 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
674 for (i = 0; i < RX_FD_NUM; i++) {
675 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
676 }
677 lp->rfd_cur = lp->rfd_base;
678 lp->rfd_limit = (struct RxFD *)(fd_addr -
679 sizeof(struct FDesc) -
680 sizeof(struct BDesc) * 30);
682 /* Transmit Descriptors */
683 lp->tfd_base = (struct TxFD *)fd_addr;
684 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
685 for (i = 0; i < TX_FD_NUM; i++) {
686 lp->tfd_base[i].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[i+1]));
687 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
688 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
689 }
690 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[0]));
691 lp->tfd_start = 0;
692 lp->tfd_end = 0;
694 /* Buffer List (for Receive) */
695 lp->fbl_ptr = (struct FrFD *)fd_addr;
696 lp->fbl_ptr->fd.FDNext = cpu_to_le32(virt_to_bus(lp->fbl_ptr));
697 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_PAGES | FD_CownsFD);
698 for (i = 0; i < RX_BUF_PAGES; i++) {
699 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(virt_to_bus(lp->data_buf[i]));
700 /* BDID is index of FrFD.bd[] */
701 lp->fbl_ptr->bd[i].BDCtl =
702 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | PAGE_SIZE);
703 }
704 lp->fbl_curid = 0;
706 return 0;
707 }
709 static void
710 tc35815_clear_queues(struct net_device *dev)
711 {
712 struct tc35815_local *lp = dev->priv;
713 int i;
715 for (i = 0; i < TX_FD_NUM; i++) {
716 struct sk_buff *skb = (struct sk_buff *)
717 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
718 if (skb)
719 dev_kfree_skb_any(skb);
720 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
721 }
723 tc35815_init_queues(dev);
724 }
726 static void
727 tc35815_free_queues(struct net_device *dev)
728 {
729 struct tc35815_local *lp = dev->priv;
730 int i;
732 if (lp->tfd_base) {
733 for (i = 0; i < TX_FD_NUM; i++) {
734 struct sk_buff *skb = (struct sk_buff *)
735 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
736 if (skb)
737 dev_kfree_skb_any(skb);
738 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
739 }
740 }
742 lp->rfd_base = NULL;
743 lp->rfd_base = NULL;
744 lp->rfd_limit = NULL;
745 lp->rfd_cur = NULL;
746 lp->fbl_ptr = NULL;
748 for (i = 0; i < RX_BUF_PAGES; i++) {
749 if (lp->data_buf[i])
750 free_page((unsigned long)lp->data_buf[i]);
751 lp->data_buf[i] = 0;
752 }
753 if (lp->fd_buf)
754 __free_pages(lp->fd_buf, FD_PAGE_ORDER);
755 lp->fd_buf = NULL;
756 }
758 static void
759 dump_txfd(struct TxFD *fd)
760 {
761 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
762 le32_to_cpu(fd->fd.FDNext),
763 le32_to_cpu(fd->fd.FDSystem),
764 le32_to_cpu(fd->fd.FDStat),
765 le32_to_cpu(fd->fd.FDCtl));
766 printk("BD: ");
767 printk(" %08x %08x",
768 le32_to_cpu(fd->bd.BuffData),
769 le32_to_cpu(fd->bd.BDCtl));
770 printk("\n");
771 }
773 static int
774 dump_rxfd(struct RxFD *fd)
775 {
776 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
777 if (bd_count > 8)
778 bd_count = 8;
779 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
780 le32_to_cpu(fd->fd.FDNext),
781 le32_to_cpu(fd->fd.FDSystem),
782 le32_to_cpu(fd->fd.FDStat),
783 le32_to_cpu(fd->fd.FDCtl));
784 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
785 return 0;
786 printk("BD: ");
787 for (i = 0; i < bd_count; i++)
788 printk(" %08x %08x",
789 le32_to_cpu(fd->bd[i].BuffData),
790 le32_to_cpu(fd->bd[i].BDCtl));
791 printk("\n");
792 return bd_count;
793 }
795 static void
796 dump_frfd(struct FrFD *fd)
797 {
798 int i;
799 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
800 le32_to_cpu(fd->fd.FDNext),
801 le32_to_cpu(fd->fd.FDSystem),
802 le32_to_cpu(fd->fd.FDStat),
803 le32_to_cpu(fd->fd.FDCtl));
804 printk("BD: ");
805 for (i = 0; i < RX_BUF_PAGES; i++)
806 printk(" %08x %08x",
807 le32_to_cpu(fd->bd[i].BuffData),
808 le32_to_cpu(fd->bd[i].BDCtl));
809 printk("\n");
810 }
812 static void
813 panic_queues(struct net_device *dev)
814 {
815 struct tc35815_local *lp = dev->priv;
816 int i;
818 printk("TxFD base %p, start %d, end %d\n",
819 lp->tfd_base, lp->tfd_start, lp->tfd_end);
820 printk("RxFD base %p limit %p cur %p\n",
821 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
822 printk("FrFD %p\n", lp->fbl_ptr);
823 for (i = 0; i < TX_FD_NUM; i++)
824 dump_txfd(&lp->tfd_base[i]);
825 for (i = 0; i < RX_FD_NUM; i++) {
826 int bd_count = dump_rxfd(&lp->rfd_base[i]);
827 i += (bd_count + 1) / 2; /* skip BDs */
828 }
829 dump_frfd(lp->fbl_ptr);
830 panic("%s: Illegal queue state.", dev->name);
831 }
833 #if 0
834 static void print_buf(char *add, int length)
835 {
836 int i;
837 int len = length;
839 printk("print_buf(%08x)(%x)\n", (unsigned int) add,length);
841 if (len > 100)
842 len = 100;
843 for (i = 0; i < len; i++) {
844 printk(" %2.2X", (unsigned char) add[i]);
845 if (!(i % 16))
846 printk("\n");
847 }
848 printk("\n");
849 }
850 #endif
852 static void print_eth(char *add)
853 {
854 int i;
856 printk("print_eth(%08x)\n", (unsigned int) add);
857 for (i = 0; i < 6; i++)
858 printk(" %2.2X", (unsigned char) add[i + 6]);
859 printk(" =>");
860 for (i = 0; i < 6; i++)
861 printk(" %2.2X", (unsigned char) add[i]);
862 printk(" : %2.2X%2.2X\n", (unsigned char) add[12], (unsigned char) add[13]);
863 }
865 /*
866 * Open/initialize the board. This is called (in the current kernel)
867 * sometime after booting when the 'ifconfig' program is run.
868 *
869 * This routine should set everything up anew at each open, even
870 * registers that "should" only need to be set once at boot, so that
871 * there is non-reboot way to recover if something goes wrong.
872 */
873 static int
874 tc35815_open(struct net_device *dev)
875 {
876 struct tc35815_local *lp = dev->priv;
877 /*
878 * This is used if the interrupt line can turned off (shared).
879 * See 3c503.c for an example of selecting the IRQ at config-time.
880 */
882 if (dev->irq == 0 ||
883 request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED, cardname, dev)) {
884 return -EAGAIN;
885 }
887 tc35815_chip_reset(dev);
889 if (tc35815_init_queues(dev) != 0) {
890 free_irq(dev->irq, dev);
891 return -EAGAIN;
892 }
894 /* Reset the hardware here. Don't forget to set the station address. */
895 tc35815_chip_init(dev);
897 lp->tbusy = 0;
898 netif_start_queue(dev);
900 return 0;
901 }
903 static void tc35815_tx_timeout(struct net_device *dev)
904 {
905 struct tc35815_local *lp = dev->priv;
906 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
907 unsigned long flags;
909 spin_lock_irqsave(&lp->lock, flags);
910 printk(KERN_WARNING "%s: transmit timed out, status %#lx\n",
911 dev->name, tc_readl(&tr->Tx_Stat));
912 /* Try to restart the adaptor. */
913 tc35815_chip_reset(dev);
914 tc35815_clear_queues(dev);
915 tc35815_chip_init(dev);
916 lp->tbusy=0;
917 spin_unlock_irqrestore(&lp->lock, flags);
918 dev->trans_start = jiffies;
919 netif_wake_queue(dev);
920 }
922 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
923 {
924 struct tc35815_local *lp = dev->priv;
925 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
927 if (netif_queue_stopped(dev)) {
928 /*
929 * If we get here, some higher level has decided we are broken.
930 * There should really be a "kick me" function call instead.
931 */
932 int tickssofar = jiffies - dev->trans_start;
933 if (tickssofar < 5)
934 return 1;
935 printk(KERN_WARNING "%s: transmit timed out, status %#lx\n",
936 dev->name, tc_readl(&tr->Tx_Stat));
937 /* Try to restart the adaptor. */
938 tc35815_chip_reset(dev);
939 tc35815_clear_queues(dev);
940 tc35815_chip_init(dev);
941 lp->tbusy=0;
942 dev->trans_start = jiffies;
943 netif_wake_queue(dev);
944 }
946 /*
947 * Block a timer-based transmit from overlapping. This could better be
948 * done with atomic_swap(1, lp->tbusy), but set_bit() works as well.
949 */
950 if (test_and_set_bit(0, (void*)&lp->tbusy) != 0) {
951 printk(KERN_WARNING "%s: Transmitter access conflict.\n", dev->name);
952 dev_kfree_skb_any(skb);
953 } else {
954 short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
955 unsigned char *buf = skb->data;
956 struct TxFD *txfd = &lp->tfd_base[lp->tfd_start];
957 unsigned long flags;
958 lp->stats.tx_bytes += skb->len;
961 #ifdef __mips__
962 dma_cache_wback_inv((unsigned long)buf, length);
963 #endif
965 spin_lock_irqsave(&lp->lock, flags);
967 /* failsafe... */
968 if (lp->tfd_start != lp->tfd_end)
969 tc35815_txdone(dev);
972 txfd->bd.BuffData = cpu_to_le32(virt_to_bus(buf));
974 txfd->bd.BDCtl = cpu_to_le32(length);
975 txfd->fd.FDSystem = cpu_to_le32((__u32)skb);
976 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
978 if (lp->tfd_start == lp->tfd_end) {
979 /* Start DMA Transmitter. */
980 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
981 #ifdef GATHER_TXINT
982 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
983 #endif
984 if (tc35815_debug > 2) {
985 printk("%s: starting TxFD.\n", dev->name);
986 dump_txfd(txfd);
987 if (tc35815_debug > 3)
988 print_eth(buf);
989 }
990 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
991 } else {
992 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
993 if (tc35815_debug > 2) {
994 printk("%s: queueing TxFD.\n", dev->name);
995 dump_txfd(txfd);
996 if (tc35815_debug > 3)
997 print_eth(buf);
998 }
999 }
1000 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1002 dev->trans_start = jiffies;
1004 if ((lp->tfd_start + 1) % TX_FD_NUM != lp->tfd_end) {
1005 /* we can send another packet */
1006 lp->tbusy = 0;
1007 netif_start_queue(dev);
1008 } else {
1009 netif_stop_queue(dev);
1010 if (tc35815_debug > 1)
1011 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1013 spin_unlock_irqrestore(&lp->lock, flags);
1016 return 0;
1019 #define FATAL_ERROR_INT \
1020 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1021 static void tc35815_fatal_error_interrupt(struct net_device *dev, int status)
1023 static int count;
1024 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1025 dev->name, status);
1027 if (status & Int_IntPCI)
1028 printk(" IntPCI");
1029 if (status & Int_DmParErr)
1030 printk(" DmParErr");
1031 if (status & Int_IntNRAbt)
1032 printk(" IntNRAbt");
1033 printk("\n");
1034 if (count++ > 100)
1035 panic("%s: Too many fatal errors.", dev->name);
1036 printk(KERN_WARNING "%s: Resetting %s...\n", dev->name, cardname);
1037 /* Try to restart the adaptor. */
1038 tc35815_chip_reset(dev);
1039 tc35815_clear_queues(dev);
1040 tc35815_chip_init(dev);
1043 /*
1044 * The typical workload of the driver:
1045 * Handle the network interface interrupts.
1046 */
1047 static irqreturn_t tc35815_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1049 struct net_device *dev = dev_id;
1050 struct tc35815_regs *tr;
1051 struct tc35815_local *lp;
1052 int status, boguscount = 0;
1053 int handled = 0;
1055 if (dev == NULL) {
1056 printk(KERN_WARNING "%s: irq %d for unknown device.\n", cardname, irq);
1057 return IRQ_NONE;
1060 tr = (struct tc35815_regs*)dev->base_addr;
1061 lp = dev->priv;
1063 do {
1064 status = tc_readl(&tr->Int_Src);
1065 if (status == 0)
1066 break;
1067 handled = 1;
1068 tc_writel(status, &tr->Int_Src); /* write to clear */
1070 /* Fatal errors... */
1071 if (status & FATAL_ERROR_INT) {
1072 tc35815_fatal_error_interrupt(dev, status);
1073 break;
1075 /* recoverable errors */
1076 if (status & Int_IntFDAEx) {
1077 /* disable FDAEx int. (until we make rooms...) */
1078 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1079 printk(KERN_WARNING
1080 "%s: Free Descriptor Area Exhausted (%#x).\n",
1081 dev->name, status);
1082 lp->stats.rx_dropped++;
1084 if (status & Int_IntBLEx) {
1085 /* disable BLEx int. (until we make rooms...) */
1086 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1087 printk(KERN_WARNING
1088 "%s: Buffer List Exhausted (%#x).\n",
1089 dev->name, status);
1090 lp->stats.rx_dropped++;
1092 if (status & Int_IntExBD) {
1093 printk(KERN_WARNING
1094 "%s: Excessive Buffer Descriptiors (%#x).\n",
1095 dev->name, status);
1096 lp->stats.rx_length_errors++;
1098 /* normal notification */
1099 if (status & Int_IntMacRx) {
1100 /* Got a packet(s). */
1101 lp->lstats.rx_ints++;
1102 tc35815_rx(dev);
1104 if (status & Int_IntMacTx) {
1105 lp->lstats.tx_ints++;
1106 tc35815_txdone(dev);
1108 } while (++boguscount < 20) ;
1110 return IRQ_RETVAL(handled);
1113 /* We have a good packet(s), get it/them out of the buffers. */
1114 static void
1115 tc35815_rx(struct net_device *dev)
1117 struct tc35815_local *lp = dev->priv;
1118 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1119 unsigned int fdctl;
1120 int i;
1121 int buf_free_count = 0;
1122 int fd_free_count = 0;
1124 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1125 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1126 int pkt_len = fdctl & FD_FDLength_MASK;
1127 struct RxFD *next_rfd;
1128 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1130 if (tc35815_debug > 2)
1131 dump_rxfd(lp->rfd_cur);
1132 if (status & Rx_Good) {
1133 /* Malloc up new buffer. */
1134 struct sk_buff *skb;
1135 unsigned char *data;
1136 int cur_bd, offset;
1138 lp->stats.rx_bytes += pkt_len;
1140 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1141 if (skb == NULL) {
1142 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1143 dev->name);
1144 lp->stats.rx_dropped++;
1145 break;
1147 skb_reserve(skb, 2); /* 16 bit alignment */
1148 skb->dev = dev;
1150 data = skb_put(skb, pkt_len);
1152 /* copy from receive buffer */
1153 cur_bd = 0;
1154 offset = 0;
1155 while (offset < pkt_len && cur_bd < bd_count) {
1156 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1157 BD_BuffLength_MASK;
1158 void *rxbuf =
1159 bus_to_virt(le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData));
1160 #ifdef __mips__
1161 dma_cache_inv((unsigned long)rxbuf, len);
1162 #endif
1163 memcpy(data + offset, rxbuf, len);
1164 offset += len;
1165 cur_bd++;
1167 #if 0
1168 print_buf(data,pkt_len);
1169 #endif
1170 if (tc35815_debug > 3)
1171 print_eth(data);
1172 skb->protocol = eth_type_trans(skb, dev);
1173 netif_rx(skb);
1174 lp->stats.rx_packets++;
1175 } else {
1176 lp->stats.rx_errors++;
1177 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1178 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1179 status &= ~(Rx_LongErr|Rx_CRCErr);
1180 status |= Rx_Over;
1182 if (status & Rx_LongErr) lp->stats.rx_length_errors++;
1183 if (status & Rx_Over) lp->stats.rx_fifo_errors++;
1184 if (status & Rx_CRCErr) lp->stats.rx_crc_errors++;
1185 if (status & Rx_Align) lp->stats.rx_frame_errors++;
1188 if (bd_count > 0) {
1189 /* put Free Buffer back to controller */
1190 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1191 unsigned char id =
1192 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1193 if (id >= RX_BUF_PAGES) {
1194 printk("%s: invalid BDID.\n", dev->name);
1195 panic_queues(dev);
1197 /* free old buffers */
1198 while (lp->fbl_curid != id) {
1199 bdctl = le32_to_cpu(lp->fbl_ptr->bd[lp->fbl_curid].BDCtl);
1200 if (bdctl & BD_CownsBD) {
1201 printk("%s: Freeing invalid BD.\n",
1202 dev->name);
1203 panic_queues(dev);
1205 /* pass BD to controler */
1206 /* Note: BDLength was modified by chip. */
1207 lp->fbl_ptr->bd[lp->fbl_curid].BDCtl =
1208 cpu_to_le32(BD_CownsBD |
1209 (lp->fbl_curid << BD_RxBDID_SHIFT) |
1210 PAGE_SIZE);
1211 lp->fbl_curid =
1212 (lp->fbl_curid + 1) % RX_BUF_PAGES;
1213 if (tc35815_debug > 2) {
1214 printk("%s: Entering new FBD %d\n",
1215 dev->name, lp->fbl_curid);
1216 dump_frfd(lp->fbl_ptr);
1218 buf_free_count++;
1222 /* put RxFD back to controller */
1223 next_rfd = bus_to_virt(le32_to_cpu(lp->rfd_cur->fd.FDNext));
1224 #ifdef __mips__
1225 next_rfd = (struct RxFD *)vtonocache(next_rfd);
1226 #endif
1227 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1228 printk("%s: RxFD FDNext invalid.\n", dev->name);
1229 panic_queues(dev);
1231 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1232 /* pass FD to controler */
1233 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); /* for debug */
1234 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1235 lp->rfd_cur++;
1236 fd_free_count++;
1239 lp->rfd_cur = next_rfd;
1242 /* re-enable BL/FDA Exhaust interrupts. */
1243 if (fd_free_count) {
1244 tc_writel(tc_readl(&tr->Int_En) | Int_FDAExEn, &tr->Int_En);
1245 if (buf_free_count)
1246 tc_writel(tc_readl(&tr->Int_En) | Int_BLExEn, &tr->Int_En);
1250 #ifdef NO_CHECK_CARRIER
1251 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1252 #else
1253 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1254 #endif
1256 static void
1257 tc35815_check_tx_stat(struct net_device *dev, int status)
1259 struct tc35815_local *lp = dev->priv;
1260 const char *msg = NULL;
1262 /* count collisions */
1263 if (status & Tx_ExColl)
1264 lp->stats.collisions += 16;
1265 if (status & Tx_TxColl_MASK)
1266 lp->stats.collisions += status & Tx_TxColl_MASK;
1268 /* WORKAROUND: ignore LostCrS in full duplex operation */
1269 if (lp->fullduplex)
1270 status &= ~Tx_NCarr;
1272 if (!(status & TX_STA_ERR)) {
1273 /* no error. */
1274 lp->stats.tx_packets++;
1275 return;
1278 lp->stats.tx_errors++;
1279 if (status & Tx_ExColl) {
1280 lp->stats.tx_aborted_errors++;
1281 msg = "Excessive Collision.";
1283 if (status & Tx_Under) {
1284 lp->stats.tx_fifo_errors++;
1285 msg = "Tx FIFO Underrun.";
1287 if (status & Tx_Defer) {
1288 lp->stats.tx_fifo_errors++;
1289 msg = "Excessive Deferral.";
1291 #ifndef NO_CHECK_CARRIER
1292 if (status & Tx_NCarr) {
1293 lp->stats.tx_carrier_errors++;
1294 msg = "Lost Carrier Sense.";
1296 #endif
1297 if (status & Tx_LateColl) {
1298 lp->stats.tx_aborted_errors++;
1299 msg = "Late Collision.";
1301 if (status & Tx_TxPar) {
1302 lp->stats.tx_fifo_errors++;
1303 msg = "Transmit Parity Error.";
1305 if (status & Tx_SQErr) {
1306 lp->stats.tx_heartbeat_errors++;
1307 msg = "Signal Quality Error.";
1309 if (msg)
1310 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1313 static void
1314 tc35815_txdone(struct net_device *dev)
1316 struct tc35815_local *lp = dev->priv;
1317 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1318 struct TxFD *txfd;
1319 unsigned int fdctl;
1320 int num_done = 0;
1322 txfd = &lp->tfd_base[lp->tfd_end];
1323 while (lp->tfd_start != lp->tfd_end &&
1324 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1325 int status = le32_to_cpu(txfd->fd.FDStat);
1326 struct sk_buff *skb;
1327 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1329 if (tc35815_debug > 2) {
1330 printk("%s: complete TxFD.\n", dev->name);
1331 dump_txfd(txfd);
1333 tc35815_check_tx_stat(dev, status);
1335 skb = (struct sk_buff *)le32_to_cpu(txfd->fd.FDSystem);
1336 if (skb) {
1337 dev_kfree_skb_any(skb);
1339 txfd->fd.FDSystem = cpu_to_le32(0);
1341 num_done++;
1342 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1343 txfd = &lp->tfd_base[lp->tfd_end];
1344 if ((fdnext & ~FD_Next_EOL) != virt_to_bus(txfd)) {
1345 printk("%s: TxFD FDNext invalid.\n", dev->name);
1346 panic_queues(dev);
1348 if (fdnext & FD_Next_EOL) {
1349 /* DMA Transmitter has been stopping... */
1350 if (lp->tfd_end != lp->tfd_start) {
1351 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1352 struct TxFD* txhead = &lp->tfd_base[head];
1353 int qlen = (lp->tfd_start + TX_FD_NUM
1354 - lp->tfd_end) % TX_FD_NUM;
1356 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1357 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1358 panic_queues(dev);
1360 /* log max queue length */
1361 if (lp->lstats.max_tx_qlen < qlen)
1362 lp->lstats.max_tx_qlen = qlen;
1365 /* start DMA Transmitter again */
1366 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1367 #ifdef GATHER_TXINT
1368 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1369 #endif
1370 if (tc35815_debug > 2) {
1371 printk("%s: start TxFD on queue.\n",
1372 dev->name);
1373 dump_txfd(txfd);
1375 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
1377 break;
1381 if (num_done > 0 && lp->tbusy) {
1382 lp->tbusy = 0;
1383 netif_start_queue(dev);
1387 /* The inverse routine to tc35815_open(). */
1388 static int
1389 tc35815_close(struct net_device *dev)
1391 struct tc35815_local *lp = dev->priv;
1393 lp->tbusy = 1;
1394 netif_stop_queue(dev);
1396 /* Flush the Tx and disable Rx here. */
1398 tc35815_chip_reset(dev);
1399 free_irq(dev->irq, dev);
1401 tc35815_free_queues(dev);
1403 return 0;
1406 /*
1407 * Get the current statistics.
1408 * This may be called with the card open or closed.
1409 */
1410 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1412 struct tc35815_local *lp = dev->priv;
1413 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1414 unsigned long flags;
1416 if (netif_running(dev)) {
1417 spin_lock_irqsave(&lp->lock, flags);
1418 /* Update the statistics from the device registers. */
1419 lp->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
1420 spin_unlock_irqrestore(&lp->lock, flags);
1423 return &lp->stats;
1426 static void tc35815_set_cam_entry(struct tc35815_regs *tr, int index, unsigned char *addr)
1428 int cam_index = index * 6;
1429 unsigned long cam_data;
1430 unsigned long saved_addr;
1431 saved_addr = tc_readl(&tr->CAM_Adr);
1433 if (tc35815_debug > 1) {
1434 int i;
1435 printk(KERN_DEBUG "%s: CAM %d:", cardname, index);
1436 for (i = 0; i < 6; i++)
1437 printk(" %02x", addr[i]);
1438 printk("\n");
1440 if (index & 1) {
1441 /* read modify write */
1442 tc_writel(cam_index - 2, &tr->CAM_Adr);
1443 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1444 cam_data |= addr[0] << 8 | addr[1];
1445 tc_writel(cam_data, &tr->CAM_Data);
1446 /* write whole word */
1447 tc_writel(cam_index + 2, &tr->CAM_Adr);
1448 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1449 tc_writel(cam_data, &tr->CAM_Data);
1450 } else {
1451 /* write whole word */
1452 tc_writel(cam_index, &tr->CAM_Adr);
1453 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1454 tc_writel(cam_data, &tr->CAM_Data);
1455 /* read modify write */
1456 tc_writel(cam_index + 4, &tr->CAM_Adr);
1457 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1458 cam_data |= addr[4] << 24 | (addr[5] << 16);
1459 tc_writel(cam_data, &tr->CAM_Data);
1462 if (tc35815_debug > 2) {
1463 int i;
1464 for (i = cam_index / 4; i < cam_index / 4 + 2; i++) {
1465 tc_writel(i * 4, &tr->CAM_Adr);
1466 printk("CAM 0x%x: %08lx",
1467 i * 4, tc_readl(&tr->CAM_Data));
1470 tc_writel(saved_addr, &tr->CAM_Adr);
1474 /*
1475 * Set or clear the multicast filter for this adaptor.
1476 * num_addrs == -1 Promiscuous mode, receive all packets
1477 * num_addrs == 0 Normal mode, clear multicast list
1478 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1479 * and do best-effort filtering.
1480 */
1481 static void
1482 tc35815_set_multicast_list(struct net_device *dev)
1484 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1486 if (dev->flags&IFF_PROMISC)
1488 /* Enable promiscuous mode */
1489 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1491 else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
1493 /* CAM 0, 1, 20 are reserved. */
1494 /* Disable promiscuous mode, use normal mode. */
1495 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1497 else if(dev->mc_count)
1499 struct dev_mc_list* cur_addr = dev->mc_list;
1500 int i;
1501 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1503 tc_writel(0, &tr->CAM_Ctl);
1504 /* Walk the address list, and load the filter */
1505 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1506 if (!cur_addr)
1507 break;
1508 /* entry 0,1 is reserved. */
1509 tc35815_set_cam_entry(tr, i + 2, cur_addr->dmi_addr);
1510 ena_bits |= CAM_Ena_Bit(i + 2);
1512 tc_writel(ena_bits, &tr->CAM_Ena);
1513 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1515 else {
1516 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1517 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1521 static unsigned long tc_phy_read(struct net_device *dev, struct tc35815_regs *tr, int phy, int phy_reg)
1523 struct tc35815_local *lp = dev->priv;
1524 unsigned long data;
1525 unsigned long flags;
1527 spin_lock_irqsave(&lp->lock, flags);
1529 tc_writel(MD_CA_Busy | (phy << 5) | phy_reg, &tr->MD_CA);
1530 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1532 data = tc_readl(&tr->MD_Data);
1533 spin_unlock_irqrestore(&lp->lock, flags);
1534 return data;
1537 static void tc_phy_write(struct net_device *dev, unsigned long d, struct tc35815_regs *tr, int phy, int phy_reg)
1539 struct tc35815_local *lp = dev->priv;
1540 unsigned long flags;
1542 spin_lock_irqsave(&lp->lock, flags);
1544 tc_writel(d, &tr->MD_Data);
1545 tc_writel(MD_CA_Busy | MD_CA_Wr | (phy << 5) | phy_reg, &tr->MD_CA);
1546 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1548 spin_unlock_irqrestore(&lp->lock, flags);
1551 static void tc35815_phy_chip_init(struct net_device *dev)
1553 struct tc35815_local *lp = dev->priv;
1554 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1555 static int first = 1;
1556 unsigned short ctl;
1558 if (first) {
1559 unsigned short id0, id1;
1560 int count;
1561 first = 0;
1563 /* first data written to the PHY will be an ID number */
1564 tc_phy_write(dev, 0, tr, 0, MII_CONTROL); /* ID:0 */
1565 #if 0
1566 tc_phy_write(dev, MIICNTL_RESET, tr, 0, MII_CONTROL);
1567 printk(KERN_INFO "%s: Resetting PHY...", dev->name);
1568 while (tc_phy_read(dev, tr, 0, MII_CONTROL) & MIICNTL_RESET)
1570 printk("\n");
1571 tc_phy_write(dev, MIICNTL_AUTO|MIICNTL_SPEED|MIICNTL_FDX, tr, 0,
1572 MII_CONTROL);
1573 #endif
1574 id0 = tc_phy_read(dev, tr, 0, MII_PHY_ID0);
1575 id1 = tc_phy_read(dev, tr, 0, MII_PHY_ID1);
1576 printk(KERN_DEBUG "%s: PHY ID %04x %04x\n", dev->name,
1577 id0, id1);
1578 if (lp->option & TC35815_OPT_10M) {
1579 lp->linkspeed = 10;
1580 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1581 } else if (lp->option & TC35815_OPT_100M) {
1582 lp->linkspeed = 100;
1583 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1584 } else {
1585 /* auto negotiation */
1586 unsigned long neg_result;
1587 tc_phy_write(dev, MIICNTL_AUTO | MIICNTL_RST_AUTO, tr, 0, MII_CONTROL);
1588 printk(KERN_INFO "%s: Auto Negotiation...", dev->name);
1589 count = 0;
1590 while (!(tc_phy_read(dev, tr, 0, MII_STATUS) & MIISTAT_AUTO_DONE)) {
1591 if (count++ > 5000) {
1592 printk(" failed. Assume 10Mbps\n");
1593 lp->linkspeed = 10;
1594 lp->fullduplex = 0;
1595 goto done;
1597 if (count % 512 == 0)
1598 printk(".");
1599 mdelay(1);
1601 printk(" done.\n");
1602 neg_result = tc_phy_read(dev, tr, 0, MII_ANLPAR);
1603 if (neg_result & (MII_AN_TX_FDX | MII_AN_TX_HDX))
1604 lp->linkspeed = 100;
1605 else
1606 lp->linkspeed = 10;
1607 if (neg_result & (MII_AN_TX_FDX | MII_AN_10_FDX))
1608 lp->fullduplex = 1;
1609 else
1610 lp->fullduplex = 0;
1611 done:
1616 ctl = 0;
1617 if (lp->linkspeed == 100)
1618 ctl |= MIICNTL_SPEED;
1619 if (lp->fullduplex)
1620 ctl |= MIICNTL_FDX;
1621 tc_phy_write(dev, ctl, tr, 0, MII_CONTROL);
1623 if (lp->fullduplex) {
1624 tc_writel(tc_readl(&tr->MAC_Ctl) | MAC_FullDup, &tr->MAC_Ctl);
1628 static void tc35815_chip_reset(struct net_device *dev)
1630 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1632 /* reset the controller */
1633 tc_writel(MAC_Reset, &tr->MAC_Ctl);
1634 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset)
1637 tc_writel(0, &tr->MAC_Ctl);
1639 /* initialize registers to default value */
1640 tc_writel(0, &tr->DMA_Ctl);
1641 tc_writel(0, &tr->TxThrsh);
1642 tc_writel(0, &tr->TxPollCtr);
1643 tc_writel(0, &tr->RxFragSize);
1644 tc_writel(0, &tr->Int_En);
1645 tc_writel(0, &tr->FDA_Bas);
1646 tc_writel(0, &tr->FDA_Lim);
1647 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
1648 tc_writel(0, &tr->CAM_Ctl);
1649 tc_writel(0, &tr->Tx_Ctl);
1650 tc_writel(0, &tr->Rx_Ctl);
1651 tc_writel(0, &tr->CAM_Ena);
1652 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
1656 static void tc35815_chip_init(struct net_device *dev)
1658 struct tc35815_local *lp = dev->priv;
1659 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1660 unsigned long flags;
1661 unsigned long txctl = TX_CTL_CMD;
1663 tc35815_phy_chip_init(dev);
1665 /* load station address to CAM */
1666 tc35815_set_cam_entry(tr, CAM_ENTRY_SOURCE, dev->dev_addr);
1668 /* Enable CAM (broadcast and unicast) */
1669 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1670 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1672 spin_lock_irqsave(&lp->lock, flags);
1674 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
1676 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
1677 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
1678 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
1679 tc_writel(INT_EN_CMD, &tr->Int_En);
1681 /* set queues */
1682 tc_writel(virt_to_bus(lp->rfd_base), &tr->FDA_Bas);
1683 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
1684 &tr->FDA_Lim);
1685 /*
1686 * Activation method:
1687 * First, enable eht MAC Transmitter and the DMA Receive circuits.
1688 * Then enable the DMA Transmitter and the MAC Receive circuits.
1689 */
1690 tc_writel(virt_to_bus(lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
1691 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
1692 /* start MAC transmitter */
1693 /* WORKAROUND: ignore LostCrS in full duplex operation */
1694 if (lp->fullduplex)
1695 txctl = TX_CTL_CMD & ~Tx_EnLCarr;
1696 #ifdef GATHER_TXINT
1697 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
1698 #endif
1699 tc_writel(txctl, &tr->Tx_Ctl);
1700 #if 0 /* No need to polling */
1701 tc_writel(virt_to_bus(lp->tfd_base), &tr->TxFrmPtr); /* start DMA transmitter */
1702 #endif
1703 spin_unlock_irqrestore(&lp->lock, flags);
1706 /* XXX */
1707 void
1708 tc35815_killall(void)
1710 struct net_device *dev;
1712 for (dev = root_tc35815_dev; dev; dev = ((struct tc35815_local *)dev->priv)->next_module) {
1713 if (dev->flags&IFF_UP){
1714 dev->stop(dev);
1719 static struct pci_driver tc35815_driver = {
1720 .name = TC35815_MODULE_NAME,
1721 .probe = tc35815_probe,
1722 .remove = NULL,
1723 .id_table = tc35815_pci_tbl,
1724 };
1726 static int __init tc35815_init_module(void)
1728 return pci_module_init(&tc35815_driver);
1731 static void __exit tc35815_cleanup_module(void)
1733 struct net_device *next_dev;
1735 while (root_tc35815_dev) {
1736 struct net_device *dev = root_tc35815_dev;
1737 next_dev = ((struct tc35815_local *)dev->priv)->next_module;
1738 iounmap((void *)(dev->base_addr));
1739 unregister_netdev(dev);
1740 free_netdev(dev);
1741 root_tc35815_dev = next_dev;
1744 module_init(tc35815_init_module);
1745 module_exit(tc35815_cleanup_module);