ia64/linux-2.6.18-xen.hg

view drivers/net/sunhme.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 3e8752eb6d9c
children
line source
1 /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
4 *
5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 2006 David S. Miller (davem@davemloft.net)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/in.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/ethtool.h>
28 #include <linux/mii.h>
29 #include <linux/crc32.h>
30 #include <linux/random.h>
31 #include <linux/errno.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/bitops.h>
37 #include <asm/system.h>
38 #include <asm/io.h>
39 #include <asm/dma.h>
40 #include <asm/byteorder.h>
42 #ifdef CONFIG_SPARC
43 #include <asm/idprom.h>
44 #include <asm/sbus.h>
45 #include <asm/openprom.h>
46 #include <asm/oplib.h>
47 #include <asm/prom.h>
48 #include <asm/auxio.h>
49 #endif
50 #include <asm/uaccess.h>
52 #include <asm/pgtable.h>
53 #include <asm/irq.h>
55 #ifdef CONFIG_PCI
56 #include <linux/pci.h>
57 #ifdef CONFIG_SPARC
58 #include <asm/pbm.h>
59 #endif
60 #endif
62 #include "sunhme.h"
64 #define DRV_NAME "sunhme"
65 #define DRV_VERSION "3.00"
66 #define DRV_RELDATE "June 23, 2006"
67 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
69 static char version[] =
70 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
72 MODULE_VERSION(DRV_VERSION);
73 MODULE_AUTHOR(DRV_AUTHOR);
74 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
75 MODULE_LICENSE("GPL");
77 static int macaddr[6];
79 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
80 module_param_array(macaddr, int, NULL, 0);
81 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
83 #ifdef CONFIG_SBUS
84 static struct quattro *qfe_sbus_list;
85 #endif
87 #ifdef CONFIG_PCI
88 static struct quattro *qfe_pci_list;
89 #endif
91 #undef HMEDEBUG
92 #undef SXDEBUG
93 #undef RXDEBUG
94 #undef TXDEBUG
95 #undef TXLOGGING
97 #ifdef TXLOGGING
98 struct hme_tx_logent {
99 unsigned int tstamp;
100 int tx_new, tx_old;
101 unsigned int action;
102 #define TXLOG_ACTION_IRQ 0x01
103 #define TXLOG_ACTION_TXMIT 0x02
104 #define TXLOG_ACTION_TBUSY 0x04
105 #define TXLOG_ACTION_NBUFS 0x08
106 unsigned int status;
107 };
108 #define TX_LOG_LEN 128
109 static struct hme_tx_logent tx_log[TX_LOG_LEN];
110 static int txlog_cur_entry;
111 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
112 {
113 struct hme_tx_logent *tlp;
114 unsigned long flags;
116 save_and_cli(flags);
117 tlp = &tx_log[txlog_cur_entry];
118 tlp->tstamp = (unsigned int)jiffies;
119 tlp->tx_new = hp->tx_new;
120 tlp->tx_old = hp->tx_old;
121 tlp->action = a;
122 tlp->status = s;
123 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
124 restore_flags(flags);
125 }
126 static __inline__ void tx_dump_log(void)
127 {
128 int i, this;
130 this = txlog_cur_entry;
131 for (i = 0; i < TX_LOG_LEN; i++) {
132 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
133 tx_log[this].tstamp,
134 tx_log[this].tx_new, tx_log[this].tx_old,
135 tx_log[this].action, tx_log[this].status);
136 this = (this + 1) & (TX_LOG_LEN - 1);
137 }
138 }
139 static __inline__ void tx_dump_ring(struct happy_meal *hp)
140 {
141 struct hmeal_init_block *hb = hp->happy_block;
142 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
143 int i;
145 for (i = 0; i < TX_RING_SIZE; i+=4) {
146 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
147 i, i + 4,
148 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
149 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
150 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
151 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
152 }
153 }
154 #else
155 #define tx_add_log(hp, a, s) do { } while(0)
156 #define tx_dump_log() do { } while(0)
157 #define tx_dump_ring(hp) do { } while(0)
158 #endif
160 #ifdef HMEDEBUG
161 #define HMD(x) printk x
162 #else
163 #define HMD(x)
164 #endif
166 /* #define AUTO_SWITCH_DEBUG */
168 #ifdef AUTO_SWITCH_DEBUG
169 #define ASD(x) printk x
170 #else
171 #define ASD(x)
172 #endif
174 #define DEFAULT_IPG0 16 /* For lance-mode only */
175 #define DEFAULT_IPG1 8 /* For all modes */
176 #define DEFAULT_IPG2 4 /* For all modes */
177 #define DEFAULT_JAMSIZE 4 /* Toe jam */
179 /* NOTE: In the descriptor writes one _must_ write the address
180 * member _first_. The card must not be allowed to see
181 * the updated descriptor flags until the address is
182 * correct. I've added a write memory barrier between
183 * the two stores so that I can sleep well at night... -DaveM
184 */
186 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
187 static void sbus_hme_write32(void __iomem *reg, u32 val)
188 {
189 sbus_writel(val, reg);
190 }
192 static u32 sbus_hme_read32(void __iomem *reg)
193 {
194 return sbus_readl(reg);
195 }
197 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
198 {
199 rxd->rx_addr = addr;
200 wmb();
201 rxd->rx_flags = flags;
202 }
204 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
205 {
206 txd->tx_addr = addr;
207 wmb();
208 txd->tx_flags = flags;
209 }
211 static u32 sbus_hme_read_desc32(u32 *p)
212 {
213 return *p;
214 }
216 static void pci_hme_write32(void __iomem *reg, u32 val)
217 {
218 writel(val, reg);
219 }
221 static u32 pci_hme_read32(void __iomem *reg)
222 {
223 return readl(reg);
224 }
226 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
227 {
228 rxd->rx_addr = cpu_to_le32(addr);
229 wmb();
230 rxd->rx_flags = cpu_to_le32(flags);
231 }
233 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
234 {
235 txd->tx_addr = cpu_to_le32(addr);
236 wmb();
237 txd->tx_flags = cpu_to_le32(flags);
238 }
240 static u32 pci_hme_read_desc32(u32 *p)
241 {
242 return cpu_to_le32p(p);
243 }
245 #define hme_write32(__hp, __reg, __val) \
246 ((__hp)->write32((__reg), (__val)))
247 #define hme_read32(__hp, __reg) \
248 ((__hp)->read32(__reg))
249 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
250 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
251 #define hme_write_txd(__hp, __txd, __flags, __addr) \
252 ((__hp)->write_txd((__txd), (__flags), (__addr)))
253 #define hme_read_desc32(__hp, __p) \
254 ((__hp)->read_desc32(__p))
255 #define hme_dma_map(__hp, __ptr, __size, __dir) \
256 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
257 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
259 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
261 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
262 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
263 #else
264 #ifdef CONFIG_SBUS
265 /* SBUS only compilation */
266 #define hme_write32(__hp, __reg, __val) \
267 sbus_writel((__val), (__reg))
268 #define hme_read32(__hp, __reg) \
269 sbus_readl(__reg)
270 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
271 do { (__rxd)->rx_addr = (__addr); \
272 wmb(); \
273 (__rxd)->rx_flags = (__flags); \
274 } while(0)
275 #define hme_write_txd(__hp, __txd, __flags, __addr) \
276 do { (__txd)->tx_addr = (__addr); \
277 wmb(); \
278 (__txd)->tx_flags = (__flags); \
279 } while(0)
280 #define hme_read_desc32(__hp, __p) (*(__p))
281 #define hme_dma_map(__hp, __ptr, __size, __dir) \
282 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
283 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
285 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
287 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
289 #else
290 /* PCI only compilation */
291 #define hme_write32(__hp, __reg, __val) \
292 writel((__val), (__reg))
293 #define hme_read32(__hp, __reg) \
294 readl(__reg)
295 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
296 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
297 wmb(); \
298 (__rxd)->rx_flags = cpu_to_le32(__flags); \
299 } while(0)
300 #define hme_write_txd(__hp, __txd, __flags, __addr) \
301 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
302 wmb(); \
303 (__txd)->tx_flags = cpu_to_le32(__flags); \
304 } while(0)
305 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
306 #define hme_dma_map(__hp, __ptr, __size, __dir) \
307 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
308 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
309 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
310 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
311 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
312 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
313 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
314 #endif
315 #endif
318 #ifdef SBUS_DMA_BIDIRECTIONAL
319 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
320 #else
321 # define DMA_BIDIRECTIONAL 0
322 #endif
324 #ifdef SBUS_DMA_FROMDEVICE
325 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
326 #else
327 # define DMA_TODEVICE 1
328 #endif
330 #ifdef SBUS_DMA_TODEVICE
331 # define DMA_TODEVICE SBUS_DMA_TODEVICE
332 #else
333 # define DMA_FROMDEVICE 2
334 #endif
337 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
338 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
339 {
340 hme_write32(hp, tregs + TCVR_BBDATA, bit);
341 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
342 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
343 }
345 #if 0
346 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
347 {
348 u32 ret;
350 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
351 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
352 ret = hme_read32(hp, tregs + TCVR_CFG);
353 if (internal)
354 ret &= TCV_CFG_MDIO0;
355 else
356 ret &= TCV_CFG_MDIO1;
358 return ret;
359 }
360 #endif
362 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
363 {
364 u32 retval;
366 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
367 udelay(1);
368 retval = hme_read32(hp, tregs + TCVR_CFG);
369 if (internal)
370 retval &= TCV_CFG_MDIO0;
371 else
372 retval &= TCV_CFG_MDIO1;
373 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
375 return retval;
376 }
378 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
380 static int happy_meal_bb_read(struct happy_meal *hp,
381 void __iomem *tregs, int reg)
382 {
383 u32 tmp;
384 int retval = 0;
385 int i;
387 ASD(("happy_meal_bb_read: reg=%d ", reg));
389 /* Enable the MIF BitBang outputs. */
390 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
392 /* Force BitBang into the idle state. */
393 for (i = 0; i < 32; i++)
394 BB_PUT_BIT(hp, tregs, 1);
396 /* Give it the read sequence. */
397 BB_PUT_BIT(hp, tregs, 0);
398 BB_PUT_BIT(hp, tregs, 1);
399 BB_PUT_BIT(hp, tregs, 1);
400 BB_PUT_BIT(hp, tregs, 0);
402 /* Give it the PHY address. */
403 tmp = hp->paddr & 0xff;
404 for (i = 4; i >= 0; i--)
405 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
407 /* Tell it what register we want to read. */
408 tmp = (reg & 0xff);
409 for (i = 4; i >= 0; i--)
410 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
412 /* Close down the MIF BitBang outputs. */
413 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
415 /* Now read in the value. */
416 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
417 for (i = 15; i >= 0; i--)
418 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
419 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
420 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
421 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
422 ASD(("value=%x\n", retval));
423 return retval;
424 }
426 static void happy_meal_bb_write(struct happy_meal *hp,
427 void __iomem *tregs, int reg,
428 unsigned short value)
429 {
430 u32 tmp;
431 int i;
433 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
435 /* Enable the MIF BitBang outputs. */
436 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
438 /* Force BitBang into the idle state. */
439 for (i = 0; i < 32; i++)
440 BB_PUT_BIT(hp, tregs, 1);
442 /* Give it write sequence. */
443 BB_PUT_BIT(hp, tregs, 0);
444 BB_PUT_BIT(hp, tregs, 1);
445 BB_PUT_BIT(hp, tregs, 0);
446 BB_PUT_BIT(hp, tregs, 1);
448 /* Give it the PHY address. */
449 tmp = (hp->paddr & 0xff);
450 for (i = 4; i >= 0; i--)
451 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
453 /* Tell it what register we will be writing. */
454 tmp = (reg & 0xff);
455 for (i = 4; i >= 0; i--)
456 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
458 /* Tell it to become ready for the bits. */
459 BB_PUT_BIT(hp, tregs, 1);
460 BB_PUT_BIT(hp, tregs, 0);
462 for (i = 15; i >= 0; i--)
463 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
465 /* Close down the MIF BitBang outputs. */
466 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
467 }
469 #define TCVR_READ_TRIES 16
471 static int happy_meal_tcvr_read(struct happy_meal *hp,
472 void __iomem *tregs, int reg)
473 {
474 int tries = TCVR_READ_TRIES;
475 int retval;
477 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
478 if (hp->tcvr_type == none) {
479 ASD(("no transceiver, value=TCVR_FAILURE\n"));
480 return TCVR_FAILURE;
481 }
483 if (!(hp->happy_flags & HFLAG_FENABLE)) {
484 ASD(("doing bit bang\n"));
485 return happy_meal_bb_read(hp, tregs, reg);
486 }
488 hme_write32(hp, tregs + TCVR_FRAME,
489 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
490 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
491 udelay(20);
492 if (!tries) {
493 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
494 return TCVR_FAILURE;
495 }
496 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
497 ASD(("value=%04x\n", retval));
498 return retval;
499 }
501 #define TCVR_WRITE_TRIES 16
503 static void happy_meal_tcvr_write(struct happy_meal *hp,
504 void __iomem *tregs, int reg,
505 unsigned short value)
506 {
507 int tries = TCVR_WRITE_TRIES;
509 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
511 /* Welcome to Sun Microsystems, can I take your order please? */
512 if (!(hp->happy_flags & HFLAG_FENABLE)) {
513 happy_meal_bb_write(hp, tregs, reg, value);
514 return;
515 }
517 /* Would you like fries with that? */
518 hme_write32(hp, tregs + TCVR_FRAME,
519 (FRAME_WRITE | (hp->paddr << 23) |
520 ((reg & 0xff) << 18) | (value & 0xffff)));
521 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
522 udelay(20);
524 /* Anything else? */
525 if (!tries)
526 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
528 /* Fifty-two cents is your change, have a nice day. */
529 }
531 /* Auto negotiation. The scheme is very simple. We have a timer routine
532 * that keeps watching the auto negotiation process as it progresses.
533 * The DP83840 is first told to start doing it's thing, we set up the time
534 * and place the timer state machine in it's initial state.
535 *
536 * Here the timer peeks at the DP83840 status registers at each click to see
537 * if the auto negotiation has completed, we assume here that the DP83840 PHY
538 * will time out at some point and just tell us what (didn't) happen. For
539 * complete coverage we only allow so many of the ticks at this level to run,
540 * when this has expired we print a warning message and try another strategy.
541 * This "other" strategy is to force the interface into various speed/duplex
542 * configurations and we stop when we see a link-up condition before the
543 * maximum number of "peek" ticks have occurred.
544 *
545 * Once a valid link status has been detected we configure the BigMAC and
546 * the rest of the Happy Meal to speak the most efficient protocol we could
547 * get a clean link for. The priority for link configurations, highest first
548 * is:
549 * 100 Base-T Full Duplex
550 * 100 Base-T Half Duplex
551 * 10 Base-T Full Duplex
552 * 10 Base-T Half Duplex
553 *
554 * We start a new timer now, after a successful auto negotiation status has
555 * been detected. This timer just waits for the link-up bit to get set in
556 * the BMCR of the DP83840. When this occurs we print a kernel log message
557 * describing the link type in use and the fact that it is up.
558 *
559 * If a fatal error of some sort is signalled and detected in the interrupt
560 * service routine, and the chip is reset, or the link is ifconfig'd down
561 * and then back up, this entire process repeats itself all over again.
562 */
563 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
564 {
565 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
567 /* Downgrade from full to half duplex. Only possible
568 * via ethtool.
569 */
570 if (hp->sw_bmcr & BMCR_FULLDPLX) {
571 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
572 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
573 return 0;
574 }
576 /* Downgrade from 100 to 10. */
577 if (hp->sw_bmcr & BMCR_SPEED100) {
578 hp->sw_bmcr &= ~(BMCR_SPEED100);
579 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
580 return 0;
581 }
583 /* We've tried everything. */
584 return -1;
585 }
587 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
588 {
589 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
590 if (hp->tcvr_type == external)
591 printk("external ");
592 else
593 printk("internal ");
594 printk("transceiver at ");
595 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
596 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
597 if (hp->sw_lpa & LPA_100FULL)
598 printk("100Mb/s, Full Duplex.\n");
599 else
600 printk("100Mb/s, Half Duplex.\n");
601 } else {
602 if (hp->sw_lpa & LPA_10FULL)
603 printk("10Mb/s, Full Duplex.\n");
604 else
605 printk("10Mb/s, Half Duplex.\n");
606 }
607 }
609 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
610 {
611 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
612 if (hp->tcvr_type == external)
613 printk("external ");
614 else
615 printk("internal ");
616 printk("transceiver at ");
617 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
618 if (hp->sw_bmcr & BMCR_SPEED100)
619 printk("100Mb/s, ");
620 else
621 printk("10Mb/s, ");
622 if (hp->sw_bmcr & BMCR_FULLDPLX)
623 printk("Full Duplex.\n");
624 else
625 printk("Half Duplex.\n");
626 }
628 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
629 {
630 int full;
632 /* All we care about is making sure the bigmac tx_cfg has a
633 * proper duplex setting.
634 */
635 if (hp->timer_state == arbwait) {
636 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
637 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
638 goto no_response;
639 if (hp->sw_lpa & LPA_100FULL)
640 full = 1;
641 else if (hp->sw_lpa & LPA_100HALF)
642 full = 0;
643 else if (hp->sw_lpa & LPA_10FULL)
644 full = 1;
645 else
646 full = 0;
647 } else {
648 /* Forcing a link mode. */
649 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
650 if (hp->sw_bmcr & BMCR_FULLDPLX)
651 full = 1;
652 else
653 full = 0;
654 }
656 /* Before changing other bits in the tx_cfg register, and in
657 * general any of other the TX config registers too, you
658 * must:
659 * 1) Clear Enable
660 * 2) Poll with reads until that bit reads back as zero
661 * 3) Make TX configuration changes
662 * 4) Set Enable once more
663 */
664 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
665 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
666 ~(BIGMAC_TXCFG_ENABLE));
667 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
668 barrier();
669 if (full) {
670 hp->happy_flags |= HFLAG_FULL;
671 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
672 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
673 BIGMAC_TXCFG_FULLDPLX);
674 } else {
675 hp->happy_flags &= ~(HFLAG_FULL);
676 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
677 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
678 ~(BIGMAC_TXCFG_FULLDPLX));
679 }
680 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
681 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
682 BIGMAC_TXCFG_ENABLE);
683 return 0;
684 no_response:
685 return 1;
686 }
688 static int happy_meal_init(struct happy_meal *hp);
690 static int is_lucent_phy(struct happy_meal *hp)
691 {
692 void __iomem *tregs = hp->tcvregs;
693 unsigned short mr2, mr3;
694 int ret = 0;
696 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
697 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
698 if ((mr2 & 0xffff) == 0x0180 &&
699 ((mr3 & 0xffff) >> 10) == 0x1d)
700 ret = 1;
702 return ret;
703 }
705 static void happy_meal_timer(unsigned long data)
706 {
707 struct happy_meal *hp = (struct happy_meal *) data;
708 void __iomem *tregs = hp->tcvregs;
709 int restart_timer = 0;
711 spin_lock_irq(&hp->happy_lock);
713 hp->timer_ticks++;
714 switch(hp->timer_state) {
715 case arbwait:
716 /* Only allow for 5 ticks, thats 10 seconds and much too
717 * long to wait for arbitration to complete.
718 */
719 if (hp->timer_ticks >= 10) {
720 /* Enter force mode. */
721 do_force_mode:
722 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
723 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
724 hp->dev->name);
725 hp->sw_bmcr = BMCR_SPEED100;
726 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
728 if (!is_lucent_phy(hp)) {
729 /* OK, seems we need do disable the transceiver for the first
730 * tick to make sure we get an accurate link state at the
731 * second tick.
732 */
733 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
734 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
735 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
736 }
737 hp->timer_state = ltrywait;
738 hp->timer_ticks = 0;
739 restart_timer = 1;
740 } else {
741 /* Anything interesting happen? */
742 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
743 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
744 int ret;
746 /* Just what we've been waiting for... */
747 ret = set_happy_link_modes(hp, tregs);
748 if (ret) {
749 /* Ooops, something bad happened, go to force
750 * mode.
751 *
752 * XXX Broken hubs which don't support 802.3u
753 * XXX auto-negotiation make this happen as well.
754 */
755 goto do_force_mode;
756 }
758 /* Success, at least so far, advance our state engine. */
759 hp->timer_state = lupwait;
760 restart_timer = 1;
761 } else {
762 restart_timer = 1;
763 }
764 }
765 break;
767 case lupwait:
768 /* Auto negotiation was successful and we are awaiting a
769 * link up status. I have decided to let this timer run
770 * forever until some sort of error is signalled, reporting
771 * a message to the user at 10 second intervals.
772 */
773 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
774 if (hp->sw_bmsr & BMSR_LSTATUS) {
775 /* Wheee, it's up, display the link mode in use and put
776 * the timer to sleep.
777 */
778 display_link_mode(hp, tregs);
779 hp->timer_state = asleep;
780 restart_timer = 0;
781 } else {
782 if (hp->timer_ticks >= 10) {
783 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
784 "not completely up.\n", hp->dev->name);
785 hp->timer_ticks = 0;
786 restart_timer = 1;
787 } else {
788 restart_timer = 1;
789 }
790 }
791 break;
793 case ltrywait:
794 /* Making the timeout here too long can make it take
795 * annoyingly long to attempt all of the link mode
796 * permutations, but then again this is essentially
797 * error recovery code for the most part.
798 */
799 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
800 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
801 if (hp->timer_ticks == 1) {
802 if (!is_lucent_phy(hp)) {
803 /* Re-enable transceiver, we'll re-enable the transceiver next
804 * tick, then check link state on the following tick.
805 */
806 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
807 happy_meal_tcvr_write(hp, tregs,
808 DP83840_CSCONFIG, hp->sw_csconfig);
809 }
810 restart_timer = 1;
811 break;
812 }
813 if (hp->timer_ticks == 2) {
814 if (!is_lucent_phy(hp)) {
815 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
816 happy_meal_tcvr_write(hp, tregs,
817 DP83840_CSCONFIG, hp->sw_csconfig);
818 }
819 restart_timer = 1;
820 break;
821 }
822 if (hp->sw_bmsr & BMSR_LSTATUS) {
823 /* Force mode selection success. */
824 display_forced_link_mode(hp, tregs);
825 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
826 hp->timer_state = asleep;
827 restart_timer = 0;
828 } else {
829 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
830 int ret;
832 ret = try_next_permutation(hp, tregs);
833 if (ret == -1) {
834 /* Aieee, tried them all, reset the
835 * chip and try all over again.
836 */
838 /* Let the user know... */
839 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
840 hp->dev->name);
842 ret = happy_meal_init(hp);
843 if (ret) {
844 /* ho hum... */
845 printk(KERN_ERR "%s: Error, cannot re-init the "
846 "Happy Meal.\n", hp->dev->name);
847 }
848 goto out;
849 }
850 if (!is_lucent_phy(hp)) {
851 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
852 DP83840_CSCONFIG);
853 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
854 happy_meal_tcvr_write(hp, tregs,
855 DP83840_CSCONFIG, hp->sw_csconfig);
856 }
857 hp->timer_ticks = 0;
858 restart_timer = 1;
859 } else {
860 restart_timer = 1;
861 }
862 }
863 break;
865 case asleep:
866 default:
867 /* Can't happens.... */
868 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
869 hp->dev->name);
870 restart_timer = 0;
871 hp->timer_ticks = 0;
872 hp->timer_state = asleep; /* foo on you */
873 break;
874 };
876 if (restart_timer) {
877 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
878 add_timer(&hp->happy_timer);
879 }
881 out:
882 spin_unlock_irq(&hp->happy_lock);
883 }
885 #define TX_RESET_TRIES 32
886 #define RX_RESET_TRIES 32
888 /* hp->happy_lock must be held */
889 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
890 {
891 int tries = TX_RESET_TRIES;
893 HMD(("happy_meal_tx_reset: reset, "));
895 /* Would you like to try our SMCC Delux? */
896 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
897 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
898 udelay(20);
900 /* Lettuce, tomato, buggy hardware (no extra charge)? */
901 if (!tries)
902 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
904 /* Take care. */
905 HMD(("done\n"));
906 }
908 /* hp->happy_lock must be held */
909 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
910 {
911 int tries = RX_RESET_TRIES;
913 HMD(("happy_meal_rx_reset: reset, "));
915 /* We have a special on GNU/Viking hardware bugs today. */
916 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
917 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
918 udelay(20);
920 /* Will that be all? */
921 if (!tries)
922 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
924 /* Don't forget your vik_1137125_wa. Have a nice day. */
925 HMD(("done\n"));
926 }
928 #define STOP_TRIES 16
930 /* hp->happy_lock must be held */
931 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
932 {
933 int tries = STOP_TRIES;
935 HMD(("happy_meal_stop: reset, "));
937 /* We're consolidating our STB products, it's your lucky day. */
938 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
939 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
940 udelay(20);
942 /* Come back next week when we are "Sun Microelectronics". */
943 if (!tries)
944 printk(KERN_ERR "happy meal: Fry guys.");
946 /* Remember: "Different name, same old buggy as shit hardware." */
947 HMD(("done\n"));
948 }
950 /* hp->happy_lock must be held */
951 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
952 {
953 struct net_device_stats *stats = &hp->net_stats;
955 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
956 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
958 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
959 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
961 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
962 hme_write32(hp, bregs + BMAC_GLECTR, 0);
964 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
966 stats->collisions +=
967 (hme_read32(hp, bregs + BMAC_EXCTR) +
968 hme_read32(hp, bregs + BMAC_LTCTR));
969 hme_write32(hp, bregs + BMAC_EXCTR, 0);
970 hme_write32(hp, bregs + BMAC_LTCTR, 0);
971 }
973 /* hp->happy_lock must be held */
974 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
975 {
976 ASD(("happy_meal_poll_stop: "));
978 /* If polling disabled or not polling already, nothing to do. */
979 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
980 (HFLAG_POLLENABLE | HFLAG_POLL)) {
981 HMD(("not polling, return\n"));
982 return;
983 }
985 /* Shut up the MIF. */
986 ASD(("were polling, mif ints off, "));
987 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
989 /* Turn off polling. */
990 ASD(("polling off, "));
991 hme_write32(hp, tregs + TCVR_CFG,
992 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
994 /* We are no longer polling. */
995 hp->happy_flags &= ~(HFLAG_POLL);
997 /* Let the bits set. */
998 udelay(200);
999 ASD(("done\n"));
1002 /* Only Sun can take such nice parts and fuck up the programming interface
1003 * like this. Good job guys...
1004 */
1005 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1006 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1008 /* hp->happy_lock must be held */
1009 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1011 u32 tconfig;
1012 int result, tries = TCVR_RESET_TRIES;
1014 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1015 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1016 if (hp->tcvr_type == external) {
1017 ASD(("external<"));
1018 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1019 hp->tcvr_type = internal;
1020 hp->paddr = TCV_PADDR_ITX;
1021 ASD(("ISOLATE,"));
1022 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1023 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1024 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1025 if (result == TCVR_FAILURE) {
1026 ASD(("phyread_fail>\n"));
1027 return -1;
1029 ASD(("phyread_ok,PSELECT>"));
1030 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1031 hp->tcvr_type = external;
1032 hp->paddr = TCV_PADDR_ETX;
1033 } else {
1034 if (tconfig & TCV_CFG_MDIO1) {
1035 ASD(("internal<PSELECT,"));
1036 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1037 ASD(("ISOLATE,"));
1038 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1039 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1040 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1041 if (result == TCVR_FAILURE) {
1042 ASD(("phyread_fail>\n"));
1043 return -1;
1045 ASD(("phyread_ok,~PSELECT>"));
1046 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1047 hp->tcvr_type = internal;
1048 hp->paddr = TCV_PADDR_ITX;
1052 ASD(("BMCR_RESET "));
1053 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1055 while (--tries) {
1056 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1057 if (result == TCVR_FAILURE)
1058 return -1;
1059 hp->sw_bmcr = result;
1060 if (!(result & BMCR_RESET))
1061 break;
1062 udelay(20);
1064 if (!tries) {
1065 ASD(("BMCR RESET FAILED!\n"));
1066 return -1;
1068 ASD(("RESET_OK\n"));
1070 /* Get fresh copies of the PHY registers. */
1071 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1072 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1073 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1074 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1076 ASD(("UNISOLATE"));
1077 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1078 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1080 tries = TCVR_UNISOLATE_TRIES;
1081 while (--tries) {
1082 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1083 if (result == TCVR_FAILURE)
1084 return -1;
1085 if (!(result & BMCR_ISOLATE))
1086 break;
1087 udelay(20);
1089 if (!tries) {
1090 ASD((" FAILED!\n"));
1091 return -1;
1093 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1094 if (!is_lucent_phy(hp)) {
1095 result = happy_meal_tcvr_read(hp, tregs,
1096 DP83840_CSCONFIG);
1097 happy_meal_tcvr_write(hp, tregs,
1098 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1100 return 0;
1103 /* Figure out whether we have an internal or external transceiver.
1105 * hp->happy_lock must be held
1106 */
1107 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1109 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1111 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1112 if (hp->happy_flags & HFLAG_POLL) {
1113 /* If we are polling, we must stop to get the transceiver type. */
1114 ASD(("<polling> "));
1115 if (hp->tcvr_type == internal) {
1116 if (tconfig & TCV_CFG_MDIO1) {
1117 ASD(("<internal> <poll stop> "));
1118 happy_meal_poll_stop(hp, tregs);
1119 hp->paddr = TCV_PADDR_ETX;
1120 hp->tcvr_type = external;
1121 ASD(("<external>\n"));
1122 tconfig &= ~(TCV_CFG_PENABLE);
1123 tconfig |= TCV_CFG_PSELECT;
1124 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1126 } else {
1127 if (hp->tcvr_type == external) {
1128 ASD(("<external> "));
1129 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1130 ASD(("<poll stop> "));
1131 happy_meal_poll_stop(hp, tregs);
1132 hp->paddr = TCV_PADDR_ITX;
1133 hp->tcvr_type = internal;
1134 ASD(("<internal>\n"));
1135 hme_write32(hp, tregs + TCVR_CFG,
1136 hme_read32(hp, tregs + TCVR_CFG) &
1137 ~(TCV_CFG_PSELECT));
1139 ASD(("\n"));
1140 } else {
1141 ASD(("<none>\n"));
1144 } else {
1145 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1147 /* Else we can just work off of the MDIO bits. */
1148 ASD(("<not polling> "));
1149 if (reread & TCV_CFG_MDIO1) {
1150 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1151 hp->paddr = TCV_PADDR_ETX;
1152 hp->tcvr_type = external;
1153 ASD(("<external>\n"));
1154 } else {
1155 if (reread & TCV_CFG_MDIO0) {
1156 hme_write32(hp, tregs + TCVR_CFG,
1157 tconfig & ~(TCV_CFG_PSELECT));
1158 hp->paddr = TCV_PADDR_ITX;
1159 hp->tcvr_type = internal;
1160 ASD(("<internal>\n"));
1161 } else {
1162 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1163 hp->tcvr_type = none; /* Grrr... */
1164 ASD(("<none>\n"));
1170 /* The receive ring buffers are a bit tricky to get right. Here goes...
1172 * The buffers we dma into must be 64 byte aligned. So we use a special
1173 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1174 * we really need.
1176 * We use skb_reserve() to align the data block we get in the skb. We
1177 * also program the etxregs->cfg register to use an offset of 2. This
1178 * imperical constant plus the ethernet header size will always leave
1179 * us with a nicely aligned ip header once we pass things up to the
1180 * protocol layers.
1182 * The numbers work out to:
1184 * Max ethernet frame size 1518
1185 * Ethernet header size 14
1186 * Happy Meal base offset 2
1188 * Say a skb data area is at 0xf001b010, and its size alloced is
1189 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1191 * First our alloc_skb() routine aligns the data base to a 64 byte
1192 * boundary. We now have 0xf001b040 as our skb data address. We
1193 * plug this into the receive descriptor address.
1195 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1196 * So now the data we will end up looking at starts at 0xf001b042. When
1197 * the packet arrives, we will check out the size received and subtract
1198 * this from the skb->length. Then we just pass the packet up to the
1199 * protocols as is, and allocate a new skb to replace this slot we have
1200 * just received from.
1202 * The ethernet layer will strip the ether header from the front of the
1203 * skb we just sent to it, this leaves us with the ip header sitting
1204 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1205 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1206 * bit checksum is obtained from the low bits of the receive descriptor
1207 * flags, thus:
1209 * skb->csum = rxd->rx_flags & 0xffff;
1210 * skb->ip_summed = CHECKSUM_HW;
1212 * before sending off the skb to the protocols, and we are good as gold.
1213 */
1214 static void happy_meal_clean_rings(struct happy_meal *hp)
1216 int i;
1218 for (i = 0; i < RX_RING_SIZE; i++) {
1219 if (hp->rx_skbs[i] != NULL) {
1220 struct sk_buff *skb = hp->rx_skbs[i];
1221 struct happy_meal_rxd *rxd;
1222 u32 dma_addr;
1224 rxd = &hp->happy_block->happy_meal_rxd[i];
1225 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1226 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1227 dev_kfree_skb_any(skb);
1228 hp->rx_skbs[i] = NULL;
1232 for (i = 0; i < TX_RING_SIZE; i++) {
1233 if (hp->tx_skbs[i] != NULL) {
1234 struct sk_buff *skb = hp->tx_skbs[i];
1235 struct happy_meal_txd *txd;
1236 u32 dma_addr;
1237 int frag;
1239 hp->tx_skbs[i] = NULL;
1241 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1242 txd = &hp->happy_block->happy_meal_txd[i];
1243 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1244 hme_dma_unmap(hp, dma_addr,
1245 (hme_read_desc32(hp, &txd->tx_flags)
1246 & TXFLAG_SIZE),
1247 DMA_TODEVICE);
1249 if (frag != skb_shinfo(skb)->nr_frags)
1250 i++;
1253 dev_kfree_skb_any(skb);
1258 /* hp->happy_lock must be held */
1259 static void happy_meal_init_rings(struct happy_meal *hp)
1261 struct hmeal_init_block *hb = hp->happy_block;
1262 struct net_device *dev = hp->dev;
1263 int i;
1265 HMD(("happy_meal_init_rings: counters to zero, "));
1266 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1268 /* Free any skippy bufs left around in the rings. */
1269 HMD(("clean, "));
1270 happy_meal_clean_rings(hp);
1272 /* Now get new skippy bufs for the receive ring. */
1273 HMD(("init rxring, "));
1274 for (i = 0; i < RX_RING_SIZE; i++) {
1275 struct sk_buff *skb;
1277 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1278 if (!skb) {
1279 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1280 continue;
1282 hp->rx_skbs[i] = skb;
1283 skb->dev = dev;
1285 /* Because we reserve afterwards. */
1286 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1287 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1288 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1289 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1290 skb_reserve(skb, RX_OFFSET);
1293 HMD(("init txring, "));
1294 for (i = 0; i < TX_RING_SIZE; i++)
1295 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1297 HMD(("done\n"));
1300 /* hp->happy_lock must be held */
1301 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1302 void __iomem *tregs,
1303 struct ethtool_cmd *ep)
1305 int timeout;
1307 /* Read all of the registers we are interested in now. */
1308 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1309 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1310 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1311 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1313 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1315 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1316 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1317 /* Advertise everything we can support. */
1318 if (hp->sw_bmsr & BMSR_10HALF)
1319 hp->sw_advertise |= (ADVERTISE_10HALF);
1320 else
1321 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1323 if (hp->sw_bmsr & BMSR_10FULL)
1324 hp->sw_advertise |= (ADVERTISE_10FULL);
1325 else
1326 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1327 if (hp->sw_bmsr & BMSR_100HALF)
1328 hp->sw_advertise |= (ADVERTISE_100HALF);
1329 else
1330 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1331 if (hp->sw_bmsr & BMSR_100FULL)
1332 hp->sw_advertise |= (ADVERTISE_100FULL);
1333 else
1334 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1335 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1337 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1338 * XXX and this is because the DP83840 does not support it, changes
1339 * XXX would need to be made to the tx/rx logic in the driver as well
1340 * XXX so I completely skip checking for it in the BMSR for now.
1341 */
1343 #ifdef AUTO_SWITCH_DEBUG
1344 ASD(("%s: Advertising [ ", hp->dev->name));
1345 if (hp->sw_advertise & ADVERTISE_10HALF)
1346 ASD(("10H "));
1347 if (hp->sw_advertise & ADVERTISE_10FULL)
1348 ASD(("10F "));
1349 if (hp->sw_advertise & ADVERTISE_100HALF)
1350 ASD(("100H "));
1351 if (hp->sw_advertise & ADVERTISE_100FULL)
1352 ASD(("100F "));
1353 #endif
1355 /* Enable Auto-Negotiation, this is usually on already... */
1356 hp->sw_bmcr |= BMCR_ANENABLE;
1357 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1359 /* Restart it to make sure it is going. */
1360 hp->sw_bmcr |= BMCR_ANRESTART;
1361 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1363 /* BMCR_ANRESTART self clears when the process has begun. */
1365 timeout = 64; /* More than enough. */
1366 while (--timeout) {
1367 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1368 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1369 break; /* got it. */
1370 udelay(10);
1372 if (!timeout) {
1373 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1374 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1375 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1376 hp->dev->name);
1377 goto force_link;
1378 } else {
1379 hp->timer_state = arbwait;
1381 } else {
1382 force_link:
1383 /* Force the link up, trying first a particular mode.
1384 * Either we are here at the request of ethtool or
1385 * because the Happy Meal would not start to autoneg.
1386 */
1388 /* Disable auto-negotiation in BMCR, enable the duplex and
1389 * speed setting, init the timer state machine, and fire it off.
1390 */
1391 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1392 hp->sw_bmcr = BMCR_SPEED100;
1393 } else {
1394 if (ep->speed == SPEED_100)
1395 hp->sw_bmcr = BMCR_SPEED100;
1396 else
1397 hp->sw_bmcr = 0;
1398 if (ep->duplex == DUPLEX_FULL)
1399 hp->sw_bmcr |= BMCR_FULLDPLX;
1401 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1403 if (!is_lucent_phy(hp)) {
1404 /* OK, seems we need do disable the transceiver for the first
1405 * tick to make sure we get an accurate link state at the
1406 * second tick.
1407 */
1408 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1409 DP83840_CSCONFIG);
1410 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1411 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1412 hp->sw_csconfig);
1414 hp->timer_state = ltrywait;
1417 hp->timer_ticks = 0;
1418 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1419 hp->happy_timer.data = (unsigned long) hp;
1420 hp->happy_timer.function = &happy_meal_timer;
1421 add_timer(&hp->happy_timer);
1424 /* hp->happy_lock must be held */
1425 static int happy_meal_init(struct happy_meal *hp)
1427 void __iomem *gregs = hp->gregs;
1428 void __iomem *etxregs = hp->etxregs;
1429 void __iomem *erxregs = hp->erxregs;
1430 void __iomem *bregs = hp->bigmacregs;
1431 void __iomem *tregs = hp->tcvregs;
1432 u32 regtmp, rxcfg;
1433 unsigned char *e = &hp->dev->dev_addr[0];
1435 /* If auto-negotiation timer is running, kill it. */
1436 del_timer(&hp->happy_timer);
1438 HMD(("happy_meal_init: happy_flags[%08x] ",
1439 hp->happy_flags));
1440 if (!(hp->happy_flags & HFLAG_INIT)) {
1441 HMD(("set HFLAG_INIT, "));
1442 hp->happy_flags |= HFLAG_INIT;
1443 happy_meal_get_counters(hp, bregs);
1446 /* Stop polling. */
1447 HMD(("to happy_meal_poll_stop\n"));
1448 happy_meal_poll_stop(hp, tregs);
1450 /* Stop transmitter and receiver. */
1451 HMD(("happy_meal_init: to happy_meal_stop\n"));
1452 happy_meal_stop(hp, gregs);
1454 /* Alloc and reset the tx/rx descriptor chains. */
1455 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1456 happy_meal_init_rings(hp);
1458 /* Shut up the MIF. */
1459 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1460 hme_read32(hp, tregs + TCVR_IMASK)));
1461 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1463 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1464 if (hp->happy_flags & HFLAG_FENABLE) {
1465 HMD(("use frame old[%08x], ",
1466 hme_read32(hp, tregs + TCVR_CFG)));
1467 hme_write32(hp, tregs + TCVR_CFG,
1468 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1469 } else {
1470 HMD(("use bitbang old[%08x], ",
1471 hme_read32(hp, tregs + TCVR_CFG)));
1472 hme_write32(hp, tregs + TCVR_CFG,
1473 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1476 /* Check the state of the transceiver. */
1477 HMD(("to happy_meal_transceiver_check\n"));
1478 happy_meal_transceiver_check(hp, tregs);
1480 /* Put the Big Mac into a sane state. */
1481 HMD(("happy_meal_init: "));
1482 switch(hp->tcvr_type) {
1483 case none:
1484 /* Cannot operate if we don't know the transceiver type! */
1485 HMD(("AAIEEE no transceiver type, EAGAIN"));
1486 return -EAGAIN;
1488 case internal:
1489 /* Using the MII buffers. */
1490 HMD(("internal, using MII, "));
1491 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1492 break;
1494 case external:
1495 /* Not using the MII, disable it. */
1496 HMD(("external, disable MII, "));
1497 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1498 break;
1499 };
1501 if (happy_meal_tcvr_reset(hp, tregs))
1502 return -EAGAIN;
1504 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1505 HMD(("tx/rx reset, "));
1506 happy_meal_tx_reset(hp, bregs);
1507 happy_meal_rx_reset(hp, bregs);
1509 /* Set jam size and inter-packet gaps to reasonable defaults. */
1510 HMD(("jsize/ipg1/ipg2, "));
1511 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1512 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1513 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1515 /* Load up the MAC address and random seed. */
1516 HMD(("rseed/macaddr, "));
1518 /* The docs recommend to use the 10LSB of our MAC here. */
1519 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1521 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1522 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1523 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1525 HMD(("htable, "));
1526 if ((hp->dev->flags & IFF_ALLMULTI) ||
1527 (hp->dev->mc_count > 64)) {
1528 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1529 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1530 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1531 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1532 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1533 u16 hash_table[4];
1534 struct dev_mc_list *dmi = hp->dev->mc_list;
1535 char *addrs;
1536 int i;
1537 u32 crc;
1539 for (i = 0; i < 4; i++)
1540 hash_table[i] = 0;
1542 for (i = 0; i < hp->dev->mc_count; i++) {
1543 addrs = dmi->dmi_addr;
1544 dmi = dmi->next;
1546 if (!(*addrs & 1))
1547 continue;
1549 crc = ether_crc_le(6, addrs);
1550 crc >>= 26;
1551 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1553 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1554 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1555 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1556 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1557 } else {
1558 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1559 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1560 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1561 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1564 /* Set the RX and TX ring ptrs. */
1565 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1566 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1568 hme_write32(hp, erxregs + ERX_RING,
1569 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1570 hme_write32(hp, etxregs + ETX_RING,
1571 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1573 /* Parity issues in the ERX unit of some HME revisions can cause some
1574 * registers to not be written unless their parity is even. Detect such
1575 * lost writes and simply rewrite with a low bit set (which will be ignored
1576 * since the rxring needs to be 2K aligned).
1577 */
1578 if (hme_read32(hp, erxregs + ERX_RING) !=
1579 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1580 hme_write32(hp, erxregs + ERX_RING,
1581 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1582 | 0x4);
1584 /* Set the supported burst sizes. */
1585 HMD(("happy_meal_init: old[%08x] bursts<",
1586 hme_read32(hp, gregs + GREG_CFG)));
1588 #ifndef CONFIG_SPARC
1589 /* It is always PCI and can handle 64byte bursts. */
1590 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1591 #else
1592 if ((hp->happy_bursts & DMA_BURST64) &&
1593 ((hp->happy_flags & HFLAG_PCI) != 0
1594 #ifdef CONFIG_SBUS
1595 || sbus_can_burst64(hp->happy_dev)
1596 #endif
1597 || 0)) {
1598 u32 gcfg = GREG_CFG_BURST64;
1600 /* I have no idea if I should set the extended
1601 * transfer mode bit for Cheerio, so for now I
1602 * do not. -DaveM
1603 */
1604 #ifdef CONFIG_SBUS
1605 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1606 sbus_can_dma_64bit(hp->happy_dev)) {
1607 sbus_set_sbus64(hp->happy_dev,
1608 hp->happy_bursts);
1609 gcfg |= GREG_CFG_64BIT;
1611 #endif
1613 HMD(("64>"));
1614 hme_write32(hp, gregs + GREG_CFG, gcfg);
1615 } else if (hp->happy_bursts & DMA_BURST32) {
1616 HMD(("32>"));
1617 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1618 } else if (hp->happy_bursts & DMA_BURST16) {
1619 HMD(("16>"));
1620 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1621 } else {
1622 HMD(("XXX>"));
1623 hme_write32(hp, gregs + GREG_CFG, 0);
1625 #endif /* CONFIG_SPARC */
1627 /* Turn off interrupts we do not want to hear. */
1628 HMD((", enable global interrupts, "));
1629 hme_write32(hp, gregs + GREG_IMASK,
1630 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1631 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1633 /* Set the transmit ring buffer size. */
1634 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1635 hme_read32(hp, etxregs + ETX_RSIZE)));
1636 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1638 /* Enable transmitter DVMA. */
1639 HMD(("tx dma enable old[%08x], ",
1640 hme_read32(hp, etxregs + ETX_CFG)));
1641 hme_write32(hp, etxregs + ETX_CFG,
1642 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1644 /* This chip really rots, for the receiver sometimes when you
1645 * write to its control registers not all the bits get there
1646 * properly. I cannot think of a sane way to provide complete
1647 * coverage for this hardware bug yet.
1648 */
1649 HMD(("erx regs bug old[%08x]\n",
1650 hme_read32(hp, erxregs + ERX_CFG)));
1651 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1652 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1653 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1654 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1655 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1656 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1657 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1658 /* XXX Should return failure here... */
1661 /* Enable Big Mac hash table filter. */
1662 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1663 hme_read32(hp, bregs + BMAC_RXCFG)));
1664 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1665 if (hp->dev->flags & IFF_PROMISC)
1666 rxcfg |= BIGMAC_RXCFG_PMISC;
1667 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1669 /* Let the bits settle in the chip. */
1670 udelay(10);
1672 /* Ok, configure the Big Mac transmitter. */
1673 HMD(("BIGMAC init, "));
1674 regtmp = 0;
1675 if (hp->happy_flags & HFLAG_FULL)
1676 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1678 /* Don't turn on the "don't give up" bit for now. It could cause hme
1679 * to deadlock with the PHY if a Jabber occurs.
1680 */
1681 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1683 /* Give up after 16 TX attempts. */
1684 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1686 /* Enable the output drivers no matter what. */
1687 regtmp = BIGMAC_XCFG_ODENABLE;
1689 /* If card can do lance mode, enable it. */
1690 if (hp->happy_flags & HFLAG_LANCE)
1691 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1693 /* Disable the MII buffers if using external transceiver. */
1694 if (hp->tcvr_type == external)
1695 regtmp |= BIGMAC_XCFG_MIIDISAB;
1697 HMD(("XIF config old[%08x], ",
1698 hme_read32(hp, bregs + BMAC_XIFCFG)));
1699 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1701 /* Start things up. */
1702 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1703 hme_read32(hp, bregs + BMAC_TXCFG),
1704 hme_read32(hp, bregs + BMAC_RXCFG)));
1705 hme_write32(hp, bregs + BMAC_TXCFG,
1706 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1707 hme_write32(hp, bregs + BMAC_RXCFG,
1708 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1710 /* Get the autonegotiation started, and the watch timer ticking. */
1711 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1713 /* Success. */
1714 return 0;
1717 /* hp->happy_lock must be held */
1718 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1720 void __iomem *tregs = hp->tcvregs;
1721 void __iomem *bregs = hp->bigmacregs;
1722 void __iomem *gregs = hp->gregs;
1724 happy_meal_stop(hp, gregs);
1725 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1726 if (hp->happy_flags & HFLAG_FENABLE)
1727 hme_write32(hp, tregs + TCVR_CFG,
1728 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1729 else
1730 hme_write32(hp, tregs + TCVR_CFG,
1731 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1732 happy_meal_transceiver_check(hp, tregs);
1733 switch(hp->tcvr_type) {
1734 case none:
1735 return;
1736 case internal:
1737 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1738 break;
1739 case external:
1740 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1741 break;
1742 };
1743 if (happy_meal_tcvr_reset(hp, tregs))
1744 return;
1746 /* Latch PHY registers as of now. */
1747 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1748 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1750 /* Advertise everything we can support. */
1751 if (hp->sw_bmsr & BMSR_10HALF)
1752 hp->sw_advertise |= (ADVERTISE_10HALF);
1753 else
1754 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1756 if (hp->sw_bmsr & BMSR_10FULL)
1757 hp->sw_advertise |= (ADVERTISE_10FULL);
1758 else
1759 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1760 if (hp->sw_bmsr & BMSR_100HALF)
1761 hp->sw_advertise |= (ADVERTISE_100HALF);
1762 else
1763 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1764 if (hp->sw_bmsr & BMSR_100FULL)
1765 hp->sw_advertise |= (ADVERTISE_100FULL);
1766 else
1767 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1769 /* Update the PHY advertisement register. */
1770 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1773 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1774 * the hardware, so we cannot re-read it and get a correct value.
1776 * hp->happy_lock must be held
1777 */
1778 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1780 int reset = 0;
1782 /* Only print messages for non-counter related interrupts. */
1783 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1784 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1785 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1786 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1787 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1788 GREG_STAT_SLVPERR))
1789 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1790 hp->dev->name, status);
1792 if (status & GREG_STAT_RFIFOVF) {
1793 /* Receive FIFO overflow is harmless and the hardware will take
1794 care of it, just some packets are lost. Who cares. */
1795 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1798 if (status & GREG_STAT_STSTERR) {
1799 /* BigMAC SQE link test failed. */
1800 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1801 reset = 1;
1804 if (status & GREG_STAT_TFIFO_UND) {
1805 /* Transmit FIFO underrun, again DMA error likely. */
1806 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1807 hp->dev->name);
1808 reset = 1;
1811 if (status & GREG_STAT_MAXPKTERR) {
1812 /* Driver error, tried to transmit something larger
1813 * than ethernet max mtu.
1814 */
1815 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1816 reset = 1;
1819 if (status & GREG_STAT_NORXD) {
1820 /* This is harmless, it just means the system is
1821 * quite loaded and the incoming packet rate was
1822 * faster than the interrupt handler could keep up
1823 * with.
1824 */
1825 printk(KERN_INFO "%s: Happy Meal out of receive "
1826 "descriptors, packet dropped.\n",
1827 hp->dev->name);
1830 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1831 /* All sorts of DMA receive errors. */
1832 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1833 if (status & GREG_STAT_RXERR)
1834 printk("GenericError ");
1835 if (status & GREG_STAT_RXPERR)
1836 printk("ParityError ");
1837 if (status & GREG_STAT_RXTERR)
1838 printk("RxTagBotch ");
1839 printk("]\n");
1840 reset = 1;
1843 if (status & GREG_STAT_EOPERR) {
1844 /* Driver bug, didn't set EOP bit in tx descriptor given
1845 * to the happy meal.
1846 */
1847 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1848 hp->dev->name);
1849 reset = 1;
1852 if (status & GREG_STAT_MIFIRQ) {
1853 /* MIF signalled an interrupt, were we polling it? */
1854 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1857 if (status &
1858 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1859 /* All sorts of transmit DMA errors. */
1860 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1861 if (status & GREG_STAT_TXEACK)
1862 printk("GenericError ");
1863 if (status & GREG_STAT_TXLERR)
1864 printk("LateError ");
1865 if (status & GREG_STAT_TXPERR)
1866 printk("ParityErro ");
1867 if (status & GREG_STAT_TXTERR)
1868 printk("TagBotch ");
1869 printk("]\n");
1870 reset = 1;
1873 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1874 /* Bus or parity error when cpu accessed happy meal registers
1875 * or it's internal FIFO's. Should never see this.
1876 */
1877 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1878 hp->dev->name,
1879 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1880 reset = 1;
1883 if (reset) {
1884 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1885 happy_meal_init(hp);
1886 return 1;
1888 return 0;
1891 /* hp->happy_lock must be held */
1892 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1894 void __iomem *tregs = hp->tcvregs;
1896 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1897 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1898 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1900 /* Use the fastest transmission protocol possible. */
1901 if (hp->sw_lpa & LPA_100FULL) {
1902 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1903 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1904 } else if (hp->sw_lpa & LPA_100HALF) {
1905 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1906 hp->sw_bmcr |= BMCR_SPEED100;
1907 } else if (hp->sw_lpa & LPA_10FULL) {
1908 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1909 hp->sw_bmcr |= BMCR_FULLDPLX;
1910 } else {
1911 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1913 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1915 /* Finally stop polling and shut up the MIF. */
1916 happy_meal_poll_stop(hp, tregs);
1919 #ifdef TXDEBUG
1920 #define TXD(x) printk x
1921 #else
1922 #define TXD(x)
1923 #endif
1925 /* hp->happy_lock must be held */
1926 static void happy_meal_tx(struct happy_meal *hp)
1928 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1929 struct happy_meal_txd *this;
1930 struct net_device *dev = hp->dev;
1931 int elem;
1933 elem = hp->tx_old;
1934 TXD(("TX<"));
1935 while (elem != hp->tx_new) {
1936 struct sk_buff *skb;
1937 u32 flags, dma_addr, dma_len;
1938 int frag;
1940 TXD(("[%d]", elem));
1941 this = &txbase[elem];
1942 flags = hme_read_desc32(hp, &this->tx_flags);
1943 if (flags & TXFLAG_OWN)
1944 break;
1945 skb = hp->tx_skbs[elem];
1946 if (skb_shinfo(skb)->nr_frags) {
1947 int last;
1949 last = elem + skb_shinfo(skb)->nr_frags;
1950 last &= (TX_RING_SIZE - 1);
1951 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1952 if (flags & TXFLAG_OWN)
1953 break;
1955 hp->tx_skbs[elem] = NULL;
1956 hp->net_stats.tx_bytes += skb->len;
1958 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1959 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1960 dma_len = hme_read_desc32(hp, &this->tx_flags);
1962 dma_len &= TXFLAG_SIZE;
1963 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1965 elem = NEXT_TX(elem);
1966 this = &txbase[elem];
1969 dev_kfree_skb_irq(skb);
1970 hp->net_stats.tx_packets++;
1972 hp->tx_old = elem;
1973 TXD((">"));
1975 if (netif_queue_stopped(dev) &&
1976 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1977 netif_wake_queue(dev);
1980 #ifdef RXDEBUG
1981 #define RXD(x) printk x
1982 #else
1983 #define RXD(x)
1984 #endif
1986 /* Originally I used to handle the allocation failure by just giving back just
1987 * that one ring buffer to the happy meal. Problem is that usually when that
1988 * condition is triggered, the happy meal expects you to do something reasonable
1989 * with all of the packets it has DMA'd in. So now I just drop the entire
1990 * ring when we cannot get a new skb and give them all back to the happy meal,
1991 * maybe things will be "happier" now.
1993 * hp->happy_lock must be held
1994 */
1995 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1997 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1998 struct happy_meal_rxd *this;
1999 int elem = hp->rx_new, drops = 0;
2000 u32 flags;
2002 RXD(("RX<"));
2003 this = &rxbase[elem];
2004 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2005 struct sk_buff *skb;
2006 int len = flags >> 16;
2007 u16 csum = flags & RXFLAG_CSUM;
2008 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2010 RXD(("[%d ", elem));
2012 /* Check for errors. */
2013 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2014 RXD(("ERR(%08x)]", flags));
2015 hp->net_stats.rx_errors++;
2016 if (len < ETH_ZLEN)
2017 hp->net_stats.rx_length_errors++;
2018 if (len & (RXFLAG_OVERFLOW >> 16)) {
2019 hp->net_stats.rx_over_errors++;
2020 hp->net_stats.rx_fifo_errors++;
2023 /* Return it to the Happy meal. */
2024 drop_it:
2025 hp->net_stats.rx_dropped++;
2026 hme_write_rxd(hp, this,
2027 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2028 dma_addr);
2029 goto next;
2031 skb = hp->rx_skbs[elem];
2032 if (len > RX_COPY_THRESHOLD) {
2033 struct sk_buff *new_skb;
2035 /* Now refill the entry, if we can. */
2036 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2037 if (new_skb == NULL) {
2038 drops++;
2039 goto drop_it;
2041 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2042 hp->rx_skbs[elem] = new_skb;
2043 new_skb->dev = dev;
2044 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2045 hme_write_rxd(hp, this,
2046 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2047 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2048 skb_reserve(new_skb, RX_OFFSET);
2050 /* Trim the original skb for the netif. */
2051 skb_trim(skb, len);
2052 } else {
2053 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2055 if (copy_skb == NULL) {
2056 drops++;
2057 goto drop_it;
2060 copy_skb->dev = dev;
2061 skb_reserve(copy_skb, 2);
2062 skb_put(copy_skb, len);
2063 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
2064 memcpy(copy_skb->data, skb->data, len);
2065 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2067 /* Reuse original ring buffer. */
2068 hme_write_rxd(hp, this,
2069 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2070 dma_addr);
2072 skb = copy_skb;
2075 /* This card is _fucking_ hot... */
2076 skb->csum = ntohs(csum ^ 0xffff);
2077 skb->ip_summed = CHECKSUM_HW;
2079 RXD(("len=%d csum=%4x]", len, csum));
2080 skb->protocol = eth_type_trans(skb, dev);
2081 netif_rx(skb);
2083 dev->last_rx = jiffies;
2084 hp->net_stats.rx_packets++;
2085 hp->net_stats.rx_bytes += len;
2086 next:
2087 elem = NEXT_RX(elem);
2088 this = &rxbase[elem];
2090 hp->rx_new = elem;
2091 if (drops)
2092 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2093 RXD((">"));
2096 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2098 struct net_device *dev = (struct net_device *) dev_id;
2099 struct happy_meal *hp = dev->priv;
2100 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2102 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2104 spin_lock(&hp->happy_lock);
2106 if (happy_status & GREG_STAT_ERRORS) {
2107 HMD(("ERRORS "));
2108 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2109 goto out;
2112 if (happy_status & GREG_STAT_MIFIRQ) {
2113 HMD(("MIFIRQ "));
2114 happy_meal_mif_interrupt(hp);
2117 if (happy_status & GREG_STAT_TXALL) {
2118 HMD(("TXALL "));
2119 happy_meal_tx(hp);
2122 if (happy_status & GREG_STAT_RXTOHOST) {
2123 HMD(("RXTOHOST "));
2124 happy_meal_rx(hp, dev);
2127 HMD(("done\n"));
2128 out:
2129 spin_unlock(&hp->happy_lock);
2131 return IRQ_HANDLED;
2134 #ifdef CONFIG_SBUS
2135 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2137 struct quattro *qp = (struct quattro *) cookie;
2138 int i;
2140 for (i = 0; i < 4; i++) {
2141 struct net_device *dev = qp->happy_meals[i];
2142 struct happy_meal *hp = dev->priv;
2143 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2145 HMD(("quattro_interrupt: status=%08x ", happy_status));
2147 if (!(happy_status & (GREG_STAT_ERRORS |
2148 GREG_STAT_MIFIRQ |
2149 GREG_STAT_TXALL |
2150 GREG_STAT_RXTOHOST)))
2151 continue;
2153 spin_lock(&hp->happy_lock);
2155 if (happy_status & GREG_STAT_ERRORS) {
2156 HMD(("ERRORS "));
2157 if (happy_meal_is_not_so_happy(hp, happy_status))
2158 goto next;
2161 if (happy_status & GREG_STAT_MIFIRQ) {
2162 HMD(("MIFIRQ "));
2163 happy_meal_mif_interrupt(hp);
2166 if (happy_status & GREG_STAT_TXALL) {
2167 HMD(("TXALL "));
2168 happy_meal_tx(hp);
2171 if (happy_status & GREG_STAT_RXTOHOST) {
2172 HMD(("RXTOHOST "));
2173 happy_meal_rx(hp, dev);
2176 next:
2177 spin_unlock(&hp->happy_lock);
2179 HMD(("done\n"));
2181 return IRQ_HANDLED;
2183 #endif
2185 static int happy_meal_open(struct net_device *dev)
2187 struct happy_meal *hp = dev->priv;
2188 int res;
2190 HMD(("happy_meal_open: "));
2192 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2193 * into a single source which we register handling at probe time.
2194 */
2195 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2196 if (request_irq(dev->irq, &happy_meal_interrupt,
2197 IRQF_SHARED, dev->name, (void *)dev)) {
2198 HMD(("EAGAIN\n"));
2199 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2200 dev->irq);
2202 return -EAGAIN;
2206 HMD(("to happy_meal_init\n"));
2208 spin_lock_irq(&hp->happy_lock);
2209 res = happy_meal_init(hp);
2210 spin_unlock_irq(&hp->happy_lock);
2212 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2213 free_irq(dev->irq, dev);
2214 return res;
2217 static int happy_meal_close(struct net_device *dev)
2219 struct happy_meal *hp = dev->priv;
2221 spin_lock_irq(&hp->happy_lock);
2222 happy_meal_stop(hp, hp->gregs);
2223 happy_meal_clean_rings(hp);
2225 /* If auto-negotiation timer is running, kill it. */
2226 del_timer(&hp->happy_timer);
2228 spin_unlock_irq(&hp->happy_lock);
2230 /* On Quattro QFE cards, all hme interrupts are concentrated
2231 * into a single source which we register handling at probe
2232 * time and never unregister.
2233 */
2234 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2235 free_irq(dev->irq, dev);
2237 return 0;
2240 #ifdef SXDEBUG
2241 #define SXD(x) printk x
2242 #else
2243 #define SXD(x)
2244 #endif
2246 static void happy_meal_tx_timeout(struct net_device *dev)
2248 struct happy_meal *hp = dev->priv;
2250 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2251 tx_dump_log();
2252 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2253 hme_read32(hp, hp->gregs + GREG_STAT),
2254 hme_read32(hp, hp->etxregs + ETX_CFG),
2255 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2257 spin_lock_irq(&hp->happy_lock);
2258 happy_meal_init(hp);
2259 spin_unlock_irq(&hp->happy_lock);
2261 netif_wake_queue(dev);
2264 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2266 struct happy_meal *hp = dev->priv;
2267 int entry;
2268 u32 tx_flags;
2270 tx_flags = TXFLAG_OWN;
2271 if (skb->ip_summed == CHECKSUM_HW) {
2272 u32 csum_start_off, csum_stuff_off;
2274 csum_start_off = (u32) (skb->h.raw - skb->data);
2275 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2277 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2278 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2279 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2282 spin_lock_irq(&hp->happy_lock);
2284 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2285 netif_stop_queue(dev);
2286 spin_unlock_irq(&hp->happy_lock);
2287 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2288 dev->name);
2289 return 1;
2292 entry = hp->tx_new;
2293 SXD(("SX<l[%d]e[%d]>", len, entry));
2294 hp->tx_skbs[entry] = skb;
2296 if (skb_shinfo(skb)->nr_frags == 0) {
2297 u32 mapping, len;
2299 len = skb->len;
2300 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2301 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2302 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2303 (tx_flags | (len & TXFLAG_SIZE)),
2304 mapping);
2305 entry = NEXT_TX(entry);
2306 } else {
2307 u32 first_len, first_mapping;
2308 int frag, first_entry = entry;
2310 /* We must give this initial chunk to the device last.
2311 * Otherwise we could race with the device.
2312 */
2313 first_len = skb_headlen(skb);
2314 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2315 entry = NEXT_TX(entry);
2317 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2318 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2319 u32 len, mapping, this_txflags;
2321 len = this_frag->size;
2322 mapping = hme_dma_map(hp,
2323 ((void *) page_address(this_frag->page) +
2324 this_frag->page_offset),
2325 len, DMA_TODEVICE);
2326 this_txflags = tx_flags;
2327 if (frag == skb_shinfo(skb)->nr_frags - 1)
2328 this_txflags |= TXFLAG_EOP;
2329 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2330 (this_txflags | (len & TXFLAG_SIZE)),
2331 mapping);
2332 entry = NEXT_TX(entry);
2334 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2335 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2336 first_mapping);
2339 hp->tx_new = entry;
2341 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2342 netif_stop_queue(dev);
2344 /* Get it going. */
2345 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2347 spin_unlock_irq(&hp->happy_lock);
2349 dev->trans_start = jiffies;
2351 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2352 return 0;
2355 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2357 struct happy_meal *hp = dev->priv;
2359 spin_lock_irq(&hp->happy_lock);
2360 happy_meal_get_counters(hp, hp->bigmacregs);
2361 spin_unlock_irq(&hp->happy_lock);
2363 return &hp->net_stats;
2366 static void happy_meal_set_multicast(struct net_device *dev)
2368 struct happy_meal *hp = dev->priv;
2369 void __iomem *bregs = hp->bigmacregs;
2370 struct dev_mc_list *dmi = dev->mc_list;
2371 char *addrs;
2372 int i;
2373 u32 crc;
2375 spin_lock_irq(&hp->happy_lock);
2377 netif_stop_queue(dev);
2379 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2380 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2381 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2382 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2383 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2384 } else if (dev->flags & IFF_PROMISC) {
2385 hme_write32(hp, bregs + BMAC_RXCFG,
2386 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2387 } else {
2388 u16 hash_table[4];
2390 for (i = 0; i < 4; i++)
2391 hash_table[i] = 0;
2393 for (i = 0; i < dev->mc_count; i++) {
2394 addrs = dmi->dmi_addr;
2395 dmi = dmi->next;
2397 if (!(*addrs & 1))
2398 continue;
2400 crc = ether_crc_le(6, addrs);
2401 crc >>= 26;
2402 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2404 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2405 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2406 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2407 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2410 netif_wake_queue(dev);
2412 spin_unlock_irq(&hp->happy_lock);
2415 /* Ethtool support... */
2416 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2418 struct happy_meal *hp = dev->priv;
2420 cmd->supported =
2421 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2422 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2423 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2425 /* XXX hardcoded stuff for now */
2426 cmd->port = PORT_TP; /* XXX no MII support */
2427 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2428 cmd->phy_address = 0; /* XXX fixed PHYAD */
2430 /* Record PHY settings. */
2431 spin_lock_irq(&hp->happy_lock);
2432 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2433 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2434 spin_unlock_irq(&hp->happy_lock);
2436 if (hp->sw_bmcr & BMCR_ANENABLE) {
2437 cmd->autoneg = AUTONEG_ENABLE;
2438 cmd->speed =
2439 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2440 SPEED_100 : SPEED_10;
2441 if (cmd->speed == SPEED_100)
2442 cmd->duplex =
2443 (hp->sw_lpa & (LPA_100FULL)) ?
2444 DUPLEX_FULL : DUPLEX_HALF;
2445 else
2446 cmd->duplex =
2447 (hp->sw_lpa & (LPA_10FULL)) ?
2448 DUPLEX_FULL : DUPLEX_HALF;
2449 } else {
2450 cmd->autoneg = AUTONEG_DISABLE;
2451 cmd->speed =
2452 (hp->sw_bmcr & BMCR_SPEED100) ?
2453 SPEED_100 : SPEED_10;
2454 cmd->duplex =
2455 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2456 DUPLEX_FULL : DUPLEX_HALF;
2458 return 0;
2461 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2463 struct happy_meal *hp = dev->priv;
2465 /* Verify the settings we care about. */
2466 if (cmd->autoneg != AUTONEG_ENABLE &&
2467 cmd->autoneg != AUTONEG_DISABLE)
2468 return -EINVAL;
2469 if (cmd->autoneg == AUTONEG_DISABLE &&
2470 ((cmd->speed != SPEED_100 &&
2471 cmd->speed != SPEED_10) ||
2472 (cmd->duplex != DUPLEX_HALF &&
2473 cmd->duplex != DUPLEX_FULL)))
2474 return -EINVAL;
2476 /* Ok, do it to it. */
2477 spin_lock_irq(&hp->happy_lock);
2478 del_timer(&hp->happy_timer);
2479 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2480 spin_unlock_irq(&hp->happy_lock);
2482 return 0;
2485 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2487 struct happy_meal *hp = dev->priv;
2489 strcpy(info->driver, "sunhme");
2490 strcpy(info->version, "2.02");
2491 if (hp->happy_flags & HFLAG_PCI) {
2492 struct pci_dev *pdev = hp->happy_dev;
2493 strcpy(info->bus_info, pci_name(pdev));
2495 #ifdef CONFIG_SBUS
2496 else {
2497 struct sbus_dev *sdev = hp->happy_dev;
2498 sprintf(info->bus_info, "SBUS:%d",
2499 sdev->slot);
2501 #endif
2504 static u32 hme_get_link(struct net_device *dev)
2506 struct happy_meal *hp = dev->priv;
2508 spin_lock_irq(&hp->happy_lock);
2509 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2510 spin_unlock_irq(&hp->happy_lock);
2512 return (hp->sw_bmsr & BMSR_LSTATUS);
2515 static struct ethtool_ops hme_ethtool_ops = {
2516 .get_settings = hme_get_settings,
2517 .set_settings = hme_set_settings,
2518 .get_drvinfo = hme_get_drvinfo,
2519 .get_link = hme_get_link,
2520 };
2522 static int hme_version_printed;
2524 #ifdef CONFIG_SBUS
2525 void __devinit quattro_get_ranges(struct quattro *qp)
2527 struct sbus_dev *sdev = qp->quattro_dev;
2528 int err;
2530 err = prom_getproperty(sdev->prom_node,
2531 "ranges",
2532 (char *)&qp->ranges[0],
2533 sizeof(qp->ranges));
2534 if (err == 0 || err == -1) {
2535 qp->nranges = 0;
2536 return;
2538 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2541 static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2543 struct sbus_dev *sdev = hp->happy_dev;
2544 int rng;
2546 for (rng = 0; rng < qp->nranges; rng++) {
2547 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2548 int reg;
2550 for (reg = 0; reg < 5; reg++) {
2551 if (sdev->reg_addrs[reg].which_io ==
2552 rngp->ot_child_space)
2553 break;
2555 if (reg == 5)
2556 continue;
2558 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2559 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2563 /* Given a happy meal sbus device, find it's quattro parent.
2564 * If none exist, allocate and return a new one.
2566 * Return NULL on failure.
2567 */
2568 static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
2570 struct sbus_dev *sdev;
2571 struct quattro *qp;
2572 int i;
2574 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2575 for (i = 0, sdev = qp->quattro_dev;
2576 (sdev != NULL) && (i < 4);
2577 sdev = sdev->next, i++) {
2578 if (sdev == goal_sdev)
2579 return qp;
2583 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2584 if (qp != NULL) {
2585 int i;
2587 for (i = 0; i < 4; i++)
2588 qp->happy_meals[i] = NULL;
2590 qp->quattro_dev = goal_sdev;
2591 qp->next = qfe_sbus_list;
2592 qfe_sbus_list = qp;
2593 quattro_get_ranges(qp);
2595 return qp;
2598 /* After all quattro cards have been probed, we call these functions
2599 * to register the IRQ handlers.
2600 */
2601 static void __init quattro_sbus_register_irqs(void)
2603 struct quattro *qp;
2605 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2606 struct sbus_dev *sdev = qp->quattro_dev;
2607 int err;
2609 err = request_irq(sdev->irqs[0],
2610 quattro_sbus_interrupt,
2611 IRQF_SHARED, "Quattro",
2612 qp);
2613 if (err != 0) {
2614 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2615 panic("QFE request irq");
2620 static void quattro_sbus_free_irqs(void)
2622 struct quattro *qp;
2624 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2625 struct sbus_dev *sdev = qp->quattro_dev;
2627 free_irq(sdev->irqs[0], qp);
2630 #endif /* CONFIG_SBUS */
2632 #ifdef CONFIG_PCI
2633 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2635 struct pci_dev *bdev = pdev->bus->self;
2636 struct quattro *qp;
2638 if (!bdev) return NULL;
2639 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2640 struct pci_dev *qpdev = qp->quattro_dev;
2642 if (qpdev == bdev)
2643 return qp;
2645 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2646 if (qp != NULL) {
2647 int i;
2649 for (i = 0; i < 4; i++)
2650 qp->happy_meals[i] = NULL;
2652 qp->quattro_dev = bdev;
2653 qp->next = qfe_pci_list;
2654 qfe_pci_list = qp;
2656 /* No range tricks necessary on PCI. */
2657 qp->nranges = 0;
2659 return qp;
2661 #endif /* CONFIG_PCI */
2663 #ifdef CONFIG_SBUS
2664 static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
2666 struct device_node *dp = sdev->ofdev.node;
2667 struct quattro *qp = NULL;
2668 struct happy_meal *hp;
2669 struct net_device *dev;
2670 int i, qfe_slot = -1;
2671 int err = -ENODEV;
2673 if (is_qfe) {
2674 qp = quattro_sbus_find(sdev);
2675 if (qp == NULL)
2676 goto err_out;
2677 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2678 if (qp->happy_meals[qfe_slot] == NULL)
2679 break;
2680 if (qfe_slot == 4)
2681 goto err_out;
2684 err = -ENOMEM;
2685 dev = alloc_etherdev(sizeof(struct happy_meal));
2686 if (!dev)
2687 goto err_out;
2688 SET_MODULE_OWNER(dev);
2689 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
2691 if (hme_version_printed++ == 0)
2692 printk(KERN_INFO "%s", version);
2694 /* If user did not specify a MAC address specifically, use
2695 * the Quattro local-mac-address property...
2696 */
2697 for (i = 0; i < 6; i++) {
2698 if (macaddr[i] != 0)
2699 break;
2701 if (i < 6) { /* a mac address was given */
2702 for (i = 0; i < 6; i++)
2703 dev->dev_addr[i] = macaddr[i];
2704 macaddr[5]++;
2705 } else {
2706 unsigned char *addr;
2707 int len;
2709 addr = of_get_property(dp, "local-mac-address", &len);
2711 if (qfe_slot != -1 && addr && len == 6)
2712 memcpy(dev->dev_addr, addr, 6);
2713 else
2714 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2717 hp = dev->priv;
2719 hp->happy_dev = sdev;
2721 spin_lock_init(&hp->happy_lock);
2723 err = -ENODEV;
2724 if (sdev->num_registers != 5) {
2725 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
2726 sdev->num_registers);
2727 goto err_out_free_netdev;
2730 if (qp != NULL) {
2731 hp->qfe_parent = qp;
2732 hp->qfe_ent = qfe_slot;
2733 qp->happy_meals[qfe_slot] = dev;
2734 quattro_apply_ranges(qp, hp);
2737 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2738 GREG_REG_SIZE, "HME Global Regs");
2739 if (!hp->gregs) {
2740 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2741 goto err_out_free_netdev;
2744 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2745 ETX_REG_SIZE, "HME TX Regs");
2746 if (!hp->etxregs) {
2747 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2748 goto err_out_iounmap;
2751 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2752 ERX_REG_SIZE, "HME RX Regs");
2753 if (!hp->erxregs) {
2754 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2755 goto err_out_iounmap;
2758 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2759 BMAC_REG_SIZE, "HME BIGMAC Regs");
2760 if (!hp->bigmacregs) {
2761 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2762 goto err_out_iounmap;
2765 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2766 TCVR_REG_SIZE, "HME Tranceiver Regs");
2767 if (!hp->tcvregs) {
2768 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2769 goto err_out_iounmap;
2772 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2773 if (hp->hm_revision == 0xff)
2774 hp->hm_revision = 0xa0;
2776 /* Now enable the feature flags we can. */
2777 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2778 hp->happy_flags = HFLAG_20_21;
2779 else if (hp->hm_revision != 0xa0)
2780 hp->happy_flags = HFLAG_NOT_A0;
2782 if (qp != NULL)
2783 hp->happy_flags |= HFLAG_QUATTRO;
2785 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2786 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
2787 "burst-sizes", 0x00);
2789 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2790 PAGE_SIZE,
2791 &hp->hblock_dvma);
2792 err = -ENOMEM;
2793 if (!hp->happy_block) {
2794 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2795 goto err_out_iounmap;
2798 /* Force check of the link first time we are brought up. */
2799 hp->linkcheck = 0;
2801 /* Force timer state to 'asleep' with count of zero. */
2802 hp->timer_state = asleep;
2803 hp->timer_ticks = 0;
2805 init_timer(&hp->happy_timer);
2807 hp->dev = dev;
2808 dev->open = &happy_meal_open;
2809 dev->stop = &happy_meal_close;
2810 dev->hard_start_xmit = &happy_meal_start_xmit;
2811 dev->get_stats = &happy_meal_get_stats;
2812 dev->set_multicast_list = &happy_meal_set_multicast;
2813 dev->tx_timeout = &happy_meal_tx_timeout;
2814 dev->watchdog_timeo = 5*HZ;
2815 dev->ethtool_ops = &hme_ethtool_ops;
2817 /* Happy Meal can do it all... except VLAN. */
2818 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2820 dev->irq = sdev->irqs[0];
2822 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2823 /* Hook up PCI register/dma accessors. */
2824 hp->read_desc32 = sbus_hme_read_desc32;
2825 hp->write_txd = sbus_hme_write_txd;
2826 hp->write_rxd = sbus_hme_write_rxd;
2827 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2828 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2829 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2830 sbus_dma_sync_single_for_cpu;
2831 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2832 sbus_dma_sync_single_for_device;
2833 hp->read32 = sbus_hme_read32;
2834 hp->write32 = sbus_hme_write32;
2835 #endif
2837 /* Grrr, Happy Meal comes up by default not advertising
2838 * full duplex 100baseT capabilities, fix this.
2839 */
2840 spin_lock_irq(&hp->happy_lock);
2841 happy_meal_set_initial_advertisement(hp);
2842 spin_unlock_irq(&hp->happy_lock);
2844 if (register_netdev(hp->dev)) {
2845 printk(KERN_ERR "happymeal: Cannot register net device, "
2846 "aborting.\n");
2847 goto err_out_free_consistent;
2850 dev_set_drvdata(&sdev->ofdev.dev, hp);
2852 if (qfe_slot != -1)
2853 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2854 dev->name, qfe_slot);
2855 else
2856 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2857 dev->name);
2859 for (i = 0; i < 6; i++)
2860 printk("%2.2x%c",
2861 dev->dev_addr[i], i == 5 ? ' ' : ':');
2862 printk("\n");
2864 return 0;
2866 err_out_free_consistent:
2867 sbus_free_consistent(hp->happy_dev,
2868 PAGE_SIZE,
2869 hp->happy_block,
2870 hp->hblock_dvma);
2872 err_out_iounmap:
2873 if (hp->gregs)
2874 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2875 if (hp->etxregs)
2876 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2877 if (hp->erxregs)
2878 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2879 if (hp->bigmacregs)
2880 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2881 if (hp->tcvregs)
2882 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2884 err_out_free_netdev:
2885 free_netdev(dev);
2887 err_out:
2888 return err;
2890 #endif
2892 #ifdef CONFIG_PCI
2893 #ifndef CONFIG_SPARC
2894 static int is_quattro_p(struct pci_dev *pdev)
2896 struct pci_dev *busdev = pdev->bus->self;
2897 struct list_head *tmp;
2898 int n_hmes;
2900 if (busdev == NULL ||
2901 busdev->vendor != PCI_VENDOR_ID_DEC ||
2902 busdev->device != PCI_DEVICE_ID_DEC_21153)
2903 return 0;
2905 n_hmes = 0;
2906 tmp = pdev->bus->devices.next;
2907 while (tmp != &pdev->bus->devices) {
2908 struct pci_dev *this_pdev = pci_dev_b(tmp);
2910 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2911 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2912 n_hmes++;
2914 tmp = tmp->next;
2917 if (n_hmes != 4)
2918 return 0;
2920 return 1;
2923 /* Fetch MAC address from vital product data of PCI ROM. */
2924 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2926 int this_offset;
2928 for (this_offset = 0x20; this_offset < len; this_offset++) {
2929 void __iomem *p = rom_base + this_offset;
2931 if (readb(p + 0) != 0x90 ||
2932 readb(p + 1) != 0x00 ||
2933 readb(p + 2) != 0x09 ||
2934 readb(p + 3) != 0x4e ||
2935 readb(p + 4) != 0x41 ||
2936 readb(p + 5) != 0x06)
2937 continue;
2939 this_offset += 6;
2940 p += 6;
2942 if (index == 0) {
2943 int i;
2945 for (i = 0; i < 6; i++)
2946 dev_addr[i] = readb(p + i);
2947 return 1;
2949 index--;
2951 return 0;
2954 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2956 size_t size;
2957 void __iomem *p = pci_map_rom(pdev, &size);
2959 if (p) {
2960 int index = 0;
2961 int found;
2963 if (is_quattro_p(pdev))
2964 index = PCI_SLOT(pdev->devfn);
2966 found = readb(p) == 0x55 &&
2967 readb(p + 1) == 0xaa &&
2968 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2969 pci_unmap_rom(pdev, p);
2970 if (found)
2971 return;
2974 /* Sun MAC prefix then 3 random bytes. */
2975 dev_addr[0] = 0x08;
2976 dev_addr[1] = 0x00;
2977 dev_addr[2] = 0x20;
2978 get_random_bytes(&dev_addr[3], 3);
2979 return;
2981 #endif /* !(CONFIG_SPARC) */
2983 static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2984 const struct pci_device_id *ent)
2986 struct quattro *qp = NULL;
2987 #ifdef CONFIG_SPARC
2988 struct pcidev_cookie *pcp;
2989 #endif
2990 struct happy_meal *hp;
2991 struct net_device *dev;
2992 void __iomem *hpreg_base;
2993 unsigned long hpreg_res;
2994 int i, qfe_slot = -1;
2995 char prom_name[64];
2996 int err;
2998 /* Now make sure pci_dev cookie is there. */
2999 #ifdef CONFIG_SPARC
3000 pcp = pdev->sysdata;
3001 if (pcp == NULL) {
3002 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
3003 return -ENODEV;
3006 strcpy(prom_name, pcp->prom_node->name);
3007 #else
3008 if (is_quattro_p(pdev))
3009 strcpy(prom_name, "SUNW,qfe");
3010 else
3011 strcpy(prom_name, "SUNW,hme");
3012 #endif
3014 err = -ENODEV;
3016 if (pci_enable_device(pdev))
3017 goto err_out;
3018 pci_set_master(pdev);
3020 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3021 qp = quattro_pci_find(pdev);
3022 if (qp == NULL)
3023 goto err_out;
3024 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3025 if (qp->happy_meals[qfe_slot] == NULL)
3026 break;
3027 if (qfe_slot == 4)
3028 goto err_out;
3031 dev = alloc_etherdev(sizeof(struct happy_meal));
3032 err = -ENOMEM;
3033 if (!dev)
3034 goto err_out;
3035 SET_MODULE_OWNER(dev);
3036 SET_NETDEV_DEV(dev, &pdev->dev);
3038 if (hme_version_printed++ == 0)
3039 printk(KERN_INFO "%s", version);
3041 dev->base_addr = (long) pdev;
3043 hp = (struct happy_meal *)dev->priv;
3044 memset(hp, 0, sizeof(*hp));
3046 hp->happy_dev = pdev;
3048 spin_lock_init(&hp->happy_lock);
3050 if (qp != NULL) {
3051 hp->qfe_parent = qp;
3052 hp->qfe_ent = qfe_slot;
3053 qp->happy_meals[qfe_slot] = dev;
3056 hpreg_res = pci_resource_start(pdev, 0);
3057 err = -ENODEV;
3058 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3059 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3060 goto err_out_clear_quattro;
3062 if (pci_request_regions(pdev, DRV_NAME)) {
3063 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3064 "aborting.\n");
3065 goto err_out_clear_quattro;
3068 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3069 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3070 goto err_out_free_res;
3073 for (i = 0; i < 6; i++) {
3074 if (macaddr[i] != 0)
3075 break;
3077 if (i < 6) { /* a mac address was given */
3078 for (i = 0; i < 6; i++)
3079 dev->dev_addr[i] = macaddr[i];
3080 macaddr[5]++;
3081 } else {
3082 #ifdef CONFIG_SPARC
3083 unsigned char *addr;
3084 int len;
3086 if (qfe_slot != -1 &&
3087 (addr = of_get_property(pcp->prom_node,
3088 "local-mac-address", &len)) != NULL
3089 && len == 6) {
3090 memcpy(dev->dev_addr, addr, 6);
3091 } else {
3092 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3094 #else
3095 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3096 #endif
3099 /* Layout registers. */
3100 hp->gregs = (hpreg_base + 0x0000UL);
3101 hp->etxregs = (hpreg_base + 0x2000UL);
3102 hp->erxregs = (hpreg_base + 0x4000UL);
3103 hp->bigmacregs = (hpreg_base + 0x6000UL);
3104 hp->tcvregs = (hpreg_base + 0x7000UL);
3106 #ifdef CONFIG_SPARC
3107 hp->hm_revision = of_getintprop_default(pcp->prom_node, "hm-rev", 0xff);
3108 if (hp->hm_revision == 0xff) {
3109 unsigned char prev;
3111 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3112 hp->hm_revision = 0xc0 | (prev & 0x0f);
3114 #else
3115 /* works with this on non-sparc hosts */
3116 hp->hm_revision = 0x20;
3117 #endif
3119 /* Now enable the feature flags we can. */
3120 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3121 hp->happy_flags = HFLAG_20_21;
3122 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3123 hp->happy_flags = HFLAG_NOT_A0;
3125 if (qp != NULL)
3126 hp->happy_flags |= HFLAG_QUATTRO;
3128 /* And of course, indicate this is PCI. */
3129 hp->happy_flags |= HFLAG_PCI;
3131 #ifdef CONFIG_SPARC
3132 /* Assume PCI happy meals can handle all burst sizes. */
3133 hp->happy_bursts = DMA_BURSTBITS;
3134 #endif
3136 hp->happy_block = (struct hmeal_init_block *)
3137 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3139 err = -ENODEV;
3140 if (!hp->happy_block) {
3141 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3142 goto err_out_iounmap;
3145 hp->linkcheck = 0;
3146 hp->timer_state = asleep;
3147 hp->timer_ticks = 0;
3149 init_timer(&hp->happy_timer);
3151 hp->dev = dev;
3152 dev->open = &happy_meal_open;
3153 dev->stop = &happy_meal_close;
3154 dev->hard_start_xmit = &happy_meal_start_xmit;
3155 dev->get_stats = &happy_meal_get_stats;
3156 dev->set_multicast_list = &happy_meal_set_multicast;
3157 dev->tx_timeout = &happy_meal_tx_timeout;
3158 dev->watchdog_timeo = 5*HZ;
3159 dev->ethtool_ops = &hme_ethtool_ops;
3160 dev->irq = pdev->irq;
3161 dev->dma = 0;
3163 /* Happy Meal can do it all... */
3164 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3166 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3167 /* Hook up PCI register/dma accessors. */
3168 hp->read_desc32 = pci_hme_read_desc32;
3169 hp->write_txd = pci_hme_write_txd;
3170 hp->write_rxd = pci_hme_write_rxd;
3171 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3172 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3173 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3174 pci_dma_sync_single_for_cpu;
3175 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3176 pci_dma_sync_single_for_device;
3177 hp->read32 = pci_hme_read32;
3178 hp->write32 = pci_hme_write32;
3179 #endif
3181 /* Grrr, Happy Meal comes up by default not advertising
3182 * full duplex 100baseT capabilities, fix this.
3183 */
3184 spin_lock_irq(&hp->happy_lock);
3185 happy_meal_set_initial_advertisement(hp);
3186 spin_unlock_irq(&hp->happy_lock);
3188 if (register_netdev(hp->dev)) {
3189 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3190 "aborting.\n");
3191 goto err_out_iounmap;
3194 dev_set_drvdata(&pdev->dev, hp);
3196 if (!qfe_slot) {
3197 struct pci_dev *qpdev = qp->quattro_dev;
3199 prom_name[0] = 0;
3200 if (!strncmp(dev->name, "eth", 3)) {
3201 int i = simple_strtoul(dev->name + 3, NULL, 10);
3202 sprintf(prom_name, "-%d", i + 3);
3204 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3205 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3206 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3207 printk("DEC 21153 PCI Bridge\n");
3208 else
3209 printk("unknown bridge %04x.%04x\n",
3210 qpdev->vendor, qpdev->device);
3213 if (qfe_slot != -1)
3214 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3215 dev->name, qfe_slot);
3216 else
3217 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3218 dev->name);
3220 for (i = 0; i < 6; i++)
3221 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3223 printk("\n");
3225 return 0;
3227 err_out_iounmap:
3228 iounmap(hp->gregs);
3230 err_out_free_res:
3231 pci_release_regions(pdev);
3233 err_out_clear_quattro:
3234 if (qp != NULL)
3235 qp->happy_meals[qfe_slot] = NULL;
3237 free_netdev(dev);
3239 err_out:
3240 return err;
3243 static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3245 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3246 struct net_device *net_dev = hp->dev;
3248 unregister_netdev(net_dev);
3250 pci_free_consistent(hp->happy_dev,
3251 PAGE_SIZE,
3252 hp->happy_block,
3253 hp->hblock_dvma);
3254 iounmap(hp->gregs);
3255 pci_release_regions(hp->happy_dev);
3257 free_netdev(net_dev);
3259 dev_set_drvdata(&pdev->dev, NULL);
3262 static struct pci_device_id happymeal_pci_ids[] = {
3263 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3264 { } /* Terminating entry */
3265 };
3267 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3269 static struct pci_driver hme_pci_driver = {
3270 .name = "hme",
3271 .id_table = happymeal_pci_ids,
3272 .probe = happy_meal_pci_probe,
3273 .remove = __devexit_p(happy_meal_pci_remove),
3274 };
3276 static int __init happy_meal_pci_init(void)
3278 return pci_register_driver(&hme_pci_driver);
3281 static void happy_meal_pci_exit(void)
3283 pci_unregister_driver(&hme_pci_driver);
3285 while (qfe_pci_list) {
3286 struct quattro *qfe = qfe_pci_list;
3287 struct quattro *next = qfe->next;
3289 kfree(qfe);
3291 qfe_pci_list = next;
3295 #endif
3297 #ifdef CONFIG_SBUS
3298 static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
3300 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
3301 struct device_node *dp = dev->node;
3302 char *model = of_get_property(dp, "model", NULL);
3303 int is_qfe = (match->data != NULL);
3305 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3306 is_qfe = 1;
3308 return happy_meal_sbus_probe_one(sdev, is_qfe);
3311 static int __devexit hme_sbus_remove(struct of_device *dev)
3313 struct happy_meal *hp = dev_get_drvdata(&dev->dev);
3314 struct net_device *net_dev = hp->dev;
3316 unregister_netdevice(net_dev);
3318 /* XXX qfe parent interrupt... */
3320 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3321 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3322 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3323 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3324 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3325 sbus_free_consistent(hp->happy_dev,
3326 PAGE_SIZE,
3327 hp->happy_block,
3328 hp->hblock_dvma);
3330 free_netdev(net_dev);
3332 dev_set_drvdata(&dev->dev, NULL);
3334 return 0;
3337 static struct of_device_id hme_sbus_match[] = {
3339 .name = "SUNW,hme",
3340 },
3342 .name = "SUNW,qfe",
3343 .data = (void *) 1,
3344 },
3346 .name = "qfe",
3347 .data = (void *) 1,
3348 },
3349 {},
3350 };
3352 MODULE_DEVICE_TABLE(of, hme_sbus_match);
3354 static struct of_platform_driver hme_sbus_driver = {
3355 .name = "hme",
3356 .match_table = hme_sbus_match,
3357 .probe = hme_sbus_probe,
3358 .remove = __devexit_p(hme_sbus_remove),
3359 };
3361 static int __init happy_meal_sbus_init(void)
3363 int err;
3365 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
3366 if (!err)
3367 quattro_sbus_register_irqs();
3369 return err;
3372 static void happy_meal_sbus_exit(void)
3374 of_unregister_driver(&hme_sbus_driver);
3375 quattro_sbus_free_irqs();
3377 while (qfe_sbus_list) {
3378 struct quattro *qfe = qfe_sbus_list;
3379 struct quattro *next = qfe->next;
3381 kfree(qfe);
3383 qfe_sbus_list = next;
3386 #endif
3388 static int __init happy_meal_probe(void)
3390 int err = 0;
3392 #ifdef CONFIG_SBUS
3393 err = happy_meal_sbus_init();
3394 #endif
3395 #ifdef CONFIG_PCI
3396 if (!err) {
3397 err = happy_meal_pci_init();
3398 #ifdef CONFIG_SBUS
3399 if (err)
3400 happy_meal_sbus_exit();
3401 #endif
3403 #endif
3405 return err;
3409 static void __exit happy_meal_exit(void)
3411 #ifdef CONFIG_SBUS
3412 happy_meal_sbus_exit();
3413 #endif
3414 #ifdef CONFIG_PCI
3415 happy_meal_pci_exit();
3416 #endif
3419 module_init(happy_meal_probe);
3420 module_exit(happy_meal_exit);