ia64/linux-2.6.18-xen.hg

view drivers/net/spider_net.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Network device driver for Cell Processor-Based Blade
3 *
4 * (C) Copyright IBM Corp. 2005
5 *
6 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
7 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
24 #ifndef _SPIDER_NET_H
25 #define _SPIDER_NET_H
27 #include "sungem_phy.h"
29 extern int spider_net_stop(struct net_device *netdev);
30 extern int spider_net_open(struct net_device *netdev);
32 extern struct ethtool_ops spider_net_ethtool_ops;
34 extern char spider_net_driver_name[];
36 #define SPIDER_NET_MAX_FRAME 2312
37 #define SPIDER_NET_MAX_MTU 2294
38 #define SPIDER_NET_MIN_MTU 64
40 #define SPIDER_NET_RXBUF_ALIGN 128
42 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
43 #define SPIDER_NET_RX_DESCRIPTORS_MIN 16
44 #define SPIDER_NET_RX_DESCRIPTORS_MAX 512
46 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
47 #define SPIDER_NET_TX_DESCRIPTORS_MIN 16
48 #define SPIDER_NET_TX_DESCRIPTORS_MAX 512
50 #define SPIDER_NET_TX_TIMER 20
52 #define SPIDER_NET_RX_CSUM_DEFAULT 1
54 #define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
55 #define SPIDER_NET_NAPI_WEIGHT 64
57 #define SPIDER_NET_FIRMWARE_SEQS 6
58 #define SPIDER_NET_FIRMWARE_SEQWORDS 1024
59 #define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
60 SPIDER_NET_FIRMWARE_SEQWORDS * \
61 sizeof(u32))
62 #define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
64 /** spider_net SMMIO registers */
65 #define SPIDER_NET_GHIINT0STS 0x00000000
66 #define SPIDER_NET_GHIINT1STS 0x00000004
67 #define SPIDER_NET_GHIINT2STS 0x00000008
68 #define SPIDER_NET_GHIINT0MSK 0x00000010
69 #define SPIDER_NET_GHIINT1MSK 0x00000014
70 #define SPIDER_NET_GHIINT2MSK 0x00000018
72 #define SPIDER_NET_GRESUMINTNUM 0x00000020
73 #define SPIDER_NET_GREINTNUM 0x00000024
75 #define SPIDER_NET_GFFRMNUM 0x00000028
76 #define SPIDER_NET_GFAFRMNUM 0x0000002c
77 #define SPIDER_NET_GFBFRMNUM 0x00000030
78 #define SPIDER_NET_GFCFRMNUM 0x00000034
79 #define SPIDER_NET_GFDFRMNUM 0x00000038
81 /* clear them (don't use it) */
82 #define SPIDER_NET_GFREECNNUM 0x0000003c
83 #define SPIDER_NET_GONETIMENUM 0x00000040
85 #define SPIDER_NET_GTOUTFRMNUM 0x00000044
87 #define SPIDER_NET_GTXMDSET 0x00000050
88 #define SPIDER_NET_GPCCTRL 0x00000054
89 #define SPIDER_NET_GRXMDSET 0x00000058
90 #define SPIDER_NET_GIPSECINIT 0x0000005c
91 #define SPIDER_NET_GFTRESTRT 0x00000060
92 #define SPIDER_NET_GRXDMAEN 0x00000064
93 #define SPIDER_NET_GMRWOLCTRL 0x00000068
94 #define SPIDER_NET_GPCWOPCMD 0x0000006c
95 #define SPIDER_NET_GPCROPCMD 0x00000070
96 #define SPIDER_NET_GTTFRMCNT 0x00000078
97 #define SPIDER_NET_GTESTMD 0x0000007c
99 #define SPIDER_NET_GSINIT 0x00000080
100 #define SPIDER_NET_GSnPRGADR 0x00000084
101 #define SPIDER_NET_GSnPRGDAT 0x00000088
103 #define SPIDER_NET_GMACOPEMD 0x00000100
104 #define SPIDER_NET_GMACLENLMT 0x00000108
105 #define SPIDER_NET_GMACINTEN 0x00000118
106 #define SPIDER_NET_GMACPHYCTRL 0x00000120
108 #define SPIDER_NET_GMACAPAUSE 0x00000154
109 #define SPIDER_NET_GMACTXPAUSE 0x00000164
111 #define SPIDER_NET_GMACMODE 0x000001b0
112 #define SPIDER_NET_GMACBSTLMT 0x000001b4
114 #define SPIDER_NET_GMACUNIMACU 0x000001c0
115 #define SPIDER_NET_GMACUNIMACL 0x000001c8
117 #define SPIDER_NET_GMRMHFILnR 0x00000400
118 #define SPIDER_NET_MULTICAST_HASHES 256
120 #define SPIDER_NET_GMRUAFILnR 0x00000500
121 #define SPIDER_NET_GMRUA0FIL15R 0x00000578
123 #define SPIDER_NET_GTTQMSK 0x00000934
125 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
126 * 0x00000b.. for DMA controller B, etc. */
127 #define SPIDER_NET_GDADCHA 0x00000a00
128 #define SPIDER_NET_GDADMACCNTR 0x00000a04
129 #define SPIDER_NET_GDACTDPA 0x00000a08
130 #define SPIDER_NET_GDACTDCNT 0x00000a0c
131 #define SPIDER_NET_GDACDBADDR 0x00000a20
132 #define SPIDER_NET_GDACDBSIZE 0x00000a24
133 #define SPIDER_NET_GDACNEXTDA 0x00000a28
134 #define SPIDER_NET_GDACCOMST 0x00000a2c
135 #define SPIDER_NET_GDAWBCOMST 0x00000a30
136 #define SPIDER_NET_GDAWBRSIZE 0x00000a34
137 #define SPIDER_NET_GDAWBVSIZE 0x00000a38
138 #define SPIDER_NET_GDAWBTRST 0x00000a3c
139 #define SPIDER_NET_GDAWBTRERR 0x00000a40
141 /* TX DMA controller registers */
142 #define SPIDER_NET_GDTDCHA 0x00000e00
143 #define SPIDER_NET_GDTDMACCNTR 0x00000e04
144 #define SPIDER_NET_GDTCDPA 0x00000e08
145 #define SPIDER_NET_GDTDMASEL 0x00000e14
147 #define SPIDER_NET_ECMODE 0x00000f00
148 /* clock and reset control register */
149 #define SPIDER_NET_CKRCTRL 0x00000ff0
151 /** SCONFIG registers */
152 #define SPIDER_NET_SCONFIG_IOACTE 0x00002810
154 /** interrupt mask registers */
155 #define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
156 #define SPIDER_NET_INT1_MASK_VALUE 0xffff7ff7
157 /* no MAC aborts -> auto retransmission */
158 #define SPIDER_NET_INT2_MASK_VALUE 0xffef7ff1
160 /* we rely on flagged descriptor interrupts */
161 #define SPIDER_NET_FRAMENUM_VALUE 0x00000000
162 /* set this first, then the FRAMENUM_VALUE */
163 #define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
165 #define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
166 #define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
168 #define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
169 /* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
170 #define SPIDER_NET_RXMODE_VALUE 0x00000011
171 /* auto retransmission in case of MAC aborts */
172 #define SPIDER_NET_TXMODE_VALUE 0x00010000
173 #define SPIDER_NET_RESTART_VALUE 0x00000000
174 #define SPIDER_NET_WOL_VALUE 0x00001111
175 #if 0
176 #define SPIDER_NET_WOL_VALUE 0x00000000
177 #endif
178 #define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
180 /* pause frames: automatic, no upper retransmission count */
181 /* outside loopback mode: ETOMOD signal dont matter, not connected */
182 #define SPIDER_NET_OPMODE_VALUE 0x00000063
183 /*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/
184 #define SPIDER_NET_LENLMT_VALUE 0x00000908
186 #define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
187 #define SPIDER_NET_TXPAUSE_VALUE 0x00000000
189 #define SPIDER_NET_MACMODE_VALUE 0x00000001
190 #define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
192 /* 1(0) enable r/tx dma
193 * 0000000 fixed to 0
194 *
195 * 000000 fixed to 0
196 * 0(1) en/disable descr writeback on force end
197 * 0(1) force end
198 *
199 * 000000 fixed to 0
200 * 00 burst alignment: 128 bytes
201 *
202 * 00000 fixed to 0
203 * 0 descr writeback size 32 bytes
204 * 0(1) descr chain end interrupt enable
205 * 0(1) descr status writeback enable */
207 /* to set RX_DMA_EN */
208 #define SPIDER_NET_DMA_RX_VALUE 0x80000000
209 #define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
210 /* to set TX_DMA_EN */
211 #define SPIDER_NET_TX_DMA_EN 0x80000000
212 #define SPIDER_NET_GDTDCEIDIS 0x00000002
213 #define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
214 SPIDER_NET_GDTDCEIDIS
215 #define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
217 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
218 #define SPIDER_NET_UA_DESCR_VALUE 0x00080000
219 #define SPIDER_NET_PROMISC_VALUE 0x00080000
220 #define SPIDER_NET_NONPROMISC_VALUE 0x00000000
222 #define SPIDER_NET_DMASEL_VALUE 0x00000001
224 #define SPIDER_NET_ECMODE_VALUE 0x00000000
226 #define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
227 #define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
229 #define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
230 #define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
232 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
233 * with 1 << SPIDER_NET_... */
234 enum spider_net_int0_status {
235 SPIDER_NET_GPHYINT = 0,
236 SPIDER_NET_GMAC2INT,
237 SPIDER_NET_GMAC1INT,
238 SPIDER_NET_GIPSINT,
239 SPIDER_NET_GFIFOINT,
240 SPIDER_NET_GDMACINT,
241 SPIDER_NET_GSYSINT,
242 SPIDER_NET_GPWOPCMPINT,
243 SPIDER_NET_GPROPCMPINT,
244 SPIDER_NET_GPWFFINT,
245 SPIDER_NET_GRMDADRINT,
246 SPIDER_NET_GRMARPINT,
247 SPIDER_NET_GRMMPINT,
248 SPIDER_NET_GDTDEN0INT,
249 SPIDER_NET_GDDDEN0INT,
250 SPIDER_NET_GDCDEN0INT,
251 SPIDER_NET_GDBDEN0INT,
252 SPIDER_NET_GDADEN0INT,
253 SPIDER_NET_GDTFDCINT,
254 SPIDER_NET_GDDFDCINT,
255 SPIDER_NET_GDCFDCINT,
256 SPIDER_NET_GDBFDCINT,
257 SPIDER_NET_GDAFDCINT,
258 SPIDER_NET_GTTEDINT,
259 SPIDER_NET_GDTDCEINT,
260 SPIDER_NET_GRFDNMINT,
261 SPIDER_NET_GRFCNMINT,
262 SPIDER_NET_GRFBNMINT,
263 SPIDER_NET_GRFANMINT,
264 SPIDER_NET_GRFNMINT,
265 SPIDER_NET_G1TMCNTINT,
266 SPIDER_NET_GFREECNTINT
267 };
268 /* GHIINT1STS bits */
269 enum spider_net_int1_status {
270 SPIDER_NET_GTMFLLINT = 0,
271 SPIDER_NET_GRMFLLINT,
272 SPIDER_NET_GTMSHTINT,
273 SPIDER_NET_GDTINVDINT,
274 SPIDER_NET_GRFDFLLINT,
275 SPIDER_NET_GDDDCEINT,
276 SPIDER_NET_GDDINVDINT,
277 SPIDER_NET_GRFCFLLINT,
278 SPIDER_NET_GDCDCEINT,
279 SPIDER_NET_GDCINVDINT,
280 SPIDER_NET_GRFBFLLINT,
281 SPIDER_NET_GDBDCEINT,
282 SPIDER_NET_GDBINVDINT,
283 SPIDER_NET_GRFAFLLINT,
284 SPIDER_NET_GDADCEINT,
285 SPIDER_NET_GDAINVDINT,
286 SPIDER_NET_GDTRSERINT,
287 SPIDER_NET_GDDRSERINT,
288 SPIDER_NET_GDCRSERINT,
289 SPIDER_NET_GDBRSERINT,
290 SPIDER_NET_GDARSERINT,
291 SPIDER_NET_GDSERINT,
292 SPIDER_NET_GDTPTERINT,
293 SPIDER_NET_GDDPTERINT,
294 SPIDER_NET_GDCPTERINT,
295 SPIDER_NET_GDBPTERINT,
296 SPIDER_NET_GDAPTERINT
297 };
298 /* GHIINT2STS bits */
299 enum spider_net_int2_status {
300 SPIDER_NET_GPROPERINT = 0,
301 SPIDER_NET_GMCTCRSNGINT,
302 SPIDER_NET_GMCTLCOLINT,
303 SPIDER_NET_GMCTTMOTINT,
304 SPIDER_NET_GMCRCAERINT,
305 SPIDER_NET_GMCRCALERINT,
306 SPIDER_NET_GMCRALNERINT,
307 SPIDER_NET_GMCROVRINT,
308 SPIDER_NET_GMCRRNTINT,
309 SPIDER_NET_GMCRRXERINT,
310 SPIDER_NET_GTITCSERINT,
311 SPIDER_NET_GTIFMTERINT,
312 SPIDER_NET_GTIPKTRVKINT,
313 SPIDER_NET_GTISPINGINT,
314 SPIDER_NET_GTISADNGINT,
315 SPIDER_NET_GTISPDNGINT,
316 SPIDER_NET_GRIFMTERINT,
317 SPIDER_NET_GRIPKTRVKINT,
318 SPIDER_NET_GRISPINGINT,
319 SPIDER_NET_GRISADNGINT,
320 SPIDER_NET_GRISPDNGINT
321 };
323 #define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GTTEDINT) | \
324 (1 << SPIDER_NET_GDTDCEINT) | \
325 (1 << SPIDER_NET_GDTFDCINT) )
327 /* we rely on flagged descriptor interrupts*/
328 #define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) | \
329 (1 << SPIDER_NET_GRMFLLINT) )
331 #define SPIDER_NET_ERRINT ( 0xffffffff & \
332 (~SPIDER_NET_TXINT) & \
333 (~SPIDER_NET_RXINT) )
335 #define SPIDER_NET_GPREXEC 0x80000000
336 #define SPIDER_NET_GPRDAT_MASK 0x0000ffff
338 #define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
339 #define SPIDER_NET_DMAC_NOCS 0x00040000
340 #define SPIDER_NET_DMAC_TCP 0x00020000
341 #define SPIDER_NET_DMAC_UDP 0x00030000
342 #define SPIDER_NET_TXDCEST 0x08000000
344 #define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
345 #define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
346 #define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
347 #define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
348 #define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
349 #define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
350 #define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
351 #define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
353 struct spider_net_descr {
354 /* as defined by the hardware */
355 u32 buf_addr;
356 u32 buf_size;
357 u32 next_descr_addr;
358 u32 dmac_cmd_status;
359 u32 result_size;
360 u32 valid_size; /* all zeroes for tx */
361 u32 data_status;
362 u32 data_error; /* all zeroes for tx */
364 /* used in the driver */
365 struct sk_buff *skb;
366 u32 bus_addr;
367 struct spider_net_descr *next;
368 struct spider_net_descr *prev;
369 } __attribute__((aligned(32)));
371 struct spider_net_descr_chain {
372 spinlock_t lock;
373 struct spider_net_descr *head;
374 struct spider_net_descr *tail;
375 };
377 /* descriptor data_status bits */
378 #define SPIDER_NET_RX_IPCHK 29
379 #define SPIDER_NET_RX_TCPCHK 28
380 #define SPIDER_NET_VLAN_PACKET 21
381 #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
382 (1 << SPIDER_NET_RX_TCPCHK) )
384 /* descriptor data_error bits */
385 #define SPIDER_NET_RX_IPCHKERR 27
386 #define SPIDER_NET_RX_RXTCPCHKERR 28
388 #define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
390 /* the cases we don't pass the packet to the stack.
391 * 701b8000 would be correct, but every packets gets that flag */
392 #define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
394 #define SPIDER_NET_DESCR_SIZE 32
396 /* this will be bigger some time */
397 struct spider_net_options {
398 int rx_csum; /* for rx: if 0 ip_summed=NONE,
399 if 1 and hw has verified, ip_summed=UNNECESSARY */
400 };
402 #define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \
403 NETIF_MSG_PROBE | \
404 NETIF_MSG_LINK | \
405 NETIF_MSG_TIMER | \
406 NETIF_MSG_IFDOWN | \
407 NETIF_MSG_IFUP | \
408 NETIF_MSG_RX_ERR | \
409 NETIF_MSG_TX_ERR | \
410 NETIF_MSG_TX_QUEUED | \
411 NETIF_MSG_INTR | \
412 NETIF_MSG_TX_DONE | \
413 NETIF_MSG_RX_STATUS | \
414 NETIF_MSG_PKTDATA | \
415 NETIF_MSG_HW | \
416 NETIF_MSG_WOL )
418 struct spider_net_card {
419 struct net_device *netdev;
420 struct pci_dev *pdev;
421 struct mii_phy phy;
423 void __iomem *regs;
425 struct spider_net_descr_chain tx_chain;
426 struct spider_net_descr_chain rx_chain;
428 struct net_device_stats netdev_stats;
430 struct spider_net_options options;
432 spinlock_t intmask_lock;
433 struct tasklet_struct rxram_full_tl;
434 struct timer_list tx_timer;
436 struct work_struct tx_timeout_task;
437 atomic_t tx_timeout_task_counter;
438 wait_queue_head_t waitq;
440 /* for ethtool */
441 int msg_enable;
443 int rx_desc;
444 int tx_desc;
446 struct spider_net_descr descr[0];
447 };
449 #define pr_err(fmt,arg...) \
450 printk(KERN_ERR fmt ,##arg)
452 #endif