ia64/linux-2.6.18-xen.hg

view drivers/net/smc91x.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
42 #if defined(CONFIG_ARCH_LUBBOCK)
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
66 #define SMC_IO_SHIFT 0
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
112 #define SMC_IRQ_FLAGS (0)
114 #elif defined(CONFIG_SA1100_ASSABET)
116 #include <asm/arch/neponset.h>
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
132 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
137 #define SMC_IO_SHIFT 0
138 #define SMC_NOWAIT 1
140 #define SMC_inw(a, r) readw((a) + (r))
141 #define SMC_outw(v, a, r) writew(v, (a) + (r))
142 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
143 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
145 #elif defined(CONFIG_ARCH_INNOKOM) || \
146 defined(CONFIG_MACH_MAINSTONE) || \
147 defined(CONFIG_ARCH_PXA_IDP) || \
148 defined(CONFIG_ARCH_RAMSES)
150 #define SMC_CAN_USE_8BIT 1
151 #define SMC_CAN_USE_16BIT 1
152 #define SMC_CAN_USE_32BIT 1
153 #define SMC_IO_SHIFT 0
154 #define SMC_NOWAIT 1
155 #define SMC_USE_PXA_DMA 1
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_inw(a, r) readw((a) + (r))
159 #define SMC_inl(a, r) readl((a) + (r))
160 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
161 #define SMC_outl(v, a, r) writel(v, (a) + (r))
162 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
165 /* We actually can't write halfwords properly if not word aligned */
166 static inline void
167 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
168 {
169 if (reg & 2) {
170 unsigned int v = val << 16;
171 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
172 writel(v, ioaddr + (reg & ~2));
173 } else {
174 writew(val, ioaddr + reg);
175 }
176 }
178 #elif defined(CONFIG_ARCH_OMAP)
180 /* We can only do 16-bit reads and writes in the static memory space. */
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
192 #include <asm/mach-types.h>
193 #include <asm/arch/cpu.h>
195 #define SMC_IRQ_FLAGS (( \
196 machine_is_omap_h2() \
197 || machine_is_omap_h3() \
198 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
199 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
202 #elif defined(CONFIG_SH_SH4202_MICRODEV)
204 #define SMC_CAN_USE_8BIT 0
205 #define SMC_CAN_USE_16BIT 1
206 #define SMC_CAN_USE_32BIT 0
208 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
209 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
210 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
211 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
212 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
213 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
214 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
215 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
216 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
217 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
219 #define SMC_IRQ_FLAGS (0)
221 #elif defined(CONFIG_ISA)
223 #define SMC_CAN_USE_8BIT 1
224 #define SMC_CAN_USE_16BIT 1
225 #define SMC_CAN_USE_32BIT 0
227 #define SMC_inb(a, r) inb((a) + (r))
228 #define SMC_inw(a, r) inw((a) + (r))
229 #define SMC_outb(v, a, r) outb(v, (a) + (r))
230 #define SMC_outw(v, a, r) outw(v, (a) + (r))
231 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
232 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
234 #elif defined(CONFIG_M32R)
236 #define SMC_CAN_USE_8BIT 0
237 #define SMC_CAN_USE_16BIT 1
238 #define SMC_CAN_USE_32BIT 0
240 #define SMC_inb(a, r) inb((u32)a) + (r))
241 #define SMC_inw(a, r) inw(((u32)a) + (r))
242 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
243 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
244 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
245 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
247 #define SMC_IRQ_FLAGS (0)
249 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
250 #define RPC_LSB_DEFAULT RPC_LED_100_10
252 #elif defined(CONFIG_MACH_LPD79520) \
253 || defined(CONFIG_MACH_LPD7A400) \
254 || defined(CONFIG_MACH_LPD7A404)
256 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
257 * way that the CPU handles chip selects and the way that the SMC chip
258 * expects the chip select to operate. Refer to
259 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
260 * IOBARRIER is a byte, in order that we read the least-common
261 * denominator. It would be wasteful to read 32 bits from an 8-bit
262 * accessible region.
263 *
264 * There is no explicit protection against interrupts intervening
265 * between the writew and the IOBARRIER. In SMC ISR there is a
266 * preamble that performs an IOBARRIER in the extremely unlikely event
267 * that the driver interrupts itself between a writew to the chip an
268 * the IOBARRIER that follows *and* the cache is large enough that the
269 * first off-chip access while handing the interrupt is to the SMC
270 * chip. Other devices in the same address space as the SMC chip must
271 * be aware of the potential for trouble and perform a similar
272 * IOBARRIER on entry to their ISR.
273 */
275 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
277 #define SMC_CAN_USE_8BIT 0
278 #define SMC_CAN_USE_16BIT 1
279 #define SMC_CAN_USE_32BIT 0
280 #define SMC_NOWAIT 0
281 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
283 #define SMC_inw(a,r)\
284 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
285 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
287 #define SMC_insw LPD7_SMC_insw
288 static inline void LPD7_SMC_insw (unsigned char* a, int r,
289 unsigned char* p, int l)
290 {
291 unsigned short* ps = (unsigned short*) p;
292 while (l-- > 0) {
293 *ps++ = readw (a + r);
294 LPD7X_IOBARRIER;
295 }
296 }
298 #define SMC_outsw LPD7_SMC_outsw
299 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
300 unsigned char* p, int l)
301 {
302 unsigned short* ps = (unsigned short*) p;
303 while (l-- > 0) {
304 writew (*ps++, a + r);
305 LPD7X_IOBARRIER;
306 }
307 }
309 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
311 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
312 #define RPC_LSB_DEFAULT RPC_LED_100_10
314 #elif defined(CONFIG_SOC_AU1X00)
316 #include <au1xxx.h>
318 /* We can only do 16-bit reads and writes in the static memory space. */
319 #define SMC_CAN_USE_8BIT 0
320 #define SMC_CAN_USE_16BIT 1
321 #define SMC_CAN_USE_32BIT 0
322 #define SMC_IO_SHIFT 0
323 #define SMC_NOWAIT 1
325 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
326 #define SMC_insw(a, r, p, l) \
327 do { \
328 unsigned long _a = (unsigned long)((a) + (r)); \
329 int _l = (l); \
330 u16 *_p = (u16 *)(p); \
331 while (_l-- > 0) \
332 *_p++ = au_readw(_a); \
333 } while(0)
334 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
335 #define SMC_outsw(a, r, p, l) \
336 do { \
337 unsigned long _a = (unsigned long)((a) + (r)); \
338 int _l = (l); \
339 const u16 *_p = (const u16 *)(p); \
340 while (_l-- > 0) \
341 au_writew(*_p++ , _a); \
342 } while(0)
344 #define SMC_IRQ_FLAGS (0)
346 #elif defined(CONFIG_ARCH_VERSATILE)
348 #define SMC_CAN_USE_8BIT 1
349 #define SMC_CAN_USE_16BIT 1
350 #define SMC_CAN_USE_32BIT 1
351 #define SMC_NOWAIT 1
353 #define SMC_inb(a, r) readb((a) + (r))
354 #define SMC_inw(a, r) readw((a) + (r))
355 #define SMC_inl(a, r) readl((a) + (r))
356 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
357 #define SMC_outw(v, a, r) writew(v, (a) + (r))
358 #define SMC_outl(v, a, r) writel(v, (a) + (r))
359 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
360 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
362 #define SMC_IRQ_FLAGS (0)
364 #elif defined(CONFIG_ARCH_VERSATILE)
366 #define SMC_CAN_USE_8BIT 1
367 #define SMC_CAN_USE_16BIT 1
368 #define SMC_CAN_USE_32BIT 1
369 #define SMC_NOWAIT 1
371 #define SMC_inb(a, r) readb((a) + (r))
372 #define SMC_inw(a, r) readw((a) + (r))
373 #define SMC_inl(a, r) readl((a) + (r))
374 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
375 #define SMC_outw(v, a, r) writew(v, (a) + (r))
376 #define SMC_outl(v, a, r) writel(v, (a) + (r))
377 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
378 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
380 #define SMC_IRQ_FLAGS (0)
382 #else
384 #define SMC_CAN_USE_8BIT 1
385 #define SMC_CAN_USE_16BIT 1
386 #define SMC_CAN_USE_32BIT 1
387 #define SMC_NOWAIT 1
389 #define SMC_inb(a, r) readb((a) + (r))
390 #define SMC_inw(a, r) readw((a) + (r))
391 #define SMC_inl(a, r) readl((a) + (r))
392 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
393 #define SMC_outw(v, a, r) writew(v, (a) + (r))
394 #define SMC_outl(v, a, r) writel(v, (a) + (r))
395 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
396 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
398 #define RPC_LSA_DEFAULT RPC_LED_100_10
399 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
401 #endif
403 #ifdef SMC_USE_PXA_DMA
404 /*
405 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
406 * always happening in irq context so no need to worry about races. TX is
407 * different and probably not worth it for that reason, and not as critical
408 * as RX which can overrun memory and lose packets.
409 */
410 #include <linux/dma-mapping.h>
411 #include <asm/dma.h>
412 #include <asm/arch/pxa-regs.h>
414 #ifdef SMC_insl
415 #undef SMC_insl
416 #define SMC_insl(a, r, p, l) \
417 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
418 static inline void
419 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
420 u_char *buf, int len)
421 {
422 dma_addr_t dmabuf;
424 /* fallback if no DMA available */
425 if (dma == (unsigned char)-1) {
426 readsl(ioaddr + reg, buf, len);
427 return;
428 }
430 /* 64 bit alignment is required for memory to memory DMA */
431 if ((long)buf & 4) {
432 *((u32 *)buf) = SMC_inl(ioaddr, reg);
433 buf += 4;
434 len--;
435 }
437 len *= 4;
438 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
439 DCSR(dma) = DCSR_NODESC;
440 DTADR(dma) = dmabuf;
441 DSADR(dma) = physaddr + reg;
442 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
443 DCMD_WIDTH4 | (DCMD_LENGTH & len));
444 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
445 while (!(DCSR(dma) & DCSR_STOPSTATE))
446 cpu_relax();
447 DCSR(dma) = 0;
448 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
449 }
450 #endif
452 #ifdef SMC_insw
453 #undef SMC_insw
454 #define SMC_insw(a, r, p, l) \
455 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
456 static inline void
457 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
458 u_char *buf, int len)
459 {
460 dma_addr_t dmabuf;
462 /* fallback if no DMA available */
463 if (dma == (unsigned char)-1) {
464 readsw(ioaddr + reg, buf, len);
465 return;
466 }
468 /* 64 bit alignment is required for memory to memory DMA */
469 while ((long)buf & 6) {
470 *((u16 *)buf) = SMC_inw(ioaddr, reg);
471 buf += 2;
472 len--;
473 }
475 len *= 2;
476 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
477 DCSR(dma) = DCSR_NODESC;
478 DTADR(dma) = dmabuf;
479 DSADR(dma) = physaddr + reg;
480 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
481 DCMD_WIDTH2 | (DCMD_LENGTH & len));
482 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
483 while (!(DCSR(dma) & DCSR_STOPSTATE))
484 cpu_relax();
485 DCSR(dma) = 0;
486 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
487 }
488 #endif
490 static void
491 smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
492 {
493 DCSR(dma) = 0;
494 }
495 #endif /* SMC_USE_PXA_DMA */
498 /*
499 * Everything a particular hardware setup needs should have been defined
500 * at this point. Add stubs for the undefined cases, mainly to avoid
501 * compilation warnings since they'll be optimized away, or to prevent buggy
502 * use of them.
503 */
505 #if ! SMC_CAN_USE_32BIT
506 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
507 #define SMC_outl(x, ioaddr, reg) BUG()
508 #define SMC_insl(a, r, p, l) BUG()
509 #define SMC_outsl(a, r, p, l) BUG()
510 #endif
512 #if !defined(SMC_insl) || !defined(SMC_outsl)
513 #define SMC_insl(a, r, p, l) BUG()
514 #define SMC_outsl(a, r, p, l) BUG()
515 #endif
517 #if ! SMC_CAN_USE_16BIT
519 /*
520 * Any 16-bit access is performed with two 8-bit accesses if the hardware
521 * can't do it directly. Most registers are 16-bit so those are mandatory.
522 */
523 #define SMC_outw(x, ioaddr, reg) \
524 do { \
525 unsigned int __val16 = (x); \
526 SMC_outb( __val16, ioaddr, reg ); \
527 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
528 } while (0)
529 #define SMC_inw(ioaddr, reg) \
530 ({ \
531 unsigned int __val16; \
532 __val16 = SMC_inb( ioaddr, reg ); \
533 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
534 __val16; \
535 })
537 #define SMC_insw(a, r, p, l) BUG()
538 #define SMC_outsw(a, r, p, l) BUG()
540 #endif
542 #if !defined(SMC_insw) || !defined(SMC_outsw)
543 #define SMC_insw(a, r, p, l) BUG()
544 #define SMC_outsw(a, r, p, l) BUG()
545 #endif
547 #if ! SMC_CAN_USE_8BIT
548 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
549 #define SMC_outb(x, ioaddr, reg) BUG()
550 #define SMC_insb(a, r, p, l) BUG()
551 #define SMC_outsb(a, r, p, l) BUG()
552 #endif
554 #if !defined(SMC_insb) || !defined(SMC_outsb)
555 #define SMC_insb(a, r, p, l) BUG()
556 #define SMC_outsb(a, r, p, l) BUG()
557 #endif
559 #ifndef SMC_CAN_USE_DATACS
560 #define SMC_CAN_USE_DATACS 0
561 #endif
563 #ifndef SMC_IO_SHIFT
564 #define SMC_IO_SHIFT 0
565 #endif
567 #ifndef SMC_IRQ_FLAGS
568 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
569 #endif
571 #ifndef SMC_INTERRUPT_PREAMBLE
572 #define SMC_INTERRUPT_PREAMBLE
573 #endif
576 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
577 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
578 #define SMC_DATA_EXTENT (4)
580 /*
581 . Bank Select Register:
582 .
583 . yyyy yyyy 0000 00xx
584 . xx = bank number
585 . yyyy yyyy = 0x33, for identification purposes.
586 */
587 #define BANK_SELECT (14 << SMC_IO_SHIFT)
590 // Transmit Control Register
591 /* BANK 0 */
592 #define TCR_REG SMC_REG(0x0000, 0)
593 #define TCR_ENABLE 0x0001 // When 1 we can transmit
594 #define TCR_LOOP 0x0002 // Controls output pin LBK
595 #define TCR_FORCOL 0x0004 // When 1 will force a collision
596 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
597 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
598 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
599 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
600 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
601 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
602 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
604 #define TCR_CLEAR 0 /* do NOTHING */
605 /* the default settings for the TCR register : */
606 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
609 // EPH Status Register
610 /* BANK 0 */
611 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
612 #define ES_TX_SUC 0x0001 // Last TX was successful
613 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
614 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
615 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
616 #define ES_16COL 0x0010 // 16 Collisions Reached
617 #define ES_SQET 0x0020 // Signal Quality Error Test
618 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
619 #define ES_TXDEFR 0x0080 // Transmit Deferred
620 #define ES_LATCOL 0x0200 // Late collision detected on last tx
621 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
622 #define ES_EXC_DEF 0x0800 // Excessive Deferral
623 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
624 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
625 #define ES_TXUNRN 0x8000 // Tx Underrun
628 // Receive Control Register
629 /* BANK 0 */
630 #define RCR_REG SMC_REG(0x0004, 0)
631 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
632 #define RCR_PRMS 0x0002 // Enable promiscuous mode
633 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
634 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
635 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
636 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
637 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
638 #define RCR_SOFTRST 0x8000 // resets the chip
640 /* the normal settings for the RCR register : */
641 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
642 #define RCR_CLEAR 0x0 // set it to a base state
645 // Counter Register
646 /* BANK 0 */
647 #define COUNTER_REG SMC_REG(0x0006, 0)
650 // Memory Information Register
651 /* BANK 0 */
652 #define MIR_REG SMC_REG(0x0008, 0)
655 // Receive/Phy Control Register
656 /* BANK 0 */
657 #define RPC_REG SMC_REG(0x000A, 0)
658 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
659 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
660 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
661 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
662 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
663 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
664 #define RPC_LED_RES (0x01) // LED = Reserved
665 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
666 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
667 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
668 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
669 #define RPC_LED_TX (0x06) // LED = TX packet occurred
670 #define RPC_LED_RX (0x07) // LED = RX packet occurred
672 #ifndef RPC_LSA_DEFAULT
673 #define RPC_LSA_DEFAULT RPC_LED_100
674 #endif
675 #ifndef RPC_LSB_DEFAULT
676 #define RPC_LSB_DEFAULT RPC_LED_FD
677 #endif
679 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
682 /* Bank 0 0x0C is reserved */
684 // Bank Select Register
685 /* All Banks */
686 #define BSR_REG 0x000E
689 // Configuration Reg
690 /* BANK 1 */
691 #define CONFIG_REG SMC_REG(0x0000, 1)
692 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
693 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
694 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
695 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
697 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
698 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
701 // Base Address Register
702 /* BANK 1 */
703 #define BASE_REG SMC_REG(0x0002, 1)
706 // Individual Address Registers
707 /* BANK 1 */
708 #define ADDR0_REG SMC_REG(0x0004, 1)
709 #define ADDR1_REG SMC_REG(0x0006, 1)
710 #define ADDR2_REG SMC_REG(0x0008, 1)
713 // General Purpose Register
714 /* BANK 1 */
715 #define GP_REG SMC_REG(0x000A, 1)
718 // Control Register
719 /* BANK 1 */
720 #define CTL_REG SMC_REG(0x000C, 1)
721 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
722 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
723 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
724 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
725 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
726 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
727 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
728 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
731 // MMU Command Register
732 /* BANK 2 */
733 #define MMU_CMD_REG SMC_REG(0x0000, 2)
734 #define MC_BUSY 1 // When 1 the last release has not completed
735 #define MC_NOP (0<<5) // No Op
736 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
737 #define MC_RESET (2<<5) // Reset MMU to initial state
738 #define MC_REMOVE (3<<5) // Remove the current rx packet
739 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
740 #define MC_FREEPKT (5<<5) // Release packet in PNR register
741 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
742 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
745 // Packet Number Register
746 /* BANK 2 */
747 #define PN_REG SMC_REG(0x0002, 2)
750 // Allocation Result Register
751 /* BANK 2 */
752 #define AR_REG SMC_REG(0x0003, 2)
753 #define AR_FAILED 0x80 // Alocation Failed
756 // TX FIFO Ports Register
757 /* BANK 2 */
758 #define TXFIFO_REG SMC_REG(0x0004, 2)
759 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
761 // RX FIFO Ports Register
762 /* BANK 2 */
763 #define RXFIFO_REG SMC_REG(0x0005, 2)
764 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
766 #define FIFO_REG SMC_REG(0x0004, 2)
768 // Pointer Register
769 /* BANK 2 */
770 #define PTR_REG SMC_REG(0x0006, 2)
771 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
772 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
773 #define PTR_READ 0x2000 // When 1 the operation is a read
776 // Data Register
777 /* BANK 2 */
778 #define DATA_REG SMC_REG(0x0008, 2)
781 // Interrupt Status/Acknowledge Register
782 /* BANK 2 */
783 #define INT_REG SMC_REG(0x000C, 2)
786 // Interrupt Mask Register
787 /* BANK 2 */
788 #define IM_REG SMC_REG(0x000D, 2)
789 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
790 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
791 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
792 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
793 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
794 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
795 #define IM_TX_INT 0x02 // Transmit Interrupt
796 #define IM_RCV_INT 0x01 // Receive Interrupt
799 // Multicast Table Registers
800 /* BANK 3 */
801 #define MCAST_REG1 SMC_REG(0x0000, 3)
802 #define MCAST_REG2 SMC_REG(0x0002, 3)
803 #define MCAST_REG3 SMC_REG(0x0004, 3)
804 #define MCAST_REG4 SMC_REG(0x0006, 3)
807 // Management Interface Register (MII)
808 /* BANK 3 */
809 #define MII_REG SMC_REG(0x0008, 3)
810 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
811 #define MII_MDOE 0x0008 // MII Output Enable
812 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
813 #define MII_MDI 0x0002 // MII Input, pin MDI
814 #define MII_MDO 0x0001 // MII Output, pin MDO
817 // Revision Register
818 /* BANK 3 */
819 /* ( hi: chip id low: rev # ) */
820 #define REV_REG SMC_REG(0x000A, 3)
823 // Early RCV Register
824 /* BANK 3 */
825 /* this is NOT on SMC9192 */
826 #define ERCV_REG SMC_REG(0x000C, 3)
827 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
828 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
831 // External Register
832 /* BANK 7 */
833 #define EXT_REG SMC_REG(0x0000, 7)
836 #define CHIP_9192 3
837 #define CHIP_9194 4
838 #define CHIP_9195 5
839 #define CHIP_9196 6
840 #define CHIP_91100 7
841 #define CHIP_91100FD 8
842 #define CHIP_91111FD 9
844 static const char * chip_ids[ 16 ] = {
845 NULL, NULL, NULL,
846 /* 3 */ "SMC91C90/91C92",
847 /* 4 */ "SMC91C94",
848 /* 5 */ "SMC91C95",
849 /* 6 */ "SMC91C96",
850 /* 7 */ "SMC91C100",
851 /* 8 */ "SMC91C100FD",
852 /* 9 */ "SMC91C11xFD",
853 NULL, NULL, NULL,
854 NULL, NULL, NULL};
857 /*
858 . Receive status bits
859 */
860 #define RS_ALGNERR 0x8000
861 #define RS_BRODCAST 0x4000
862 #define RS_BADCRC 0x2000
863 #define RS_ODDFRAME 0x1000
864 #define RS_TOOLONG 0x0800
865 #define RS_TOOSHORT 0x0400
866 #define RS_MULTICAST 0x0001
867 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
870 /*
871 * PHY IDs
872 * LAN83C183 == LAN91C111 Internal PHY
873 */
874 #define PHY_LAN83C183 0x0016f840
875 #define PHY_LAN83C180 0x02821c50
877 /*
878 * PHY Register Addresses (LAN91C111 Internal PHY)
879 *
880 * Generic PHY registers can be found in <linux/mii.h>
881 *
882 * These phy registers are specific to our on-board phy.
883 */
885 // PHY Configuration Register 1
886 #define PHY_CFG1_REG 0x10
887 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
888 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
889 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
890 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
891 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
892 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
893 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
894 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
895 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
896 #define PHY_CFG1_TLVL_MASK 0x003C
897 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
900 // PHY Configuration Register 2
901 #define PHY_CFG2_REG 0x11
902 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
903 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
904 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
905 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
907 // PHY Status Output (and Interrupt status) Register
908 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
909 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
910 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
911 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
912 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
913 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
914 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
915 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
916 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
917 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
918 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
920 // PHY Interrupt/Status Mask Register
921 #define PHY_MASK_REG 0x13 // Interrupt Mask
922 // Uses the same bit definitions as PHY_INT_REG
925 /*
926 * SMC91C96 ethernet config and status registers.
927 * These are in the "attribute" space.
928 */
929 #define ECOR 0x8000
930 #define ECOR_RESET 0x80
931 #define ECOR_LEVEL_IRQ 0x40
932 #define ECOR_WR_ATTRIB 0x04
933 #define ECOR_ENABLE 0x01
935 #define ECSR 0x8002
936 #define ECSR_IOIS8 0x20
937 #define ECSR_PWRDWN 0x04
938 #define ECSR_INT 0x02
940 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
943 /*
944 * Macros to abstract register access according to the data bus
945 * capabilities. Please use those and not the in/out primitives.
946 * Note: the following macros do *not* select the bank -- this must
947 * be done separately as needed in the main code. The SMC_REG() macro
948 * only uses the bank argument for debugging purposes (when enabled).
949 *
950 * Note: despite inline functions being safer, everything leading to this
951 * should preferably be macros to let BUG() display the line number in
952 * the core source code since we're interested in the top call site
953 * not in any inline function location.
954 */
956 #if SMC_DEBUG > 0
957 #define SMC_REG(reg, bank) \
958 ({ \
959 int __b = SMC_CURRENT_BANK(); \
960 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
961 printk( "%s: bank reg screwed (0x%04x)\n", \
962 CARDNAME, __b ); \
963 BUG(); \
964 } \
965 reg<<SMC_IO_SHIFT; \
966 })
967 #else
968 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
969 #endif
971 /*
972 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
973 * aligned to a 32 bit boundary. I tell you that does exist!
974 * Fortunately the affected register accesses can be easily worked around
975 * since we can write zeroes to the preceeding 16 bits without adverse
976 * effects and use a 32-bit access.
977 *
978 * Enforce it on any 32-bit capable setup for now.
979 */
980 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
982 #define SMC_GET_PN() \
983 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
984 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
986 #define SMC_SET_PN(x) \
987 do { \
988 if (SMC_MUST_ALIGN_WRITE) \
989 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
990 else if (SMC_CAN_USE_8BIT) \
991 SMC_outb(x, ioaddr, PN_REG); \
992 else \
993 SMC_outw(x, ioaddr, PN_REG); \
994 } while (0)
996 #define SMC_GET_AR() \
997 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
998 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1000 #define SMC_GET_TXFIFO() \
1001 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1002 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1004 #define SMC_GET_RXFIFO() \
1005 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1006 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1008 #define SMC_GET_INT() \
1009 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1010 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1012 #define SMC_ACK_INT(x) \
1013 do { \
1014 if (SMC_CAN_USE_8BIT) \
1015 SMC_outb(x, ioaddr, INT_REG); \
1016 else { \
1017 unsigned long __flags; \
1018 int __mask; \
1019 local_irq_save(__flags); \
1020 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1021 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1022 local_irq_restore(__flags); \
1023 } \
1024 } while (0)
1026 #define SMC_GET_INT_MASK() \
1027 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1028 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1030 #define SMC_SET_INT_MASK(x) \
1031 do { \
1032 if (SMC_CAN_USE_8BIT) \
1033 SMC_outb(x, ioaddr, IM_REG); \
1034 else \
1035 SMC_outw((x) << 8, ioaddr, INT_REG); \
1036 } while (0)
1038 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1040 #define SMC_SELECT_BANK(x) \
1041 do { \
1042 if (SMC_MUST_ALIGN_WRITE) \
1043 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1044 else \
1045 SMC_outw(x, ioaddr, BANK_SELECT); \
1046 } while (0)
1048 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1050 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1052 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1054 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1056 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1058 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1060 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1062 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1064 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1066 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1068 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1070 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1072 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1074 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1076 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1078 #define SMC_SET_PTR(x) \
1079 do { \
1080 if (SMC_MUST_ALIGN_WRITE) \
1081 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1082 else \
1083 SMC_outw(x, ioaddr, PTR_REG); \
1084 } while (0)
1086 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1088 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1090 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1092 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1094 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1096 #define SMC_SET_RPC(x) \
1097 do { \
1098 if (SMC_MUST_ALIGN_WRITE) \
1099 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1100 else \
1101 SMC_outw(x, ioaddr, RPC_REG); \
1102 } while (0)
1104 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1106 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1108 #ifndef SMC_GET_MAC_ADDR
1109 #define SMC_GET_MAC_ADDR(addr) \
1110 do { \
1111 unsigned int __v; \
1112 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1113 addr[0] = __v; addr[1] = __v >> 8; \
1114 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1115 addr[2] = __v; addr[3] = __v >> 8; \
1116 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1117 addr[4] = __v; addr[5] = __v >> 8; \
1118 } while (0)
1119 #endif
1121 #define SMC_SET_MAC_ADDR(addr) \
1122 do { \
1123 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1124 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1125 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1126 } while (0)
1128 #define SMC_SET_MCAST(x) \
1129 do { \
1130 const unsigned char *mt = (x); \
1131 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1132 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1133 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1134 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1135 } while (0)
1137 #define SMC_PUT_PKT_HDR(status, length) \
1138 do { \
1139 if (SMC_CAN_USE_32BIT) \
1140 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1141 else { \
1142 SMC_outw(status, ioaddr, DATA_REG); \
1143 SMC_outw(length, ioaddr, DATA_REG); \
1144 } \
1145 } while (0)
1147 #define SMC_GET_PKT_HDR(status, length) \
1148 do { \
1149 if (SMC_CAN_USE_32BIT) { \
1150 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1151 (status) = __val & 0xffff; \
1152 (length) = __val >> 16; \
1153 } else { \
1154 (status) = SMC_inw(ioaddr, DATA_REG); \
1155 (length) = SMC_inw(ioaddr, DATA_REG); \
1156 } \
1157 } while (0)
1159 #define SMC_PUSH_DATA(p, l) \
1160 do { \
1161 if (SMC_CAN_USE_32BIT) { \
1162 void *__ptr = (p); \
1163 int __len = (l); \
1164 void *__ioaddr = ioaddr; \
1165 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1166 __len -= 2; \
1167 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1168 __ptr += 2; \
1169 } \
1170 if (SMC_CAN_USE_DATACS && lp->datacs) \
1171 __ioaddr = lp->datacs; \
1172 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1173 if (__len & 2) { \
1174 __ptr += (__len & ~3); \
1175 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1176 } \
1177 } else if (SMC_CAN_USE_16BIT) \
1178 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1179 else if (SMC_CAN_USE_8BIT) \
1180 SMC_outsb(ioaddr, DATA_REG, p, l); \
1181 } while (0)
1183 #define SMC_PULL_DATA(p, l) \
1184 do { \
1185 if (SMC_CAN_USE_32BIT) { \
1186 void *__ptr = (p); \
1187 int __len = (l); \
1188 void *__ioaddr = ioaddr; \
1189 if ((unsigned long)__ptr & 2) { \
1190 /* \
1191 * We want 32bit alignment here. \
1192 * Since some buses perform a full \
1193 * 32bit fetch even for 16bit data \
1194 * we can't use SMC_inw() here. \
1195 * Back both source (on-chip) and \
1196 * destination pointers of 2 bytes. \
1197 * This is possible since the call to \
1198 * SMC_GET_PKT_HDR() already advanced \
1199 * the source pointer of 4 bytes, and \
1200 * the skb_reserve(skb, 2) advanced \
1201 * the destination pointer of 2 bytes. \
1202 */ \
1203 __ptr -= 2; \
1204 __len += 2; \
1205 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1206 } \
1207 if (SMC_CAN_USE_DATACS && lp->datacs) \
1208 __ioaddr = lp->datacs; \
1209 __len += 2; \
1210 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1211 } else if (SMC_CAN_USE_16BIT) \
1212 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1213 else if (SMC_CAN_USE_8BIT) \
1214 SMC_insb(ioaddr, DATA_REG, p, l); \
1215 } while (0)
1217 #endif /* _SMC91X_H_ */