ia64/linux-2.6.18-xen.hg

view drivers/net/smc911x.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <dustin@sensoria.com>
27 .
28 ---------------------------------------------------------------------------*/
29 #ifndef _SMC911X_H_
30 #define _SMC911X_H_
32 /*
33 * Use the DMA feature on PXA chips
34 */
35 #ifdef CONFIG_ARCH_PXA
36 #define SMC_USE_PXA_DMA 1
37 #define SMC_USE_16BIT 0
38 #define SMC_USE_32BIT 1
39 #endif
42 /*
43 * Define the bus width specific IO macros
44 */
46 #if SMC_USE_16BIT
47 #define SMC_inb(a, r) readb((a) + (r))
48 #define SMC_inw(a, r) readw((a) + (r))
49 #define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
50 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
51 #define SMC_outw(v, a, r) writew(v, (a) + (r))
52 #define SMC_outl(v, a, r) \
53 do{ \
54 writel(v & 0xFFFF, (a) + (r)); \
55 writel(v >> 16, (a) + (r) + 2); \
56 } while (0)
57 #define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2)
58 #define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2)
60 #elif SMC_USE_32BIT
61 #define SMC_inb(a, r) readb((a) + (r))
62 #define SMC_inw(a, r) readw((a) + (r))
63 #define SMC_inl(a, r) readl((a) + (r))
64 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
65 #define SMC_outl(v, a, r) writel(v, (a) + (r))
66 #define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
67 #define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
69 #endif /* SMC_USE_16BIT */
73 #if SMC_USE_PXA_DMA
74 #define SMC_USE_DMA
76 /*
77 * Define the request and free functions
78 * These are unfortunately architecture specific as no generic allocation
79 * mechanism exits
80 */
81 #define SMC_DMA_REQUEST(dev, handler) \
82 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
84 #define SMC_DMA_FREE(dev, dma) \
85 pxa_free_dma(dma)
87 #define SMC_DMA_ACK_IRQ(dev, dma) \
88 { \
89 if (DCSR(dma) & DCSR_BUSERR) { \
90 printk("%s: DMA %d bus error!\n", dev->name, dma); \
91 } \
92 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
93 }
95 /*
96 * Use a DMA for RX and TX packets.
97 */
98 #include <linux/dma-mapping.h>
99 #include <asm/dma.h>
100 #include <asm/arch/pxa-regs.h>
102 static dma_addr_t rx_dmabuf, tx_dmabuf;
103 static int rx_dmalen, tx_dmalen;
105 #ifdef SMC_insl
106 #undef SMC_insl
107 #define SMC_insl(a, r, p, l) \
108 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
110 static inline void
111 smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
112 int reg, int dma, u_char *buf, int len)
113 {
114 /* 64 bit alignment is required for memory to memory DMA */
115 if ((long)buf & 4) {
116 *((u32 *)buf) = SMC_inl(ioaddr, reg);
117 buf += 4;
118 len--;
119 }
121 len *= 4;
122 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
123 rx_dmalen = len;
124 DCSR(dma) = DCSR_NODESC;
125 DTADR(dma) = rx_dmabuf;
126 DSADR(dma) = physaddr + reg;
127 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
128 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
129 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
130 }
131 #endif
133 #ifdef SMC_insw
134 #undef SMC_insw
135 #define SMC_insw(a, r, p, l) \
136 smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
138 static inline void
139 smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
140 int reg, int dma, u_char *buf, int len)
141 {
142 /* 64 bit alignment is required for memory to memory DMA */
143 while ((long)buf & 6) {
144 *((u16 *)buf) = SMC_inw(ioaddr, reg);
145 buf += 2;
146 len--;
147 }
149 len *= 2;
150 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
151 rx_dmalen = len;
152 DCSR(dma) = DCSR_NODESC;
153 DTADR(dma) = rx_dmabuf;
154 DSADR(dma) = physaddr + reg;
155 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
156 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
157 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
158 }
159 #endif
161 #ifdef SMC_outsl
162 #undef SMC_outsl
163 #define SMC_outsl(a, r, p, l) \
164 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
166 static inline void
167 smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
168 int reg, int dma, u_char *buf, int len)
169 {
170 /* 64 bit alignment is required for memory to memory DMA */
171 if ((long)buf & 4) {
172 SMC_outl(*((u32 *)buf), ioaddr, reg);
173 buf += 4;
174 len--;
175 }
177 len *= 4;
178 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
179 tx_dmalen = len;
180 DCSR(dma) = DCSR_NODESC;
181 DSADR(dma) = tx_dmabuf;
182 DTADR(dma) = physaddr + reg;
183 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
184 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
185 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
186 }
187 #endif
189 #ifdef SMC_outsw
190 #undef SMC_outsw
191 #define SMC_outsw(a, r, p, l) \
192 smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
194 static inline void
195 smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
196 int reg, int dma, u_char *buf, int len)
197 {
198 /* 64 bit alignment is required for memory to memory DMA */
199 while ((long)buf & 6) {
200 SMC_outw(*((u16 *)buf), ioaddr, reg);
201 buf += 2;
202 len--;
203 }
205 len *= 2;
206 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
207 tx_dmalen = len;
208 DCSR(dma) = DCSR_NODESC;
209 DSADR(dma) = tx_dmabuf;
210 DTADR(dma) = physaddr + reg;
211 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
212 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
213 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
214 }
215 #endif
217 #endif /* SMC_USE_PXA_DMA */
220 /* Chip Parameters and Register Definitions */
222 #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
224 #define SMC911X_IO_EXTENT 0x100
226 #define SMC911X_EEPROM_LEN 7
228 /* Below are the register offsets and bit definitions
229 * of the Lan911x memory space
230 */
231 #define RX_DATA_FIFO (0x00)
233 #define TX_DATA_FIFO (0x20)
234 #define TX_CMD_A_INT_ON_COMP_ (0x80000000)
235 #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
236 #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
237 #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
238 #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
239 #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
240 #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
241 #define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
242 #define TX_CMD_A_BUF_SIZE_ (0x000007FF)
243 #define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
244 #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
245 #define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
246 #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
248 #define RX_STATUS_FIFO (0x40)
249 #define RX_STS_PKT_LEN_ (0x3FFF0000)
250 #define RX_STS_ES_ (0x00008000)
251 #define RX_STS_BCST_ (0x00002000)
252 #define RX_STS_LEN_ERR_ (0x00001000)
253 #define RX_STS_RUNT_ERR_ (0x00000800)
254 #define RX_STS_MCAST_ (0x00000400)
255 #define RX_STS_TOO_LONG_ (0x00000080)
256 #define RX_STS_COLL_ (0x00000040)
257 #define RX_STS_ETH_TYPE_ (0x00000020)
258 #define RX_STS_WDOG_TMT_ (0x00000010)
259 #define RX_STS_MII_ERR_ (0x00000008)
260 #define RX_STS_DRIBBLING_ (0x00000004)
261 #define RX_STS_CRC_ERR_ (0x00000002)
262 #define RX_STATUS_FIFO_PEEK (0x44)
263 #define TX_STATUS_FIFO (0x48)
264 #define TX_STS_TAG_ (0xFFFF0000)
265 #define TX_STS_ES_ (0x00008000)
266 #define TX_STS_LOC_ (0x00000800)
267 #define TX_STS_NO_CARR_ (0x00000400)
268 #define TX_STS_LATE_COLL_ (0x00000200)
269 #define TX_STS_MANY_COLL_ (0x00000100)
270 #define TX_STS_COLL_CNT_ (0x00000078)
271 #define TX_STS_MANY_DEFER_ (0x00000004)
272 #define TX_STS_UNDERRUN_ (0x00000002)
273 #define TX_STS_DEFERRED_ (0x00000001)
274 #define TX_STATUS_FIFO_PEEK (0x4C)
275 #define ID_REV (0x50)
276 #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
277 #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
279 #define INT_CFG (0x54)
280 #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
281 #define INT_CFG_INT_DEAS_CLR_ (0x00004000)
282 #define INT_CFG_INT_DEAS_STS_ (0x00002000)
283 #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
284 #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
285 #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
286 #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
288 #define INT_STS (0x58)
289 #define INT_STS_SW_INT_ (0x80000000) /* R/WC */
290 #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
291 #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
292 #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
293 #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
294 #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
295 #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
296 #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
297 #define INT_STS_PHY_INT_ (0x00040000) /* RO */
298 #define INT_STS_PME_INT_ (0x00020000) /* R/WC */
299 #define INT_STS_TXSO_ (0x00010000) /* R/WC */
300 #define INT_STS_RWT_ (0x00008000) /* R/WC */
301 #define INT_STS_RXE_ (0x00004000) /* R/WC */
302 #define INT_STS_TXE_ (0x00002000) /* R/WC */
303 //#define INT_STS_ERX_ (0x00001000) /* R/WC */
304 #define INT_STS_TDFU_ (0x00000800) /* R/WC */
305 #define INT_STS_TDFO_ (0x00000400) /* R/WC */
306 #define INT_STS_TDFA_ (0x00000200) /* R/WC */
307 #define INT_STS_TSFF_ (0x00000100) /* R/WC */
308 #define INT_STS_TSFL_ (0x00000080) /* R/WC */
309 //#define INT_STS_RXDF_ (0x00000040) /* R/WC */
310 #define INT_STS_RDFO_ (0x00000040) /* R/WC */
311 #define INT_STS_RDFL_ (0x00000020) /* R/WC */
312 #define INT_STS_RSFF_ (0x00000010) /* R/WC */
313 #define INT_STS_RSFL_ (0x00000008) /* R/WC */
314 #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
315 #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
316 #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
318 #define INT_EN (0x5C)
319 #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
320 #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
321 #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
322 #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
323 //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
324 #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
325 #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
326 #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
327 #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
328 #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
329 #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
330 #define INT_EN_RWT_EN_ (0x00008000) /* R/W */
331 #define INT_EN_RXE_EN_ (0x00004000) /* R/W */
332 #define INT_EN_TXE_EN_ (0x00002000) /* R/W */
333 //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
334 #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
335 #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
336 #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
337 #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
338 #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
339 //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
340 #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
341 #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
342 #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
343 #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
344 #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
345 #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
346 #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
348 #define BYTE_TEST (0x64)
349 #define FIFO_INT (0x68)
350 #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
351 #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
352 #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
353 #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
355 #define RX_CFG (0x6C)
356 #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
357 #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
358 #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
359 #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
360 #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
361 #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
362 #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
363 //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
365 #define TX_CFG (0x70)
366 //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
367 //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
368 #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
369 #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
370 #define TX_CFG_TXSAO_ (0x00000004) /* R/W */
371 #define TX_CFG_TX_ON_ (0x00000002) /* R/W */
372 #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
374 #define HW_CFG (0x74)
375 #define HW_CFG_TTM_ (0x00200000) /* R/W */
376 #define HW_CFG_SF_ (0x00100000) /* R/W */
377 #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
378 #define HW_CFG_TR_ (0x00003000) /* R/W */
379 #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
380 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
381 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
382 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
383 #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
384 #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
385 #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
386 #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
387 #define HW_CFG_SRST_TO_ (0x00000002) /* RO */
388 #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
390 #define RX_DP_CTRL (0x78)
391 #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
392 #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
394 #define RX_FIFO_INF (0x7C)
395 #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
396 #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
398 #define TX_FIFO_INF (0x80)
399 #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
400 #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
402 #define PMT_CTRL (0x84)
403 #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
404 #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
405 #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
406 #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
407 #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
408 #define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
409 #define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
410 #define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
411 #define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
412 #define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
413 #define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
414 #define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
415 #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
416 #define PMT_CTRL_READY_ (0x00000001) /* RO */
418 #define GPIO_CFG (0x88)
419 #define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
420 #define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
421 #define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
422 #define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
423 #define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
424 #define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
425 #define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
426 #define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
427 #define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
428 #define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
429 #define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
430 #define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
431 #define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
432 #define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
433 #define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
434 #define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
435 #define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
436 #define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
438 #define GPT_CFG (0x8C)
439 #define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
440 #define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
442 #define GPT_CNT (0x90)
443 #define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
445 #define ENDIAN (0x98)
446 #define FREE_RUN (0x9C)
447 #define RX_DROP (0xA0)
448 #define MAC_CSR_CMD (0xA4)
449 #define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
450 #define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
451 #define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
453 #define MAC_CSR_DATA (0xA8)
454 #define AFC_CFG (0xAC)
455 #define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
456 #define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
457 #define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
458 #define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
459 #define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
460 #define AFC_CFG_FCADD_ (0x00000002) /* R/W */
461 #define AFC_CFG_FCANY_ (0x00000001) /* R/W */
463 #define E2P_CMD (0xB0)
464 #define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
465 #define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
466 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
467 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
468 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
469 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
470 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
471 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
472 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
473 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
474 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
475 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
476 #define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
478 #define E2P_DATA (0xB4)
479 #define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
480 /* end of LAN register offsets and bit definitions */
482 /*
483 ****************************************************************************
484 ****************************************************************************
485 * MAC Control and Status Register (Indirect Address)
486 * Offset (through the MAC_CSR CMD and DATA port)
487 ****************************************************************************
488 ****************************************************************************
489 *
490 */
491 #define MAC_CR (0x01) /* R/W */
493 /* MAC_CR - MAC Control Register */
494 #define MAC_CR_RXALL_ (0x80000000)
495 // TODO: delete this bit? It is not described in the data sheet.
496 #define MAC_CR_HBDIS_ (0x10000000)
497 #define MAC_CR_RCVOWN_ (0x00800000)
498 #define MAC_CR_LOOPBK_ (0x00200000)
499 #define MAC_CR_FDPX_ (0x00100000)
500 #define MAC_CR_MCPAS_ (0x00080000)
501 #define MAC_CR_PRMS_ (0x00040000)
502 #define MAC_CR_INVFILT_ (0x00020000)
503 #define MAC_CR_PASSBAD_ (0x00010000)
504 #define MAC_CR_HFILT_ (0x00008000)
505 #define MAC_CR_HPFILT_ (0x00002000)
506 #define MAC_CR_LCOLL_ (0x00001000)
507 #define MAC_CR_BCAST_ (0x00000800)
508 #define MAC_CR_DISRTY_ (0x00000400)
509 #define MAC_CR_PADSTR_ (0x00000100)
510 #define MAC_CR_BOLMT_MASK_ (0x000000C0)
511 #define MAC_CR_DFCHK_ (0x00000020)
512 #define MAC_CR_TXEN_ (0x00000008)
513 #define MAC_CR_RXEN_ (0x00000004)
515 #define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
516 #define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
517 #define HASHH (0x04) /* R/W */
518 #define HASHL (0x05) /* R/W */
520 #define MII_ACC (0x06) /* R/W */
521 #define MII_ACC_PHY_ADDR_ (0x0000F800)
522 #define MII_ACC_MIIRINDA_ (0x000007C0)
523 #define MII_ACC_MII_WRITE_ (0x00000002)
524 #define MII_ACC_MII_BUSY_ (0x00000001)
526 #define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
528 #define FLOW (0x08) /* R/W */
529 #define FLOW_FCPT_ (0xFFFF0000)
530 #define FLOW_FCPASS_ (0x00000004)
531 #define FLOW_FCEN_ (0x00000002)
532 #define FLOW_FCBSY_ (0x00000001)
534 #define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
535 #define VLAN1_VTI1_ (0x0000ffff)
537 #define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
538 #define VLAN2_VTI2_ (0x0000ffff)
540 #define WUFF (0x0B) /* WO */
542 #define WUCSR (0x0C) /* R/W */
543 #define WUCSR_GUE_ (0x00000200)
544 #define WUCSR_WUFR_ (0x00000040)
545 #define WUCSR_MPR_ (0x00000020)
546 #define WUCSR_WAKE_EN_ (0x00000004)
547 #define WUCSR_MPEN_ (0x00000002)
549 /*
550 ****************************************************************************
551 * Chip Specific MII Defines
552 ****************************************************************************
553 *
554 * Phy register offsets and bit definitions
555 *
556 */
558 #define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
559 //#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
560 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
561 //#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
562 //#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
563 //#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
564 //#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
565 //#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
566 //#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
567 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
568 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
570 #define PHY_INT_SRC ((u32)29)
571 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
572 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
573 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
574 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
575 #define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
576 #define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
577 #define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
579 #define PHY_INT_MASK ((u32)30)
580 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
581 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
582 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
583 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
584 #define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
585 #define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
586 #define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
588 #define PHY_SPECIAL ((u32)31)
589 #define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
590 #define PHY_SPECIAL_RES_ ((u16)0x0040)
591 #define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
592 #define PHY_SPECIAL_SPD_ ((u16)0x001C)
593 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
594 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
595 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
596 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
598 #define LAN911X_INTERNAL_PHY_ID (0x0007C000)
600 /* Chip ID values */
601 #define CHIP_9115 0x115
602 #define CHIP_9116 0x116
603 #define CHIP_9117 0x117
604 #define CHIP_9118 0x118
606 struct chip_id {
607 u16 id;
608 char *name;
609 };
611 static const struct chip_id chip_ids[] = {
612 { CHIP_9115, "LAN9115" },
613 { CHIP_9116, "LAN9116" },
614 { CHIP_9117, "LAN9117" },
615 { CHIP_9118, "LAN9118" },
616 { 0, NULL },
617 };
619 #define IS_REV_A(x) ((x & 0xFFFF)==0)
621 /*
622 * Macros to abstract register access according to the data bus
623 * capabilities. Please use those and not the in/out primitives.
624 */
625 /* FIFO read/write macros */
626 #define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
627 #define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
628 #define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )
629 #define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )
632 /* I/O mapped register read/write macros */
633 #define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )
634 #define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )
635 #define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
636 #define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)
637 #define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
638 #define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )
639 #define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )
640 #define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )
641 #define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )
642 #define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )
643 #define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )
644 #define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )
645 #define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )
646 #define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )
647 #define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )
648 #define SMC_SET_FIFO_TDA(x) \
649 do { \
650 unsigned long __flags; \
651 int __mask; \
652 local_irq_save(__flags); \
653 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \
654 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \
655 local_irq_restore(__flags); \
656 } while (0)
657 #define SMC_SET_FIFO_TSL(x) \
658 do { \
659 unsigned long __flags; \
660 int __mask; \
661 local_irq_save(__flags); \
662 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \
663 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
664 local_irq_restore(__flags); \
665 } while (0)
666 #define SMC_SET_FIFO_RSA(x) \
667 do { \
668 unsigned long __flags; \
669 int __mask; \
670 local_irq_save(__flags); \
671 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \
672 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \
673 local_irq_restore(__flags); \
674 } while (0)
675 #define SMC_SET_FIFO_RSL(x) \
676 do { \
677 unsigned long __flags; \
678 int __mask; \
679 local_irq_save(__flags); \
680 __mask = SMC_GET_FIFO_INT() & ~0xFF; \
681 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \
682 local_irq_restore(__flags); \
683 } while (0)
684 #define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )
685 #define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )
686 #define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )
687 #define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )
688 #define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )
689 #define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )
690 #define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )
691 #define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )
692 #define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )
693 #define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )
694 #define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )
695 #define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )
696 #define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )
697 #define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )
698 #define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )
699 #define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )
700 #define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )
701 #define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )
702 #define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )
703 #define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )
704 #define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )
705 #define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )
706 #define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )
707 #define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )
708 #define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )
709 #define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )
710 #define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )
711 #define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )
712 #define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )
713 #define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )
715 /* MAC register read/write macros */
716 #define SMC_GET_MAC_CSR(a,v) \
717 do { \
718 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
719 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \
720 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
721 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
722 v = SMC_GET_MAC_DATA(); \
723 } while (0)
724 #define SMC_SET_MAC_CSR(a,v) \
725 do { \
726 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
727 SMC_SET_MAC_DATA(v); \
728 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
729 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
730 } while (0)
731 #define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )
732 #define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )
733 #define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )
734 #define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )
735 #define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )
736 #define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )
737 #define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )
738 #define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )
739 #define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )
740 #define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )
741 #define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )
742 #define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )
743 #define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )
744 #define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )
745 #define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )
746 #define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )
747 #define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )
748 #define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )
749 #define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )
750 #define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )
751 #define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )
752 #define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )
753 #define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )
755 /* PHY register read/write macros */
756 #define SMC_GET_MII(a,phy,v) \
757 do { \
758 u32 __v; \
759 do { \
760 SMC_GET_MII_ACC(__v); \
761 } while ( __v & MII_ACC_MII_BUSY_ ); \
762 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
763 MII_ACC_MII_BUSY_); \
764 do { \
765 SMC_GET_MII_ACC(__v); \
766 } while ( __v & MII_ACC_MII_BUSY_ ); \
767 SMC_GET_MII_DATA(v); \
768 } while (0)
769 #define SMC_SET_MII(a,phy,v) \
770 do { \
771 u32 __v; \
772 do { \
773 SMC_GET_MII_ACC(__v); \
774 } while ( __v & MII_ACC_MII_BUSY_ ); \
775 SMC_SET_MII_DATA(v); \
776 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
777 MII_ACC_MII_BUSY_ | \
778 MII_ACC_MII_WRITE_ ); \
779 do { \
780 SMC_GET_MII_ACC(__v); \
781 } while ( __v & MII_ACC_MII_BUSY_ ); \
782 } while (0)
783 #define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )
784 #define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )
785 #define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )
786 #define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )
787 #define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )
788 #define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )
789 #define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )
790 #define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )
791 #define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )
792 #define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
793 #define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
794 #define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )
795 #define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )
796 #define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )
797 #define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )
798 #define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )
802 /* Misc read/write macros */
804 #ifndef SMC_GET_MAC_ADDR
805 #define SMC_GET_MAC_ADDR(addr) \
806 do { \
807 unsigned int __v; \
808 \
809 SMC_GET_MAC_CSR(ADDRL, __v); \
810 addr[0] = __v; addr[1] = __v >> 8; \
811 addr[2] = __v >> 16; addr[3] = __v >> 24; \
812 SMC_GET_MAC_CSR(ADDRH, __v); \
813 addr[4] = __v; addr[5] = __v >> 8; \
814 } while (0)
815 #endif
817 #define SMC_SET_MAC_ADDR(addr) \
818 do { \
819 SMC_SET_MAC_CSR(ADDRL, \
820 addr[0] | \
821 (addr[1] << 8) | \
822 (addr[2] << 16) | \
823 (addr[3] << 24)); \
824 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
825 } while (0)
828 #define SMC_WRITE_EEPROM_CMD(cmd, addr) \
829 do { \
830 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
831 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \
832 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
833 } while (0)
835 #endif /* _SMC911X_H_ */