ia64/linux-2.6.18-xen.hg

view drivers/net/sky2.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 3e8752eb6d9c
children
line source
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
7 /* PCI config registers */
8 enum {
9 PCI_DEV_REG1 = 0x40,
10 PCI_DEV_REG2 = 0x44,
11 PCI_DEV_STATUS = 0x7c,
12 PCI_DEV_REG3 = 0x80,
13 PCI_DEV_REG4 = 0x84,
14 PCI_DEV_REG5 = 0x88,
15 };
17 enum {
18 PEX_DEV_CAP = 0xe4,
19 PEX_DEV_CTRL = 0xe8,
20 PEX_DEV_STA = 0xea,
21 PEX_LNK_STAT = 0xf2,
22 PEX_UNC_ERR_STAT= 0x104,
23 };
25 /* Yukon-2 */
26 enum pci_dev_reg_1 {
27 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
28 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
29 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
30 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
31 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
32 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
33 };
35 enum pci_dev_reg_2 {
36 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
37 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
38 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
40 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
41 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
42 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
43 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
45 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
46 };
48 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
49 enum pci_dev_reg_4 {
50 /* (Link Training & Status State Machine) */
51 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
52 /* (Active State Power Management) */
53 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
54 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
55 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
56 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
58 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
59 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
60 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
61 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
62 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
63 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
64 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
65 };
68 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
69 PCI_STATUS_SIG_SYSTEM_ERROR | \
70 PCI_STATUS_REC_MASTER_ABORT | \
71 PCI_STATUS_REC_TARGET_ABORT | \
72 PCI_STATUS_PARITY)
74 enum pex_dev_ctrl {
75 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
76 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
77 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
78 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
79 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
80 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
81 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
82 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
83 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
84 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
85 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
86 };
87 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
89 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
90 enum pex_err {
91 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
93 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
95 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
97 PEX_COMP_TO = 1<<14, /* Completion Timeout */
98 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
99 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
101 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
102 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
103 };
106 enum csr_regs {
107 B0_RAP = 0x0000,
108 B0_CTST = 0x0004,
109 B0_Y2LED = 0x0005,
110 B0_POWER_CTRL = 0x0007,
111 B0_ISRC = 0x0008,
112 B0_IMSK = 0x000c,
113 B0_HWE_ISRC = 0x0010,
114 B0_HWE_IMSK = 0x0014,
116 /* Special ISR registers (Yukon-2 only) */
117 B0_Y2_SP_ISRC2 = 0x001c,
118 B0_Y2_SP_ISRC3 = 0x0020,
119 B0_Y2_SP_EISR = 0x0024,
120 B0_Y2_SP_LISR = 0x0028,
121 B0_Y2_SP_ICR = 0x002c,
123 B2_MAC_1 = 0x0100,
124 B2_MAC_2 = 0x0108,
125 B2_MAC_3 = 0x0110,
126 B2_CONN_TYP = 0x0118,
127 B2_PMD_TYP = 0x0119,
128 B2_MAC_CFG = 0x011a,
129 B2_CHIP_ID = 0x011b,
130 B2_E_0 = 0x011c,
132 B2_Y2_CLK_GATE = 0x011d,
133 B2_Y2_HW_RES = 0x011e,
134 B2_E_3 = 0x011f,
135 B2_Y2_CLK_CTRL = 0x0120,
137 B2_TI_INI = 0x0130,
138 B2_TI_VAL = 0x0134,
139 B2_TI_CTRL = 0x0138,
140 B2_TI_TEST = 0x0139,
142 B2_TST_CTRL1 = 0x0158,
143 B2_TST_CTRL2 = 0x0159,
144 B2_GP_IO = 0x015c,
146 B2_I2C_CTRL = 0x0160,
147 B2_I2C_DATA = 0x0164,
148 B2_I2C_IRQ = 0x0168,
149 B2_I2C_SW = 0x016c,
151 B3_RAM_ADDR = 0x0180,
152 B3_RAM_DATA_LO = 0x0184,
153 B3_RAM_DATA_HI = 0x0188,
155 /* RAM Interface Registers */
156 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
157 /*
158 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
159 * not usable in SW. Please notice these are NOT real timeouts, these are
160 * the number of qWords transferred continuously.
161 */
162 #define RAM_BUFFER(port, reg) (reg | (port <<6))
164 B3_RI_WTO_R1 = 0x0190,
165 B3_RI_WTO_XA1 = 0x0191,
166 B3_RI_WTO_XS1 = 0x0192,
167 B3_RI_RTO_R1 = 0x0193,
168 B3_RI_RTO_XA1 = 0x0194,
169 B3_RI_RTO_XS1 = 0x0195,
170 B3_RI_WTO_R2 = 0x0196,
171 B3_RI_WTO_XA2 = 0x0197,
172 B3_RI_WTO_XS2 = 0x0198,
173 B3_RI_RTO_R2 = 0x0199,
174 B3_RI_RTO_XA2 = 0x019a,
175 B3_RI_RTO_XS2 = 0x019b,
176 B3_RI_TO_VAL = 0x019c,
177 B3_RI_CTRL = 0x01a0,
178 B3_RI_TEST = 0x01a2,
179 B3_MA_TOINI_RX1 = 0x01b0,
180 B3_MA_TOINI_RX2 = 0x01b1,
181 B3_MA_TOINI_TX1 = 0x01b2,
182 B3_MA_TOINI_TX2 = 0x01b3,
183 B3_MA_TOVAL_RX1 = 0x01b4,
184 B3_MA_TOVAL_RX2 = 0x01b5,
185 B3_MA_TOVAL_TX1 = 0x01b6,
186 B3_MA_TOVAL_TX2 = 0x01b7,
187 B3_MA_TO_CTRL = 0x01b8,
188 B3_MA_TO_TEST = 0x01ba,
189 B3_MA_RCINI_RX1 = 0x01c0,
190 B3_MA_RCINI_RX2 = 0x01c1,
191 B3_MA_RCINI_TX1 = 0x01c2,
192 B3_MA_RCINI_TX2 = 0x01c3,
193 B3_MA_RCVAL_RX1 = 0x01c4,
194 B3_MA_RCVAL_RX2 = 0x01c5,
195 B3_MA_RCVAL_TX1 = 0x01c6,
196 B3_MA_RCVAL_TX2 = 0x01c7,
197 B3_MA_RC_CTRL = 0x01c8,
198 B3_MA_RC_TEST = 0x01ca,
199 B3_PA_TOINI_RX1 = 0x01d0,
200 B3_PA_TOINI_RX2 = 0x01d4,
201 B3_PA_TOINI_TX1 = 0x01d8,
202 B3_PA_TOINI_TX2 = 0x01dc,
203 B3_PA_TOVAL_RX1 = 0x01e0,
204 B3_PA_TOVAL_RX2 = 0x01e4,
205 B3_PA_TOVAL_TX1 = 0x01e8,
206 B3_PA_TOVAL_TX2 = 0x01ec,
207 B3_PA_CTRL = 0x01f0,
208 B3_PA_TEST = 0x01f2,
210 Y2_CFG_SPC = 0x1c00,
211 };
213 /* B0_CTST 16 bit Control/Status register */
214 enum {
215 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
216 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
217 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
218 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
219 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
220 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
221 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
222 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
223 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
224 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
226 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
227 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
228 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
229 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
230 CS_MRST_CLR = 1<<3, /* Clear Master reset */
231 CS_MRST_SET = 1<<2, /* Set Master reset */
232 CS_RST_CLR = 1<<1, /* Clear Software reset */
233 CS_RST_SET = 1, /* Set Software reset */
234 };
236 /* B0_LED 8 Bit LED register */
237 enum {
238 /* Bit 7.. 2: reserved */
239 LED_STAT_ON = 1<<1, /* Status LED on */
240 LED_STAT_OFF = 1, /* Status LED off */
241 };
243 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
244 enum {
245 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
246 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
247 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
248 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
249 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
250 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
251 PC_VCC_ON = 1<<1, /* Switch VCC On */
252 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
253 };
255 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
257 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
258 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
259 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
260 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
261 enum {
262 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
263 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
264 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
266 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
267 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
268 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
269 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
271 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
272 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
273 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
274 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
275 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
277 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
278 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
279 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
280 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
281 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
283 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
284 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
285 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
286 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
287 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
288 };
290 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
291 enum {
292 IS_ERR_MSK = 0x00003fff,/* All Error bits */
294 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
295 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
296 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
297 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
298 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
299 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
300 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
301 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
302 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
303 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
304 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
305 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
306 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
307 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
308 };
310 /* Hardware error interrupt mask for Yukon 2 */
311 enum {
312 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
313 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
314 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
315 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
316 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
317 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
318 /* Link 2 */
319 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
320 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
321 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
322 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
323 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
324 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
325 /* Link 1 */
326 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
327 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
328 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
329 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
330 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
331 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
333 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
334 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
335 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
336 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
338 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
339 Y2_IS_PCI_EXP |
340 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
341 };
343 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
344 enum {
345 DPT_START = 1<<1,
346 DPT_STOP = 1<<0,
347 };
349 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
350 enum {
351 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
352 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
353 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
354 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
355 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
356 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
357 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
358 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
359 };
361 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
362 enum {
363 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
364 /* Bit 3.. 2: reserved */
365 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
366 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
367 };
369 /* B2_CHIP_ID 8 bit Chip Identification Number */
370 enum {
371 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
372 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
373 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
374 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
375 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
376 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
377 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
378 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
380 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
381 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
382 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
384 CHIP_REV_YU_EC_U_A0 = 0,
385 CHIP_REV_YU_EC_U_A1 = 1,
386 };
388 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
389 enum {
390 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
391 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
392 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
393 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
394 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
395 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
396 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
397 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
398 };
400 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
401 enum {
402 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
403 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
404 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
405 };
406 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
407 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
410 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
411 enum {
412 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
413 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
414 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
415 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
416 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
417 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
418 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
419 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
420 };
422 /* B2_TI_CTRL 8 bit Timer control */
423 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
424 enum {
425 TIM_START = 1<<2, /* Start Timer */
426 TIM_STOP = 1<<1, /* Stop Timer */
427 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
428 };
430 /* B2_TI_TEST 8 Bit Timer Test */
431 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
432 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
433 enum {
434 TIM_T_ON = 1<<2, /* Test mode on */
435 TIM_T_OFF = 1<<1, /* Test mode off */
436 TIM_T_STEP = 1<<0, /* Test step */
437 };
439 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
440 /* Bit 31..19: reserved */
441 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
442 /* RAM Interface Registers */
444 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
445 enum {
446 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
447 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
449 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
450 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
451 };
453 #define SK_RI_TO_53 36 /* RAM interface timeout */
456 /* Port related registers FIFO, and Arbiter */
457 #define SK_REG(port,reg) (((port)<<7)+(reg))
459 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
460 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
461 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
462 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
463 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
465 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
467 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
468 enum {
469 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
470 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
471 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
472 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
473 TXA_START_RC = 1<<3, /* Start sync Rate Control */
474 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
475 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
476 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
477 };
479 /*
480 * Bank 4 - 5
481 */
482 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
483 enum {
484 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
485 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
486 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
487 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
488 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
489 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
490 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
491 };
494 enum {
495 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
496 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
497 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
498 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
499 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
500 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
501 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
502 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
503 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
504 };
506 /* Queue Register Offsets, use Q_ADDR() to access */
507 enum {
508 B8_Q_REGS = 0x0400, /* base of Queue registers */
509 Q_D = 0x00, /* 8*32 bit Current Descriptor */
510 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
511 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
512 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
513 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
514 Q_BC = 0x30, /* 32 bit Current Byte Counter */
515 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
516 Q_F = 0x38, /* 32 bit Flag Register */
517 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
518 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
519 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
520 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
521 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
522 Q_T2 = 0x40, /* 32 bit Test Register 2 */
523 Q_T3 = 0x44, /* 32 bit Test Register 3 */
525 /* Yukon-2 */
526 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
527 Q_WM = 0x40, /* 16 bit FIFO Watermark */
528 Q_AL = 0x42, /* 8 bit FIFO Alignment */
529 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
530 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
531 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
532 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
533 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
534 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
535 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
536 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
537 };
538 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
540 /* Q_F 32 bit Flag Register */
541 enum {
542 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
543 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
544 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
545 F_WM_REACHED = 1<<25, /* Watermark reached */
546 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
547 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
548 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
549 };
551 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
552 enum {
553 Y2_B8_PREF_REGS = 0x0450,
555 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
556 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
557 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
558 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
559 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
560 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
561 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
562 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
563 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
564 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
566 PREF_UNIT_MASK_IDX = 0x0fff,
567 };
568 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
570 /* RAM Buffer Register Offsets */
571 enum {
573 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
574 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
575 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
576 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
577 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
578 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
579 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
580 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
581 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
582 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
583 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
584 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
585 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
586 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
587 };
589 /* Receive and Transmit Queues */
590 enum {
591 Q_R1 = 0x0000, /* Receive Queue 1 */
592 Q_R2 = 0x0080, /* Receive Queue 2 */
593 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
594 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
595 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
596 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
597 };
599 /* Different PHY Types */
600 enum {
601 PHY_ADDR_MARV = 0,
602 };
604 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
607 enum {
608 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
609 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
610 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
611 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
613 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
615 /* Receive GMAC FIFO (YUKON and Yukon-2) */
617 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
618 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
619 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
620 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
621 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
622 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
623 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
624 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
625 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
626 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
628 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
630 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
632 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
633 };
636 /* Q_BC 32 bit Current Byte Counter */
638 /* BMU Control Status Registers */
639 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
640 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
641 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
642 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
643 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
644 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
645 /* Q_CSR 32 bit BMU Control/Status Register */
647 /* Rx BMU Control / Status Registers (Yukon-2) */
648 enum {
649 BMU_IDLE = 1<<31, /* BMU Idle State */
650 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
651 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
653 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
654 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
655 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
656 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
657 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
658 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
659 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
660 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
661 BMU_START = 1<<8, /* Start Rx/Tx Queue */
662 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
663 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
664 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
665 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
666 BMU_OP_ON = 1<<3, /* BMU Operational On */
667 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
668 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
669 BMU_RST_SET = 1<<0, /* Set BMU Reset */
671 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
672 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
673 BMU_FIFO_ENA | BMU_OP_ON,
675 BMU_WM_DEFAULT = 0x600,
676 };
678 /* Tx BMU Control / Status Registers (Yukon-2) */
679 /* Bit 31: same as for Rx */
680 enum {
681 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
682 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
683 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
684 };
686 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
687 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
688 enum {
689 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
690 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
691 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
692 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
693 };
695 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
696 /* RB_START 32 bit RAM Buffer Start Address */
697 /* RB_END 32 bit RAM Buffer End Address */
698 /* RB_WP 32 bit RAM Buffer Write Pointer */
699 /* RB_RP 32 bit RAM Buffer Read Pointer */
700 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
701 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
702 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
703 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
704 /* RB_PC 32 bit RAM Buffer Packet Counter */
705 /* RB_LEV 32 bit RAM Buffer Level Register */
707 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
708 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
709 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
711 /* RB_CTRL 8 bit RAM Buffer Control Register */
712 enum {
713 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
714 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
715 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
716 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
717 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
718 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
719 };
722 /* Transmit GMAC FIFO (YUKON only) */
723 enum {
724 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
725 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
726 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
728 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
729 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
730 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
732 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
733 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
734 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
735 };
737 /* Descriptor Poll Timer Registers */
738 enum {
739 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
740 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
741 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
743 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
744 };
746 /* Time Stamp Timer Registers (YUKON only) */
747 enum {
748 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
749 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
750 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
751 };
753 /* Polling Unit Registers (Yukon-2 only) */
754 enum {
755 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
756 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
758 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
759 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
760 };
762 /* ASF Subsystem Registers (Yukon-2 only) */
763 enum {
764 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
765 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
766 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
768 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
769 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
770 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
771 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
772 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
773 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
774 };
776 /* Status BMU Registers (Yukon-2 only)*/
777 enum {
778 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
779 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
781 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
782 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
783 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
784 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
785 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
786 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
787 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
788 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
790 /* FIFO Control/Status Registers (Yukon-2 only)*/
791 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
792 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
793 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
794 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
795 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
796 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
797 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
799 /* Level and ISR Timer Registers (Yukon-2 only)*/
800 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
801 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
802 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
803 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
804 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
805 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
806 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
807 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
808 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
809 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
810 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
811 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
812 };
814 enum {
815 LINKLED_OFF = 0x01,
816 LINKLED_ON = 0x02,
817 LINKLED_LINKSYNC_OFF = 0x04,
818 LINKLED_LINKSYNC_ON = 0x08,
819 LINKLED_BLINK_OFF = 0x10,
820 LINKLED_BLINK_ON = 0x20,
821 };
823 /* GMAC and GPHY Control Registers (YUKON only) */
824 enum {
825 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
826 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
827 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
828 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
829 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
831 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
833 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
835 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
836 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
837 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
838 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
839 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
840 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
841 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
843 /* WOL Pattern Length Registers (YUKON only) */
845 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
846 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
848 /* WOL Pattern Counter Registers (YUKON only) */
851 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
852 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
853 };
855 enum {
856 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
857 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
858 };
860 enum {
861 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
862 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
863 };
865 /*
866 * Marvel-PHY Registers, indirect addressed over GMAC
867 */
868 enum {
869 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
870 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
871 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
872 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
873 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
874 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
875 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
876 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
877 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
878 /* Marvel-specific registers */
879 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
880 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
881 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
882 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
883 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
884 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
885 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
886 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
887 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
888 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
889 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
890 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
891 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
892 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
893 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
894 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
895 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
896 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
898 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
899 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
900 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
901 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
902 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
903 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
904 };
906 enum {
907 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
908 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
909 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
910 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
911 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
912 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
913 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
914 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
915 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
916 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
917 };
919 enum {
920 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
921 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
922 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
923 };
925 enum {
926 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
928 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
929 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
930 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
931 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
932 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
933 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
934 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
935 };
937 enum {
938 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
939 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
940 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
941 };
943 /* different Marvell PHY Ids */
944 enum {
945 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
947 PHY_BCOM_ID1_A1 = 0x6041,
948 PHY_BCOM_ID1_B2 = 0x6043,
949 PHY_BCOM_ID1_C0 = 0x6044,
950 PHY_BCOM_ID1_C5 = 0x6047,
952 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
953 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
954 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
955 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
956 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
957 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
958 };
960 /* Advertisement register bits */
961 enum {
962 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
963 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
964 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
966 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
967 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
968 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
969 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
970 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
971 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
972 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
973 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
974 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
975 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
976 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
977 PHY_AN_100HALF | PHY_AN_100FULL,
978 };
980 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
981 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
982 enum {
983 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
984 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
985 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
986 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
987 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
988 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
989 /* Bit 9..8: reserved */
990 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
991 };
993 /** Marvell-Specific */
994 enum {
995 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
996 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
997 PHY_M_AN_RF = 1<<13, /* Remote Fault */
999 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1000 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1001 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1002 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1003 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1004 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1005 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1006 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1007 };
1009 /* special defines for FIBER (88E1011S only) */
1010 enum {
1011 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1012 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1013 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1014 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1015 };
1017 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1018 enum {
1019 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1020 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1021 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1022 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1023 };
1025 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1026 enum {
1027 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1028 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1029 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1030 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1031 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1032 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1033 };
1035 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1036 enum {
1037 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1038 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1039 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1040 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1041 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1042 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1043 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1044 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1045 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1046 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1047 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1048 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1049 };
1051 enum {
1052 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1053 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1054 };
1056 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1058 enum {
1059 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1060 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1061 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1062 };
1064 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1065 enum {
1066 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1067 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1068 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1069 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1070 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1072 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1073 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1075 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1076 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1077 };
1079 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1080 enum {
1081 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1082 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1083 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1084 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1085 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1086 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1087 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1088 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1089 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1090 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1091 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1092 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1093 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1094 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1095 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1096 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1097 };
1099 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1101 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1102 enum {
1103 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1104 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1105 };
1107 enum {
1108 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1109 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1110 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1111 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1112 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1113 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1114 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1115 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1116 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1117 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1118 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1119 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1121 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1122 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1123 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1125 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1126 | PHY_M_IS_FIFO_ERROR,
1127 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1128 };
1131 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1132 enum {
1133 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1134 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1136 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1137 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1138 /* (88E1011 only) */
1139 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1140 /* (88E1011 only) */
1141 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1142 /* (88E1111 only) */
1143 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1144 /* !!! Errata in spec. (1 = disable) */
1145 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1146 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1147 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1148 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1149 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1150 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1152 #define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1153 /* 00=1x; 01=2x; 10=3x; 11=4x */
1154 #define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1155 /* 00=dis; 01=1x; 10=2x; 11=3x */
1156 #define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1157 /* 000=1x; 001=2x; 010=3x; 011=4x */
1158 #define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1159 /* 01X=0; 110=2.5; 111=25 (MHz) */
1161 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1162 enum {
1163 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1164 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1165 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1166 };
1167 /* !!! Errata in spec. (1 = disable) */
1169 #define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1170 /* 100=5x; 101=6x; 110=7x; 111=8x */
1171 enum {
1172 MAC_TX_CLK_0_MHZ = 2,
1173 MAC_TX_CLK_2_5_MHZ = 6,
1174 MAC_TX_CLK_25_MHZ = 7,
1175 };
1177 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1178 enum {
1179 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1180 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1181 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1182 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1183 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1184 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1185 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1186 /* (88E1111 only) */
1187 };
1189 enum {
1190 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1191 /* (88E1011 only) */
1192 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1193 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1194 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1195 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1196 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1197 };
1199 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1201 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1202 enum {
1203 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1204 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1205 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1206 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1207 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1208 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1209 };
1211 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1212 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1213 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1214 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1215 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1216 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1218 enum {
1219 PULS_NO_STR = 0,/* no pulse stretching */
1220 PULS_21MS = 1,/* 21 ms to 42 ms */
1221 PULS_42MS = 2,/* 42 ms to 84 ms */
1222 PULS_84MS = 3,/* 84 ms to 170 ms */
1223 PULS_170MS = 4,/* 170 ms to 340 ms */
1224 PULS_340MS = 5,/* 340 ms to 670 ms */
1225 PULS_670MS = 6,/* 670 ms to 1.3 s */
1226 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1227 };
1229 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1231 enum {
1232 BLINK_42MS = 0,/* 42 ms */
1233 BLINK_84MS = 1,/* 84 ms */
1234 BLINK_170MS = 2,/* 170 ms */
1235 BLINK_340MS = 3,/* 340 ms */
1236 BLINK_670MS = 4,/* 670 ms */
1237 };
1239 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1240 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1241 /* Bit 13..12: reserved */
1242 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1243 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1244 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1245 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1246 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1247 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1249 enum {
1250 MO_LED_NORM = 0,
1251 MO_LED_BLINK = 1,
1252 MO_LED_OFF = 2,
1253 MO_LED_ON = 3,
1254 };
1256 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1257 enum {
1258 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1259 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1260 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1261 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1262 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1263 };
1265 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1266 enum {
1267 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1268 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1269 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1270 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1271 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1272 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1273 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1274 /* (88E1111 only) */
1276 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1277 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1278 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1279 };
1281 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1282 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1283 /* Bit 15..12: reserved (used internally) */
1284 enum {
1285 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1286 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1287 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1288 };
1290 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1291 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1292 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1294 enum {
1295 LED_PAR_CTRL_COLX = 0x00,
1296 LED_PAR_CTRL_ERROR = 0x01,
1297 LED_PAR_CTRL_DUPLEX = 0x02,
1298 LED_PAR_CTRL_DP_COL = 0x03,
1299 LED_PAR_CTRL_SPEED = 0x04,
1300 LED_PAR_CTRL_LINK = 0x05,
1301 LED_PAR_CTRL_TX = 0x06,
1302 LED_PAR_CTRL_RX = 0x07,
1303 LED_PAR_CTRL_ACT = 0x08,
1304 LED_PAR_CTRL_LNK_RX = 0x09,
1305 LED_PAR_CTRL_LNK_AC = 0x0a,
1306 LED_PAR_CTRL_ACT_BL = 0x0b,
1307 LED_PAR_CTRL_TX_BL = 0x0c,
1308 LED_PAR_CTRL_RX_BL = 0x0d,
1309 LED_PAR_CTRL_COL_BL = 0x0e,
1310 LED_PAR_CTRL_INACT = 0x0f
1311 };
1313 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1314 enum {
1315 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1316 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1317 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1318 };
1320 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1321 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1322 enum {
1323 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1324 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1325 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1326 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1327 };
1328 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1330 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1331 enum {
1332 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1333 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1334 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1335 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1336 };
1338 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1339 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1340 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1341 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1343 /* GMAC registers */
1344 /* Port Registers */
1345 enum {
1346 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1347 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1348 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1349 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1350 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1351 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1352 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1353 /* Source Address Registers */
1354 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1355 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1356 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1357 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1358 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1359 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1361 /* Multicast Address Hash Registers */
1362 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1363 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1364 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1365 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1367 /* Interrupt Source Registers */
1368 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1369 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1370 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1372 /* Interrupt Mask Registers */
1373 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1374 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1375 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1377 /* Serial Management Interface (SMI) Registers */
1378 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1379 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1380 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1381 /* MIB Counters */
1382 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1383 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1384 };
1387 /*
1388 * MIB Counters base address definitions (low word) -
1389 * use offset 4 for access to high word (32 bit r/o)
1390 */
1391 enum {
1392 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1393 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1394 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1395 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1396 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1398 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1399 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1400 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1401 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1402 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1403 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1404 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1405 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1406 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1407 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1408 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1409 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1410 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1411 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1412 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1414 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1415 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1416 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1417 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1418 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1419 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1420 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1421 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1422 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1423 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1424 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1425 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1426 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1427 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1429 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1430 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1431 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1432 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1433 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1434 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1435 };
1437 /* GMAC Bit Definitions */
1438 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1439 enum {
1440 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1441 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1442 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1443 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1444 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1445 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1446 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1447 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1449 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1450 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1451 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1452 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1453 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1454 };
1456 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1457 enum {
1458 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1459 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1460 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1461 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1462 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1463 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1464 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1465 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1466 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1467 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1468 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1469 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1470 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1471 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1472 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1473 };
1475 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1476 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1478 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1479 enum {
1480 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1481 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1482 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1483 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1484 };
1486 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1487 #define TX_COL_DEF 0x04
1489 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1490 enum {
1491 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1492 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1493 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1494 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1495 };
1497 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1498 enum {
1499 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1500 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1501 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1502 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1504 TX_JAM_LEN_DEF = 0x03,
1505 TX_JAM_IPG_DEF = 0x0b,
1506 TX_IPG_JAM_DEF = 0x1c,
1507 TX_BOF_LIM_DEF = 0x04,
1508 };
1510 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1511 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1512 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1513 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1516 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1517 enum {
1518 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1519 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1520 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1521 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1522 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1523 };
1525 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1526 #define DATA_BLIND_DEF 0x04
1528 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1529 #define IPG_DATA_DEF 0x1e
1531 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1532 enum {
1533 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1534 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1535 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1536 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1537 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1538 };
1540 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1541 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1543 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1544 enum {
1545 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1546 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1547 };
1549 /* Receive Frame Status Encoding */
1550 enum {
1551 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1552 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1553 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1554 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1555 GMR_FS_MC = 1<<10, /* Multicast Packet */
1556 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1557 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1558 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1559 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1560 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1561 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1562 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1564 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1565 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1567 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1568 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1569 GMR_FS_MII_ERR | GMR_FS_GOOD_FC | GMR_FS_BAD_FC |
1570 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1571 };
1573 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1574 enum {
1575 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1576 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1577 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1578 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1580 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1581 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1582 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1584 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1585 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1586 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1587 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1588 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1589 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1590 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1592 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1593 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1594 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1595 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1597 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1599 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1600 };
1603 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1604 enum {
1605 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1606 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1608 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1609 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1611 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1612 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1613 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1615 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1616 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1617 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1618 };
1620 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1621 enum {
1622 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1623 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1624 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1625 };
1627 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1628 enum {
1629 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1630 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1631 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1632 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1633 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1635 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1636 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1637 };
1639 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1640 enum {
1641 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1642 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1643 };
1645 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1646 enum {
1647 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1648 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1649 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1650 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1651 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1652 };
1654 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1655 enum {
1656 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1657 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1658 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1659 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1660 GMC_PAUSE_ON = 1<<3, /* Pause On */
1661 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1662 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1663 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1664 };
1666 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1667 enum {
1668 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1669 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1670 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1671 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1672 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1673 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1674 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1675 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1676 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1677 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1678 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1679 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1680 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1681 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1682 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1683 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1684 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1685 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1686 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1687 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1688 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1689 /* Bits 7..2: reserved */
1690 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1691 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1692 };
1694 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1695 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1696 enum {
1697 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1698 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1699 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1700 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1701 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1702 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1704 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1706 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1707 /* Bits 15.. 2: reserved */
1708 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1709 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1712 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1713 WOL_CTL_LINK_CHG_OCC = 1<<15,
1714 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1715 WOL_CTL_PATTERN_OCC = 1<<13,
1716 WOL_CTL_CLEAR_RESULT = 1<<12,
1717 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1718 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1719 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1720 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1721 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1722 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1723 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1724 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1725 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1726 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1727 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1728 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1729 };
1731 #define WOL_CTL_DEFAULT \
1732 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1733 WOL_CTL_DIS_PME_ON_PATTERN | \
1734 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1735 WOL_CTL_DIS_LINK_CHG_UNIT | \
1736 WOL_CTL_DIS_PATTERN_UNIT | \
1737 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1739 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1740 #define WOL_CTL_PATT_ENA(x) (1 << (x))
1743 /* Control flags */
1744 enum {
1745 UDPTCP = 1<<0,
1746 CALSUM = 1<<1,
1747 WR_SUM = 1<<2,
1748 INIT_SUM= 1<<3,
1749 LOCK_SUM= 1<<4,
1750 INS_VLAN= 1<<5,
1751 FRC_STAT= 1<<6,
1752 EOP = 1<<7,
1753 };
1755 enum {
1756 HW_OWNER = 1<<7,
1757 OP_TCPWRITE = 0x11,
1758 OP_TCPSTART = 0x12,
1759 OP_TCPINIT = 0x14,
1760 OP_TCPLCK = 0x18,
1761 OP_TCPCHKSUM = OP_TCPSTART,
1762 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1763 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1764 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1765 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1767 OP_ADDR64 = 0x21,
1768 OP_VLAN = 0x22,
1769 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1770 OP_LRGLEN = 0x24,
1771 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1772 OP_BUFFER = 0x40,
1773 OP_PACKET = 0x41,
1774 OP_LARGESEND = 0x43,
1776 /* YUKON-2 STATUS opcodes defines */
1777 OP_RXSTAT = 0x60,
1778 OP_RXTIMESTAMP = 0x61,
1779 OP_RXVLAN = 0x62,
1780 OP_RXCHKS = 0x64,
1781 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1782 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1783 OP_RSS_HASH = 0x65,
1784 OP_TXINDEXLE = 0x68,
1785 };
1787 /* Yukon 2 hardware interface
1788 * Not tested on big endian
1789 */
1790 struct sky2_tx_le {
1791 union {
1792 __le32 addr;
1793 struct {
1794 __le16 offset;
1795 __le16 start;
1796 } csum __attribute((packed));
1797 struct {
1798 __le16 size;
1799 __le16 rsvd;
1800 } tso __attribute((packed));
1801 } tx;
1802 __le16 length; /* also vlan tag or checksum start */
1803 u8 ctrl;
1804 u8 opcode;
1805 } __attribute((packed));
1807 struct sky2_rx_le {
1808 __le32 addr;
1809 __le16 length;
1810 u8 ctrl;
1811 u8 opcode;
1812 } __attribute((packed));
1814 struct sky2_status_le {
1815 __le32 status; /* also checksum */
1816 __le16 length; /* also vlan tag */
1817 u8 link;
1818 u8 opcode;
1819 } __attribute((packed));
1821 struct tx_ring_info {
1822 struct sk_buff *skb;
1823 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1824 u16 idx;
1825 };
1827 struct ring_info {
1828 struct sk_buff *skb;
1829 dma_addr_t mapaddr;
1830 };
1832 struct sky2_port {
1833 struct sky2_hw *hw;
1834 struct net_device *netdev;
1835 unsigned port;
1836 u32 msg_enable;
1837 spinlock_t phy_lock;
1839 spinlock_t tx_lock ____cacheline_aligned_in_smp;
1840 struct tx_ring_info *tx_ring;
1841 struct sky2_tx_le *tx_le;
1842 u16 tx_cons; /* next le to check */
1843 u16 tx_prod; /* next le to use */
1844 u32 tx_addr64;
1845 u16 tx_pending;
1846 u16 tx_last_mss;
1848 struct ring_info *rx_ring ____cacheline_aligned_in_smp;
1849 struct sky2_rx_le *rx_le;
1850 u32 rx_addr64;
1851 u16 rx_next; /* next re to check */
1852 u16 rx_put; /* next le index to use */
1853 u16 rx_pending;
1854 u16 rx_bufsize;
1855 #ifdef SKY2_VLAN_TAG_USED
1856 u16 rx_tag;
1857 struct vlan_group *vlgrp;
1858 #endif
1860 dma_addr_t rx_le_map;
1861 dma_addr_t tx_le_map;
1862 u32 advertising; /* ADVERTISED_ bits */
1863 u16 speed; /* SPEED_1000, SPEED_100, ... */
1864 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1865 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1866 u8 rx_pause;
1867 u8 tx_pause;
1868 u8 rx_csum;
1870 struct net_device_stats net_stats;
1872 };
1874 struct sky2_hw {
1875 void __iomem *regs;
1876 struct pci_dev *pdev;
1877 struct net_device *dev[2];
1879 int pm_cap;
1880 u8 chip_id;
1881 u8 chip_rev;
1882 u8 copper;
1883 u8 ports;
1885 struct sky2_status_le *st_le;
1886 u32 st_idx;
1887 dma_addr_t st_dma;
1889 struct timer_list idle_timer;
1890 int msi_detected;
1891 wait_queue_head_t msi_wait;
1892 };
1894 /* Register accessor for memory mapped device */
1895 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1897 return readl(hw->regs + reg);
1900 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1902 return readw(hw->regs + reg);
1905 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1907 return readb(hw->regs + reg);
1910 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1912 writel(val, hw->regs + reg);
1915 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1917 writew(val, hw->regs + reg);
1920 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1922 writeb(val, hw->regs + reg);
1925 /* Yukon PHY related registers */
1926 #define SK_GMAC_REG(port,reg) \
1927 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1928 #define GM_PHY_RETRIES 100
1930 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1932 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1935 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1937 unsigned base = SK_GMAC_REG(port, reg);
1938 return (u32) sky2_read16(hw, base)
1939 | (u32) sky2_read16(hw, base+4) << 16;
1942 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1944 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1947 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1948 const u8 *addr)
1950 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1951 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1952 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1955 /* PCI config space access */
1956 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
1958 return sky2_read32(hw, Y2_CFG_SPC + reg);
1961 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
1963 return sky2_read16(hw, Y2_CFG_SPC + reg);
1966 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
1968 sky2_write32(hw, Y2_CFG_SPC + reg, val);
1971 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
1973 sky2_write16(hw, Y2_CFG_SPC + reg, val);
1975 #endif