ia64/linux-2.6.18-xen.hg

view drivers/net/sk_mca.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 #ifndef _SK_MCA_INCLUDE_
2 #define _SK_MCA_INCLUDE_
4 #ifdef _SK_MCA_DRIVER_
6 /* Adapter ID's */
7 #define SKNET_MCA_ID 0x6afd
8 #define SKNET_JUNIOR_MCA_ID 0x6be9
10 /* media enumeration - defined in a way that it fits onto the MC2+'s
11 POS registers... */
13 typedef enum { Media_10Base2, Media_10BaseT,
14 Media_10Base5, Media_Unknown, Media_Count
15 } skmca_medium;
17 /* private structure */
18 typedef struct {
19 unsigned int slot; /* MCA-Slot-# */
20 void __iomem *base;
21 void __iomem *macbase; /* base address of MAC address PROM */
22 void __iomem *ioregaddr;/* address of I/O-register (Lo) */
23 void __iomem *ctrladdr; /* address of control/stat register */
24 void __iomem *cmdaddr; /* address of I/O-command register */
25 int nextrx; /* index of next RX descriptor to
26 be read */
27 int nexttxput; /* index of next free TX descriptor */
28 int nexttxdone; /* index of next TX descriptor to
29 be finished */
30 int txbusy; /* # of busy TX descriptors */
31 struct net_device_stats stat; /* packet statistics */
32 int realirq; /* memorizes actual IRQ, even when
33 currently not allocated */
34 skmca_medium medium; /* physical cannector */
35 spinlock_t lock;
36 } skmca_priv;
38 /* card registers: control/status register bits */
40 #define CTRL_ADR_DATA 0 /* Bit 0 = 0 ->access data register */
41 #define CTRL_ADR_RAP 1 /* Bit 0 = 1 ->access RAP register */
42 #define CTRL_RW_WRITE 0 /* Bit 1 = 0 ->write register */
43 #define CTRL_RW_READ 2 /* Bit 1 = 1 ->read register */
44 #define CTRL_RESET_ON 0 /* Bit 3 = 0 ->reset board */
45 #define CTRL_RESET_OFF 8 /* Bit 3 = 1 ->no reset of board */
47 #define STAT_ADR_DATA 0 /* Bit 0 of ctrl register read back */
48 #define STAT_ADR_RAP 1
49 #define STAT_RW_WRITE 0 /* Bit 1 of ctrl register read back */
50 #define STAT_RW_READ 2
51 #define STAT_RESET_ON 0 /* Bit 3 of ctrl register read back */
52 #define STAT_RESET_OFF 8
53 #define STAT_IRQ_ACT 0 /* interrupt pending */
54 #define STAT_IRQ_NOACT 16 /* no interrupt pending */
55 #define STAT_IO_NOBUSY 0 /* no transfer busy */
56 #define STAT_IO_BUSY 32 /* transfer busy */
58 /* I/O command register bits */
60 #define IOCMD_GO 128 /* Bit 7 = 1 -> start register xfer */
62 /* LANCE registers */
64 #define LANCE_CSR0 0 /* Status/Control */
66 #define CSR0_ERR 0x8000 /* general error flag */
67 #define CSR0_BABL 0x4000 /* transmitter timeout */
68 #define CSR0_CERR 0x2000 /* collision error */
69 #define CSR0_MISS 0x1000 /* lost Rx block */
70 #define CSR0_MERR 0x0800 /* memory access error */
71 #define CSR0_RINT 0x0400 /* receiver interrupt */
72 #define CSR0_TINT 0x0200 /* transmitter interrupt */
73 #define CSR0_IDON 0x0100 /* initialization done */
74 #define CSR0_INTR 0x0080 /* general interrupt flag */
75 #define CSR0_INEA 0x0040 /* interrupt enable */
76 #define CSR0_RXON 0x0020 /* receiver enabled */
77 #define CSR0_TXON 0x0010 /* transmitter enabled */
78 #define CSR0_TDMD 0x0008 /* force transmission now */
79 #define CSR0_STOP 0x0004 /* stop LANCE */
80 #define CSR0_STRT 0x0002 /* start LANCE */
81 #define CSR0_INIT 0x0001 /* read initialization block */
83 #define LANCE_CSR1 1 /* addr bit 0..15 of initialization */
84 #define LANCE_CSR2 2 /* 16..23 block */
86 #define LANCE_CSR3 3 /* Bus control */
87 #define CSR3_BCON_HOLD 0 /* Bit 0 = 0 -> BM1,BM0,HOLD */
88 #define CSR3_BCON_BUSRQ 1 /* Bit 0 = 1 -> BUSAK0,BYTE,BUSRQ */
89 #define CSR3_ALE_HIGH 0 /* Bit 1 = 0 -> ALE asserted high */
90 #define CSR3_ALE_LOW 2 /* Bit 1 = 1 -> ALE asserted low */
91 #define CSR3_BSWAP_OFF 0 /* Bit 2 = 0 -> no byte swap */
92 #define CSR3_BSWAP_ON 4 /* Bit 2 = 1 -> byte swap */
94 /* LANCE structures */
96 typedef struct { /* LANCE initialization block */
97 u16 Mode; /* mode flags */
98 u8 PAdr[6]; /* MAC address */
99 u8 LAdrF[8]; /* Multicast filter */
100 u32 RdrP; /* Receive descriptor */
101 u32 TdrP; /* Transmit descriptor */
102 } LANCE_InitBlock;
104 /* Mode flags init block */
106 #define LANCE_INIT_PROM 0x8000 /* enable promiscous mode */
107 #define LANCE_INIT_INTL 0x0040 /* internal loopback */
108 #define LANCE_INIT_DRTY 0x0020 /* disable retry */
109 #define LANCE_INIT_COLL 0x0010 /* force collision */
110 #define LANCE_INIT_DTCR 0x0008 /* disable transmit CRC */
111 #define LANCE_INIT_LOOP 0x0004 /* loopback */
112 #define LANCE_INIT_DTX 0x0002 /* disable transmitter */
113 #define LANCE_INIT_DRX 0x0001 /* disable receiver */
115 typedef struct { /* LANCE Tx descriptor */
116 u16 LowAddr; /* bit 0..15 of address */
117 u16 Flags; /* bit 16..23 of address + Flags */
118 u16 Len; /* 2s complement of packet length */
119 u16 Status; /* Result of transmission */
120 } LANCE_TxDescr;
122 #define TXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
123 #define TXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
124 #define TXDSCR_FLAGS_MORE 0x1000 /* more than one retry needed? */
125 #define TXDSCR_FLAGS_ONE 0x0800 /* one retry? */
126 #define TXDSCR_FLAGS_DEF 0x0400 /* transmission deferred? */
127 #define TXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
128 #define TXDSCR_FLAGS_ENP 0x0100 /* last packet in chain? */
130 #define TXDSCR_STATUS_BUFF 0x8000 /* buffer error? */
131 #define TXDSCR_STATUS_UFLO 0x4000 /* silo underflow during transmit? */
132 #define TXDSCR_STATUS_LCOL 0x1000 /* late collision? */
133 #define TXDSCR_STATUS_LCAR 0x0800 /* loss of carrier? */
134 #define TXDSCR_STATUS_RTRY 0x0400 /* retry error? */
136 typedef struct { /* LANCE Rx descriptor */
137 u16 LowAddr; /* bit 0..15 of address */
138 u16 Flags; /* bit 16..23 of address + Flags */
139 u16 MaxLen; /* 2s complement of buffer length */
140 u16 Len; /* packet length */
141 } LANCE_RxDescr;
143 #define RXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
144 #define RXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
145 #define RXDSCR_FLAGS_FRAM 0x2000 /* framing error flag */
146 #define RXDSCR_FLAGS_OFLO 0x1000 /* FIFO overflow? */
147 #define RXDSCR_FLAGS_CRC 0x0800 /* CRC error? */
148 #define RXDSCR_FLAGS_BUFF 0x0400 /* buffer error? */
149 #define RXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
150 #define RXDCSR_FLAGS_ENP 0x0100 /* last packet in chain? */
152 /* RAM layout */
154 #define TXCOUNT 4 /* length of TX descriptor queue */
155 #define LTXCOUNT 2 /* log2 of it */
156 #define RXCOUNT 4 /* length of RX descriptor queue */
157 #define LRXCOUNT 2 /* log2 of it */
159 #define RAM_INITBASE 0 /* LANCE init block */
160 #define RAM_TXBASE 24 /* Start of TX descriptor queue */
161 #define RAM_RXBASE \
162 (RAM_TXBASE + (TXCOUNT * 8)) /* Start of RX descriptor queue */
163 #define RAM_DATABASE \
164 (RAM_RXBASE + (RXCOUNT * 8)) /* Start of data area for frames */
165 #define RAM_BUFSIZE 1580 /* max. frame size - should never be
166 reached */
168 #endif /* _SK_MCA_DRIVER_ */
170 #endif /* _SK_MCA_INCLUDE_ */