ia64/linux-2.6.18-xen.hg

view drivers/net/saa9730.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * SAA9730 ethernet driver description.
24 *
25 */
26 #ifndef _SAA9730_H
27 #define _SAA9730_H
30 /* Number of 6-byte entries in the CAM. */
31 #define LAN_SAA9730_CAM_ENTRIES 10
32 #define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4)
34 /* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
35 #define LAN_SAA9730_PACKET_SIZE 2048
37 /*
38 * Number of TX buffers = number of RX buffers = 2, which is fixed according
39 * to HW requirements.
40 */
41 #define LAN_SAA9730_BUFFERS 2
43 /* Number of RX packets per RX buffer. */
44 #define LAN_SAA9730_RCV_Q_SIZE 15
46 /* Number of TX packets per TX buffer. */
47 #define LAN_SAA9730_TXM_Q_SIZE 15
49 /*
50 * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
51 * packets received.
52 * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
53 * packets, the hardware can timeout after a certain time and still tell
54 * us packets have arrived.
55 * The timeout value in unit of 32 PCI clocks (33Mhz).
56 * The value 200 approximates 0.0002 seconds.
57 */
58 #define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1
59 #define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10
61 #define RXSF_NDIS 0
62 #define RXSF_READY 2
63 #define RXSF_HWDONE 3
65 #define TXSF_EMPTY 0
66 #define TXSF_READY 2
67 #define TXSF_HWDONE 3
69 #define LANEND_LITTLE 0
70 #define LANEND_BIG_2143 1
71 #define LANEND_BIG_4321 2
73 #define LANMB_ANY 0
74 #define LANMB_8 1
75 #define LANMB_32 2
76 #define LANMB_64 3
78 #define MACCM_AUTOMATIC 0
79 #define MACCM_10MB 1
80 #define MACCM_MII 2
82 /*
83 * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
84 */
85 #define PHY_CONTROL 0x0
86 #define PHY_STATUS 0x1
87 #define PHY_STATUS_LINK_UP 0x4
88 #define PHY_CONTROL_RESET 0x8000
89 #define PHY_CONTROL_AUTO_NEG 0x1000
90 #define PHY_CONTROL_RESTART_AUTO_NEG 0x0200
91 #define PHY_ADDRESS 0x0
93 /* PK_COUNT register. */
94 #define PK_COUNT_TX_A_SHF 24
95 #define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF)
96 #define PK_COUNT_TX_B_SHF 16
97 #define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF)
98 #define PK_COUNT_RX_A_SHF 8
99 #define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF)
100 #define PK_COUNT_RX_B_SHF 0
101 #define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF)
103 /* OK2USE register. */
104 #define OK2USE_TX_A 0x8
105 #define OK2USE_TX_B 0x4
106 #define OK2USE_RX_A 0x2
107 #define OK2USE_RX_B 0x1
109 /* LAN DMA CONTROL register. */
110 #define DMA_CTL_BLK_INT 0x80000000
111 #define DMA_CTL_MAX_XFER_SHF 18
112 #define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF)
113 #define DMA_CTL_ENDIAN_SHF 16
114 #define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF)
115 #define DMA_CTL_RX_INT_COUNT_SHF 8
116 #define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF)
117 #define DMA_CTL_EN_TX_DMA 0x00000080
118 #define DMA_CTL_EN_RX_DMA 0x00000040
119 #define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020
120 #define DMA_CTL_RX_INT_TO_EN 0x00000010
121 #define DMA_CTL_RX_INT_EN 0x00000008
122 #define DMA_CTL_TX_INT_EN 0x00000004
123 #define DMA_CTL_MAC_TX_INT_EN 0x00000002
124 #define DMA_CTL_MAC_RX_INT_EN 0x00000001
126 /* DMA STATUS register. */
127 #define DMA_STATUS_BAD_ADDR_SHF 16
128 #define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF)
129 #define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8
130 #define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF)
131 #define DMA_STATUS_TX_EN_SYNC 0x00000080
132 #define DMA_STATUS_RX_BUF_A_FUL 0x00000040
133 #define DMA_STATUS_RX_BUF_B_FUL 0x00000020
134 #define DMA_STATUS_RX_TO_INT 0x00000010
135 #define DMA_STATUS_RX_INT 0x00000008
136 #define DMA_STATUS_TX_INT 0x00000004
137 #define DMA_STATUS_MAC_TX_INT 0x00000002
138 #define DMA_STATUS_MAC_RX_INT 0x00000001
140 /* DMA TEST/PANIC SWITHES register. */
141 #define DMA_TEST_LOOPBACK 0x01000000
142 #define DMA_TEST_SW_RESET 0x00000001
144 /* MAC CONTROL register. */
145 #define MAC_CONTROL_EN_MISS_ROLL 0x00002000
146 #define MAC_CONTROL_MISS_ROLL 0x00000400
147 #define MAC_CONTROL_LOOP10 0x00000080
148 #define MAC_CONTROL_CONN_SHF 5
149 #define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF)
150 #define MAC_CONTROL_MAC_LOOP 0x00000010
151 #define MAC_CONTROL_FULL_DUP 0x00000008
152 #define MAC_CONTROL_RESET 0x00000004
153 #define MAC_CONTROL_HALT_IMM 0x00000002
154 #define MAC_CONTROL_HALT_REQ 0x00000001
156 /* CAM CONTROL register. */
157 #define CAM_CONTROL_COMP_EN 0x00000010
158 #define CAM_CONTROL_NEG_CAM 0x00000008
159 #define CAM_CONTROL_BROAD_ACC 0x00000004
160 #define CAM_CONTROL_GROUP_ACC 0x00000002
161 #define CAM_CONTROL_STATION_ACC 0x00000001
163 /* TRANSMIT CONTROL register. */
164 #define TX_CTL_EN_COMP 0x00004000
165 #define TX_CTL_EN_TX_PAR 0x00002000
166 #define TX_CTL_EN_LATE_COLL 0x00001000
167 #define TX_CTL_EN_EX_COLL 0x00000800
168 #define TX_CTL_EN_L_CARR 0x00000400
169 #define TX_CTL_EN_EX_DEFER 0x00000200
170 #define TX_CTL_EN_UNDER 0x00000100
171 #define TX_CTL_MII10 0x00000080
172 #define TX_CTL_SD_PAUSE 0x00000040
173 #define TX_CTL_NO_EX_DEF0 0x00000020
174 #define TX_CTL_F_BACK 0x00000010
175 #define TX_CTL_NO_CRC 0x00000008
176 #define TX_CTL_NO_PAD 0x00000004
177 #define TX_CTL_TX_HALT 0x00000002
178 #define TX_CTL_TX_EN 0x00000001
180 /* TRANSMIT STATUS register. */
181 #define TX_STATUS_SQ_ERR 0x00010000
182 #define TX_STATUS_TX_HALTED 0x00008000
183 #define TX_STATUS_COMP 0x00004000
184 #define TX_STATUS_TX_PAR 0x00002000
185 #define TX_STATUS_LATE_COLL 0x00001000
186 #define TX_STATUS_TX10_STAT 0x00000800
187 #define TX_STATUS_L_CARR 0x00000400
188 #define TX_STATUS_EX_DEFER 0x00000200
189 #define TX_STATUS_UNDER 0x00000100
190 #define TX_STATUS_IN_TX 0x00000080
191 #define TX_STATUS_PAUSED 0x00000040
192 #define TX_STATUS_TX_DEFERRED 0x00000020
193 #define TX_STATUS_EX_COLL 0x00000010
194 #define TX_STATUS_TX_COLL_SHF 0
195 #define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF)
197 /* RECEIVE CONTROL register. */
198 #define RX_CTL_EN_GOOD 0x00004000
199 #define RX_CTL_EN_RX_PAR 0x00002000
200 #define RX_CTL_EN_LONG_ERR 0x00000800
201 #define RX_CTL_EN_OVER 0x00000400
202 #define RX_CTL_EN_CRC_ERR 0x00000200
203 #define RX_CTL_EN_ALIGN 0x00000100
204 #define RX_CTL_IGNORE_CRC 0x00000040
205 #define RX_CTL_PASS_CTL 0x00000020
206 #define RX_CTL_STRIP_CRC 0x00000010
207 #define RX_CTL_SHORT_EN 0x00000008
208 #define RX_CTL_LONG_EN 0x00000004
209 #define RX_CTL_RX_HALT 0x00000002
210 #define RX_CTL_RX_EN 0x00000001
212 /* RECEIVE STATUS register. */
213 #define RX_STATUS_RX_HALTED 0x00008000
214 #define RX_STATUS_GOOD 0x00004000
215 #define RX_STATUS_RX_PAR 0x00002000
216 #define RX_STATUS_LONG_ERR 0x00000800
217 #define RX_STATUS_OVERFLOW 0x00000400
218 #define RX_STATUS_CRC_ERR 0x00000200
219 #define RX_STATUS_ALIGN_ERR 0x00000100
220 #define RX_STATUS_RX10_STAT 0x00000080
221 #define RX_STATUS_INT_RX 0x00000040
222 #define RX_STATUS_CTL_RECD 0x00000020
224 /* MD_CA register. */
225 #define MD_CA_PRE_SUP 0x00001000
226 #define MD_CA_BUSY 0x00000800
227 #define MD_CA_WR 0x00000400
228 #define MD_CA_PHY_SHF 5
229 #define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF)
230 #define MD_CA_ADDR_SHF 0
231 #define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF)
233 /* Tx Status/Control. */
234 #define TX_STAT_CTL_OWNER_SHF 30
235 #define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF)
236 #define TX_STAT_CTL_FRAME_SHF 27
237 #define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF)
238 #define TX_STAT_CTL_STATUS_SHF 11
239 #define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF)
240 #define TX_STAT_CTL_LENGTH_SHF 0
241 #define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF)
243 #define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \
244 TX_STATUS_TX_HALTED | \
245 TX_STATUS_TX_PAR | \
246 TX_STATUS_LATE_COLL | \
247 TX_STATUS_L_CARR | \
248 TX_STATUS_EX_DEFER | \
249 TX_STATUS_UNDER | \
250 TX_STATUS_PAUSED | \
251 TX_STATUS_TX_DEFERRED | \
252 TX_STATUS_EX_COLL | \
253 TX_STATUS_TX_COLL_MSK) \
254 << TX_STAT_CTL_STATUS_SHF)
255 #define TX_STAT_CTL_INT_AFTER_TX 0x4
257 /* Rx Status/Control. */
258 #define RX_STAT_CTL_OWNER_SHF 30
259 #define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF)
260 #define RX_STAT_CTL_STATUS_SHF 11
261 #define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF)
262 #define RX_STAT_CTL_LENGTH_SHF 0
263 #define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF)
267 /* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
268 #define SAA9730_LAN_REGS_ADDR 0x20400
269 #define SAA9730_LAN_REGS_SIZE 0x00400
271 struct lan_saa9730_regmap {
272 volatile unsigned int TxBuffA; /* 0x20400 */
273 volatile unsigned int TxBuffB; /* 0x20404 */
274 volatile unsigned int RxBuffA; /* 0x20408 */
275 volatile unsigned int RxBuffB; /* 0x2040c */
276 volatile unsigned int PacketCount; /* 0x20410 */
277 volatile unsigned int Ok2Use; /* 0x20414 */
278 volatile unsigned int LanDmaCtl; /* 0x20418 */
279 volatile unsigned int Timeout; /* 0x2041c */
280 volatile unsigned int DmaStatus; /* 0x20420 */
281 volatile unsigned int DmaTest; /* 0x20424 */
282 volatile unsigned char filler20428[0x20430 - 0x20428];
283 volatile unsigned int PauseCount; /* 0x20430 */
284 volatile unsigned int RemotePauseCount; /* 0x20434 */
285 volatile unsigned char filler20438[0x20440 - 0x20438];
286 volatile unsigned int MacCtl; /* 0x20440 */
287 volatile unsigned int CamCtl; /* 0x20444 */
288 volatile unsigned int TxCtl; /* 0x20448 */
289 volatile unsigned int TxStatus; /* 0x2044c */
290 volatile unsigned int RxCtl; /* 0x20450 */
291 volatile unsigned int RxStatus; /* 0x20454 */
292 volatile unsigned int StationMgmtData; /* 0x20458 */
293 volatile unsigned int StationMgmtCtl; /* 0x2045c */
294 volatile unsigned int CamAddress; /* 0x20460 */
295 volatile unsigned int CamData; /* 0x20464 */
296 volatile unsigned int CamEnable; /* 0x20468 */
297 volatile unsigned char filler2046c[0x20500 - 0x2046c];
298 volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */
299 volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */
300 volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */
301 volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */
302 volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */
303 volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */
304 };
305 typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap;
308 /* EVM interrupt control registers. */
309 #define EVM_LAN_INT 0x00010000
310 #define EVM_MASTER_EN 0x00000001
312 /* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
313 #define SAA9730_EVM_REGS_ADDR 0x02000
314 #define SAA9730_EVM_REGS_SIZE 0x00400
316 struct evm_saa9730_regmap {
317 volatile unsigned int InterruptStatus1; /* 0x2000 */
318 volatile unsigned int InterruptEnable1; /* 0x2004 */
319 volatile unsigned int InterruptMonitor1; /* 0x2008 */
320 volatile unsigned int Counter; /* 0x200c */
321 volatile unsigned int CounterThreshold; /* 0x2010 */
322 volatile unsigned int CounterControl; /* 0x2014 */
323 volatile unsigned int GpioControl1; /* 0x2018 */
324 volatile unsigned int InterruptStatus2; /* 0x201c */
325 volatile unsigned int InterruptEnable2; /* 0x2020 */
326 volatile unsigned int InterruptMonitor2; /* 0x2024 */
327 volatile unsigned int GpioControl2; /* 0x2028 */
328 volatile unsigned int InterruptBlock1; /* 0x202c */
329 volatile unsigned int InterruptBlock2; /* 0x2030 */
330 };
331 typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;
334 struct lan_saa9730_private {
335 /*
336 * Rx/Tx packet buffers.
337 * The Rx and Tx packets must be PACKET_SIZE aligned.
338 */
339 void *buffer_start;
340 unsigned int buffer_size;
342 /*
343 * DMA address of beginning of this object, returned
344 * by pci_alloc_consistent().
345 */
346 dma_addr_t dma_addr;
348 /* Pointer to the associated pci device structure */
349 struct pci_dev *pci_dev;
351 /* Pointer for the SAA9730 LAN controller register set. */
352 t_lan_saa9730_regmap *lan_saa9730_regs;
354 /* Pointer to the SAA9730 EVM register. */
355 t_evm_saa9730_regmap *evm_saa9730_regs;
357 /* Rcv buffer Index. */
358 unsigned char NextRcvPacketIndex;
359 /* Next buffer index. */
360 unsigned char NextRcvBufferIndex;
362 /* Index of next packet to use in that buffer. */
363 unsigned char NextTxmPacketIndex;
364 /* Next buffer index. */
365 unsigned char NextTxmBufferIndex;
367 /* Index of first pending packet ready to send. */
368 unsigned char PendingTxmPacketIndex;
369 /* Pending buffer index. */
370 unsigned char PendingTxmBufferIndex;
372 unsigned char DmaRcvPackets;
373 unsigned char DmaTxmPackets;
375 void *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
376 void *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
377 unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];
379 unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];
381 struct net_device_stats stats;
382 spinlock_t lock;
383 };
385 #endif /* _SAA9730_H */