ia64/linux-2.6.18-xen.hg

view drivers/net/pcnet32.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
29 static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
52 #include <asm/dma.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/irq.h>
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
71 { } /* terminate list */
72 };
74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
76 static int cards_found;
78 /*
79 * VLB I/O addresses
80 */
81 static unsigned int pcnet32_portlist[] __initdata =
82 { 0x300, 0x320, 0x340, 0x360, 0 };
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
88 static struct net_device *pcnet32_dev;
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
103 #define PCNET32_DMA_MASK 0xffffffff
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
130 };
132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Loopback test (offline)"
134 };
136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
138 #define PCNET32_NUM_REGS 136
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options[MAX_UNITS];
142 static int full_duplex[MAX_UNITS];
143 static int homepna[MAX_UNITS];
145 /*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
155 /*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
165 #endif
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
173 #define PKT_BUF_SZ 1544
175 /* Offsets from base I/O address. */
176 #define PCNET32_WIO_RDP 0x10
177 #define PCNET32_WIO_RAP 0x12
178 #define PCNET32_WIO_RESET 0x14
179 #define PCNET32_WIO_BDP 0x16
181 #define PCNET32_DWIO_RDP 0x10
182 #define PCNET32_DWIO_RAP 0x14
183 #define PCNET32_DWIO_RESET 0x18
184 #define PCNET32_DWIO_BDP 0x1C
186 #define PCNET32_TOTAL_SIZE 0x20
188 #define CSR0 0
189 #define CSR0_INIT 0x1
190 #define CSR0_START 0x2
191 #define CSR0_STOP 0x4
192 #define CSR0_TXPOLL 0x8
193 #define CSR0_INTEN 0x40
194 #define CSR0_IDON 0x0100
195 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196 #define PCNET32_INIT_LOW 1
197 #define PCNET32_INIT_HIGH 2
198 #define CSR3 3
199 #define CSR4 4
200 #define CSR5 5
201 #define CSR5_SUSPEND 0x0001
202 #define CSR15 15
203 #define PCNET32_MC_FILTER 8
205 #define PCNET32_79C970A 0x2621
207 /* The PCNET32 Rx and Tx ring descriptors. */
208 struct pcnet32_rx_head {
209 u32 base;
210 s16 buf_length;
211 s16 status;
212 u32 msg_length;
213 u32 reserved;
214 };
216 struct pcnet32_tx_head {
217 u32 base;
218 s16 length;
219 s16 status;
220 u32 misc;
221 u32 reserved;
222 };
224 /* The PCNET32 32-Bit initialization block, described in databook. */
225 struct pcnet32_init_block {
226 u16 mode;
227 u16 tlen_rlen;
228 u8 phys_addr[6];
229 u16 reserved;
230 u32 filter[2];
231 /* Receive and transmit ring base, along with extra bits. */
232 u32 rx_ring;
233 u32 tx_ring;
234 };
236 /* PCnet32 access functions */
237 struct pcnet32_access {
238 u16 (*read_csr) (unsigned long, int);
239 void (*write_csr) (unsigned long, int, u16);
240 u16 (*read_bcr) (unsigned long, int);
241 void (*write_bcr) (unsigned long, int, u16);
242 u16 (*read_rap) (unsigned long);
243 void (*write_rap) (unsigned long, u16);
244 void (*reset) (unsigned long);
245 };
247 /*
248 * The first field of pcnet32_private is read by the ethernet device
249 * so the structure should be allocated using pci_alloc_consistent().
250 */
251 struct pcnet32_private {
252 struct pcnet32_init_block init_block;
253 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
254 struct pcnet32_rx_head *rx_ring;
255 struct pcnet32_tx_head *tx_ring;
256 dma_addr_t dma_addr;/* DMA address of beginning of this
257 object, returned by pci_alloc_consistent */
258 struct pci_dev *pci_dev;
259 const char *name;
260 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
261 struct sk_buff **tx_skbuff;
262 struct sk_buff **rx_skbuff;
263 dma_addr_t *tx_dma_addr;
264 dma_addr_t *rx_dma_addr;
265 struct pcnet32_access a;
266 spinlock_t lock; /* Guard lock */
267 unsigned int cur_rx, cur_tx; /* The next free ring entry */
268 unsigned int rx_ring_size; /* current rx ring size */
269 unsigned int tx_ring_size; /* current tx ring size */
270 unsigned int rx_mod_mask; /* rx ring modular mask */
271 unsigned int tx_mod_mask; /* tx ring modular mask */
272 unsigned short rx_len_bits;
273 unsigned short tx_len_bits;
274 dma_addr_t rx_ring_dma_addr;
275 dma_addr_t tx_ring_dma_addr;
276 unsigned int dirty_rx, /* ring entries to be freed. */
277 dirty_tx;
279 struct net_device_stats stats;
280 char tx_full;
281 char phycount; /* number of phys found */
282 int options;
283 unsigned int shared_irq:1, /* shared irq possible */
284 dxsuflo:1, /* disable transmit stop on uflo */
285 mii:1; /* mii port available */
286 struct net_device *next;
287 struct mii_if_info mii_if;
288 struct timer_list watchdog_timer;
289 struct timer_list blink_timer;
290 u32 msg_enable; /* debug message level */
292 /* each bit indicates an available PHY */
293 u32 phymask;
294 unsigned short chip_version; /* which variant this is */
295 };
297 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
298 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
299 static int pcnet32_open(struct net_device *);
300 static int pcnet32_init_ring(struct net_device *);
301 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
302 static int pcnet32_rx(struct net_device *);
303 static void pcnet32_tx_timeout(struct net_device *dev);
304 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
305 static int pcnet32_close(struct net_device *);
306 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
307 static void pcnet32_load_multicast(struct net_device *dev);
308 static void pcnet32_set_multicast_list(struct net_device *);
309 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
310 static void pcnet32_watchdog(struct net_device *);
311 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
312 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
313 int val);
314 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
315 static void pcnet32_ethtool_test(struct net_device *dev,
316 struct ethtool_test *eth_test, u64 * data);
317 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
318 static int pcnet32_phys_id(struct net_device *dev, u32 data);
319 static void pcnet32_led_blink_callback(struct net_device *dev);
320 static int pcnet32_get_regs_len(struct net_device *dev);
321 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
322 void *ptr);
323 static void pcnet32_purge_tx_ring(struct net_device *dev);
324 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
325 static void pcnet32_free_ring(struct net_device *dev);
326 static void pcnet32_check_media(struct net_device *dev, int verbose);
328 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
329 {
330 outw(index, addr + PCNET32_WIO_RAP);
331 return inw(addr + PCNET32_WIO_RDP);
332 }
334 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
335 {
336 outw(index, addr + PCNET32_WIO_RAP);
337 outw(val, addr + PCNET32_WIO_RDP);
338 }
340 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
341 {
342 outw(index, addr + PCNET32_WIO_RAP);
343 return inw(addr + PCNET32_WIO_BDP);
344 }
346 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
347 {
348 outw(index, addr + PCNET32_WIO_RAP);
349 outw(val, addr + PCNET32_WIO_BDP);
350 }
352 static u16 pcnet32_wio_read_rap(unsigned long addr)
353 {
354 return inw(addr + PCNET32_WIO_RAP);
355 }
357 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
358 {
359 outw(val, addr + PCNET32_WIO_RAP);
360 }
362 static void pcnet32_wio_reset(unsigned long addr)
363 {
364 inw(addr + PCNET32_WIO_RESET);
365 }
367 static int pcnet32_wio_check(unsigned long addr)
368 {
369 outw(88, addr + PCNET32_WIO_RAP);
370 return (inw(addr + PCNET32_WIO_RAP) == 88);
371 }
373 static struct pcnet32_access pcnet32_wio = {
374 .read_csr = pcnet32_wio_read_csr,
375 .write_csr = pcnet32_wio_write_csr,
376 .read_bcr = pcnet32_wio_read_bcr,
377 .write_bcr = pcnet32_wio_write_bcr,
378 .read_rap = pcnet32_wio_read_rap,
379 .write_rap = pcnet32_wio_write_rap,
380 .reset = pcnet32_wio_reset
381 };
383 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
384 {
385 outl(index, addr + PCNET32_DWIO_RAP);
386 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
387 }
389 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
390 {
391 outl(index, addr + PCNET32_DWIO_RAP);
392 outl(val, addr + PCNET32_DWIO_RDP);
393 }
395 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
396 {
397 outl(index, addr + PCNET32_DWIO_RAP);
398 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
399 }
401 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
402 {
403 outl(index, addr + PCNET32_DWIO_RAP);
404 outl(val, addr + PCNET32_DWIO_BDP);
405 }
407 static u16 pcnet32_dwio_read_rap(unsigned long addr)
408 {
409 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
410 }
412 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
413 {
414 outl(val, addr + PCNET32_DWIO_RAP);
415 }
417 static void pcnet32_dwio_reset(unsigned long addr)
418 {
419 inl(addr + PCNET32_DWIO_RESET);
420 }
422 static int pcnet32_dwio_check(unsigned long addr)
423 {
424 outl(88, addr + PCNET32_DWIO_RAP);
425 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
426 }
428 static struct pcnet32_access pcnet32_dwio = {
429 .read_csr = pcnet32_dwio_read_csr,
430 .write_csr = pcnet32_dwio_write_csr,
431 .read_bcr = pcnet32_dwio_read_bcr,
432 .write_bcr = pcnet32_dwio_write_bcr,
433 .read_rap = pcnet32_dwio_read_rap,
434 .write_rap = pcnet32_dwio_write_rap,
435 .reset = pcnet32_dwio_reset
436 };
438 static void pcnet32_netif_stop(struct net_device *dev)
439 {
440 dev->trans_start = jiffies;
441 netif_poll_disable(dev);
442 netif_tx_disable(dev);
443 }
445 static void pcnet32_netif_start(struct net_device *dev)
446 {
447 netif_wake_queue(dev);
448 netif_poll_enable(dev);
449 }
451 /*
452 * Allocate space for the new sized tx ring.
453 * Free old resources
454 * Save new resources.
455 * Any failure keeps old resources.
456 * Must be called with lp->lock held.
457 */
458 static void pcnet32_realloc_tx_ring(struct net_device *dev,
459 struct pcnet32_private *lp,
460 unsigned int size)
461 {
462 dma_addr_t new_ring_dma_addr;
463 dma_addr_t *new_dma_addr_list;
464 struct pcnet32_tx_head *new_tx_ring;
465 struct sk_buff **new_skb_list;
467 pcnet32_purge_tx_ring(dev);
469 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
470 sizeof(struct pcnet32_tx_head) *
471 (1 << size),
472 &new_ring_dma_addr);
473 if (new_tx_ring == NULL) {
474 if (netif_msg_drv(lp))
475 printk("\n" KERN_ERR
476 "%s: Consistent memory allocation failed.\n",
477 dev->name);
478 return;
479 }
480 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
482 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
483 GFP_ATOMIC);
484 if (!new_dma_addr_list) {
485 if (netif_msg_drv(lp))
486 printk("\n" KERN_ERR
487 "%s: Memory allocation failed.\n", dev->name);
488 goto free_new_tx_ring;
489 }
491 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
492 GFP_ATOMIC);
493 if (!new_skb_list) {
494 if (netif_msg_drv(lp))
495 printk("\n" KERN_ERR
496 "%s: Memory allocation failed.\n", dev->name);
497 goto free_new_lists;
498 }
500 kfree(lp->tx_skbuff);
501 kfree(lp->tx_dma_addr);
502 pci_free_consistent(lp->pci_dev,
503 sizeof(struct pcnet32_tx_head) *
504 lp->tx_ring_size, lp->tx_ring,
505 lp->tx_ring_dma_addr);
507 lp->tx_ring_size = (1 << size);
508 lp->tx_mod_mask = lp->tx_ring_size - 1;
509 lp->tx_len_bits = (size << 12);
510 lp->tx_ring = new_tx_ring;
511 lp->tx_ring_dma_addr = new_ring_dma_addr;
512 lp->tx_dma_addr = new_dma_addr_list;
513 lp->tx_skbuff = new_skb_list;
514 return;
516 free_new_lists:
517 kfree(new_dma_addr_list);
518 free_new_tx_ring:
519 pci_free_consistent(lp->pci_dev,
520 sizeof(struct pcnet32_tx_head) *
521 (1 << size),
522 new_tx_ring,
523 new_ring_dma_addr);
524 return;
525 }
527 /*
528 * Allocate space for the new sized rx ring.
529 * Re-use old receive buffers.
530 * alloc extra buffers
531 * free unneeded buffers
532 * free unneeded buffers
533 * Save new resources.
534 * Any failure keeps old resources.
535 * Must be called with lp->lock held.
536 */
537 static void pcnet32_realloc_rx_ring(struct net_device *dev,
538 struct pcnet32_private *lp,
539 unsigned int size)
540 {
541 dma_addr_t new_ring_dma_addr;
542 dma_addr_t *new_dma_addr_list;
543 struct pcnet32_rx_head *new_rx_ring;
544 struct sk_buff **new_skb_list;
545 int new, overlap;
547 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
548 sizeof(struct pcnet32_rx_head) *
549 (1 << size),
550 &new_ring_dma_addr);
551 if (new_rx_ring == NULL) {
552 if (netif_msg_drv(lp))
553 printk("\n" KERN_ERR
554 "%s: Consistent memory allocation failed.\n",
555 dev->name);
556 return;
557 }
558 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
560 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
561 GFP_ATOMIC);
562 if (!new_dma_addr_list) {
563 if (netif_msg_drv(lp))
564 printk("\n" KERN_ERR
565 "%s: Memory allocation failed.\n", dev->name);
566 goto free_new_rx_ring;
567 }
569 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
570 GFP_ATOMIC);
571 if (!new_skb_list) {
572 if (netif_msg_drv(lp))
573 printk("\n" KERN_ERR
574 "%s: Memory allocation failed.\n", dev->name);
575 goto free_new_lists;
576 }
578 /* first copy the current receive buffers */
579 overlap = min(size, lp->rx_ring_size);
580 for (new = 0; new < overlap; new++) {
581 new_rx_ring[new] = lp->rx_ring[new];
582 new_dma_addr_list[new] = lp->rx_dma_addr[new];
583 new_skb_list[new] = lp->rx_skbuff[new];
584 }
585 /* now allocate any new buffers needed */
586 for (; new < size; new++ ) {
587 struct sk_buff *rx_skbuff;
588 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
589 if (!(rx_skbuff = new_skb_list[new])) {
590 /* keep the original lists and buffers */
591 if (netif_msg_drv(lp))
592 printk(KERN_ERR
593 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
594 dev->name);
595 goto free_all_new;
596 }
597 skb_reserve(rx_skbuff, 2);
599 new_dma_addr_list[new] =
600 pci_map_single(lp->pci_dev, rx_skbuff->data,
601 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
602 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
603 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
604 new_rx_ring[new].status = le16_to_cpu(0x8000);
605 }
606 /* and free any unneeded buffers */
607 for (; new < lp->rx_ring_size; new++) {
608 if (lp->rx_skbuff[new]) {
609 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
610 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
611 dev_kfree_skb(lp->rx_skbuff[new]);
612 }
613 }
615 kfree(lp->rx_skbuff);
616 kfree(lp->rx_dma_addr);
617 pci_free_consistent(lp->pci_dev,
618 sizeof(struct pcnet32_rx_head) *
619 lp->rx_ring_size, lp->rx_ring,
620 lp->rx_ring_dma_addr);
622 lp->rx_ring_size = (1 << size);
623 lp->rx_mod_mask = lp->rx_ring_size - 1;
624 lp->rx_len_bits = (size << 4);
625 lp->rx_ring = new_rx_ring;
626 lp->rx_ring_dma_addr = new_ring_dma_addr;
627 lp->rx_dma_addr = new_dma_addr_list;
628 lp->rx_skbuff = new_skb_list;
629 return;
631 free_all_new:
632 for (; --new >= lp->rx_ring_size; ) {
633 if (new_skb_list[new]) {
634 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
635 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
636 dev_kfree_skb(new_skb_list[new]);
637 }
638 }
639 kfree(new_skb_list);
640 free_new_lists:
641 kfree(new_dma_addr_list);
642 free_new_rx_ring:
643 pci_free_consistent(lp->pci_dev,
644 sizeof(struct pcnet32_rx_head) *
645 (1 << size),
646 new_rx_ring,
647 new_ring_dma_addr);
648 return;
649 }
651 static void pcnet32_purge_rx_ring(struct net_device *dev)
652 {
653 struct pcnet32_private *lp = dev->priv;
654 int i;
656 /* free all allocated skbuffs */
657 for (i = 0; i < lp->rx_ring_size; i++) {
658 lp->rx_ring[i].status = 0; /* CPU owns buffer */
659 wmb(); /* Make sure adapter sees owner change */
660 if (lp->rx_skbuff[i]) {
661 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
662 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
663 dev_kfree_skb_any(lp->rx_skbuff[i]);
664 }
665 lp->rx_skbuff[i] = NULL;
666 lp->rx_dma_addr[i] = 0;
667 }
668 }
670 #ifdef CONFIG_NET_POLL_CONTROLLER
671 static void pcnet32_poll_controller(struct net_device *dev)
672 {
673 disable_irq(dev->irq);
674 pcnet32_interrupt(0, dev, NULL);
675 enable_irq(dev->irq);
676 }
677 #endif
679 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
680 {
681 struct pcnet32_private *lp = dev->priv;
682 unsigned long flags;
683 int r = -EOPNOTSUPP;
685 if (lp->mii) {
686 spin_lock_irqsave(&lp->lock, flags);
687 mii_ethtool_gset(&lp->mii_if, cmd);
688 spin_unlock_irqrestore(&lp->lock, flags);
689 r = 0;
690 }
691 return r;
692 }
694 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
695 {
696 struct pcnet32_private *lp = dev->priv;
697 unsigned long flags;
698 int r = -EOPNOTSUPP;
700 if (lp->mii) {
701 spin_lock_irqsave(&lp->lock, flags);
702 r = mii_ethtool_sset(&lp->mii_if, cmd);
703 spin_unlock_irqrestore(&lp->lock, flags);
704 }
705 return r;
706 }
708 static void pcnet32_get_drvinfo(struct net_device *dev,
709 struct ethtool_drvinfo *info)
710 {
711 struct pcnet32_private *lp = dev->priv;
713 strcpy(info->driver, DRV_NAME);
714 strcpy(info->version, DRV_VERSION);
715 if (lp->pci_dev)
716 strcpy(info->bus_info, pci_name(lp->pci_dev));
717 else
718 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
719 }
721 static u32 pcnet32_get_link(struct net_device *dev)
722 {
723 struct pcnet32_private *lp = dev->priv;
724 unsigned long flags;
725 int r;
727 spin_lock_irqsave(&lp->lock, flags);
728 if (lp->mii) {
729 r = mii_link_ok(&lp->mii_if);
730 } else if (lp->chip_version >= PCNET32_79C970A) {
731 ulong ioaddr = dev->base_addr; /* card base I/O address */
732 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
733 } else { /* can not detect link on really old chips */
734 r = 1;
735 }
736 spin_unlock_irqrestore(&lp->lock, flags);
738 return r;
739 }
741 static u32 pcnet32_get_msglevel(struct net_device *dev)
742 {
743 struct pcnet32_private *lp = dev->priv;
744 return lp->msg_enable;
745 }
747 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
748 {
749 struct pcnet32_private *lp = dev->priv;
750 lp->msg_enable = value;
751 }
753 static int pcnet32_nway_reset(struct net_device *dev)
754 {
755 struct pcnet32_private *lp = dev->priv;
756 unsigned long flags;
757 int r = -EOPNOTSUPP;
759 if (lp->mii) {
760 spin_lock_irqsave(&lp->lock, flags);
761 r = mii_nway_restart(&lp->mii_if);
762 spin_unlock_irqrestore(&lp->lock, flags);
763 }
764 return r;
765 }
767 static void pcnet32_get_ringparam(struct net_device *dev,
768 struct ethtool_ringparam *ering)
769 {
770 struct pcnet32_private *lp = dev->priv;
772 ering->tx_max_pending = TX_MAX_RING_SIZE;
773 ering->tx_pending = lp->tx_ring_size;
774 ering->rx_max_pending = RX_MAX_RING_SIZE;
775 ering->rx_pending = lp->rx_ring_size;
776 }
778 static int pcnet32_set_ringparam(struct net_device *dev,
779 struct ethtool_ringparam *ering)
780 {
781 struct pcnet32_private *lp = dev->priv;
782 unsigned long flags;
783 unsigned int size;
784 ulong ioaddr = dev->base_addr;
785 int i;
787 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
788 return -EINVAL;
790 if (netif_running(dev))
791 pcnet32_netif_stop(dev);
793 spin_lock_irqsave(&lp->lock, flags);
794 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
796 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
798 /* set the minimum ring size to 4, to allow the loopback test to work
799 * unchanged.
800 */
801 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
802 if (size <= (1 << i))
803 break;
804 }
805 if ((1 << i) != lp->tx_ring_size)
806 pcnet32_realloc_tx_ring(dev, lp, i);
808 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
809 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
810 if (size <= (1 << i))
811 break;
812 }
813 if ((1 << i) != lp->rx_ring_size)
814 pcnet32_realloc_rx_ring(dev, lp, i);
816 dev->weight = lp->rx_ring_size / 2;
818 if (netif_running(dev)) {
819 pcnet32_netif_start(dev);
820 pcnet32_restart(dev, CSR0_NORMAL);
821 }
823 spin_unlock_irqrestore(&lp->lock, flags);
825 if (netif_msg_drv(lp))
826 printk(KERN_INFO
827 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
828 lp->rx_ring_size, lp->tx_ring_size);
830 return 0;
831 }
833 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
834 u8 * data)
835 {
836 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
837 }
839 static int pcnet32_self_test_count(struct net_device *dev)
840 {
841 return PCNET32_TEST_LEN;
842 }
844 static void pcnet32_ethtool_test(struct net_device *dev,
845 struct ethtool_test *test, u64 * data)
846 {
847 struct pcnet32_private *lp = dev->priv;
848 int rc;
850 if (test->flags == ETH_TEST_FL_OFFLINE) {
851 rc = pcnet32_loopback_test(dev, data);
852 if (rc) {
853 if (netif_msg_hw(lp))
854 printk(KERN_DEBUG "%s: Loopback test failed.\n",
855 dev->name);
856 test->flags |= ETH_TEST_FL_FAILED;
857 } else if (netif_msg_hw(lp))
858 printk(KERN_DEBUG "%s: Loopback test passed.\n",
859 dev->name);
860 } else if (netif_msg_hw(lp))
861 printk(KERN_DEBUG
862 "%s: No tests to run (specify 'Offline' on ethtool).",
863 dev->name);
864 } /* end pcnet32_ethtool_test */
866 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
867 {
868 struct pcnet32_private *lp = dev->priv;
869 struct pcnet32_access *a = &lp->a; /* access to registers */
870 ulong ioaddr = dev->base_addr; /* card base I/O address */
871 struct sk_buff *skb; /* sk buff */
872 int x, i; /* counters */
873 int numbuffs = 4; /* number of TX/RX buffers and descs */
874 u16 status = 0x8300; /* TX ring status */
875 u16 teststatus; /* test of ring status */
876 int rc; /* return code */
877 int size; /* size of packets */
878 unsigned char *packet; /* source packet data */
879 static const int data_len = 60; /* length of source packets */
880 unsigned long flags;
881 unsigned long ticks;
883 rc = 1; /* default to fail */
885 if (netif_running(dev))
886 pcnet32_close(dev);
888 spin_lock_irqsave(&lp->lock, flags);
889 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
891 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
893 /* Reset the PCNET32 */
894 lp->a.reset(ioaddr);
895 lp->a.write_csr(ioaddr, CSR4, 0x0915);
897 /* switch pcnet32 to 32bit mode */
898 lp->a.write_bcr(ioaddr, 20, 2);
900 /* purge & init rings but don't actually restart */
901 pcnet32_restart(dev, 0x0000);
903 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
905 /* Initialize Transmit buffers. */
906 size = data_len + 15;
907 for (x = 0; x < numbuffs; x++) {
908 if (!(skb = dev_alloc_skb(size))) {
909 if (netif_msg_hw(lp))
910 printk(KERN_DEBUG
911 "%s: Cannot allocate skb at line: %d!\n",
912 dev->name, __LINE__);
913 goto clean_up;
914 } else {
915 packet = skb->data;
916 skb_put(skb, size); /* create space for data */
917 lp->tx_skbuff[x] = skb;
918 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
919 lp->tx_ring[x].misc = 0;
921 /* put DA and SA into the skb */
922 for (i = 0; i < 6; i++)
923 *packet++ = dev->dev_addr[i];
924 for (i = 0; i < 6; i++)
925 *packet++ = dev->dev_addr[i];
926 /* type */
927 *packet++ = 0x08;
928 *packet++ = 0x06;
929 /* packet number */
930 *packet++ = x;
931 /* fill packet with data */
932 for (i = 0; i < data_len; i++)
933 *packet++ = i;
935 lp->tx_dma_addr[x] =
936 pci_map_single(lp->pci_dev, skb->data, skb->len,
937 PCI_DMA_TODEVICE);
938 lp->tx_ring[x].base =
939 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
940 wmb(); /* Make sure owner changes after all others are visible */
941 lp->tx_ring[x].status = le16_to_cpu(status);
942 }
943 }
945 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
946 a->write_bcr(ioaddr, 32, x | 0x0002);
948 /* set int loopback in CSR15 */
949 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
950 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
952 teststatus = le16_to_cpu(0x8000);
953 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
955 /* Check status of descriptors */
956 for (x = 0; x < numbuffs; x++) {
957 ticks = 0;
958 rmb();
959 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
960 spin_unlock_irqrestore(&lp->lock, flags);
961 msleep(1);
962 spin_lock_irqsave(&lp->lock, flags);
963 rmb();
964 ticks++;
965 }
966 if (ticks == 200) {
967 if (netif_msg_hw(lp))
968 printk("%s: Desc %d failed to reset!\n",
969 dev->name, x);
970 break;
971 }
972 }
974 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
975 wmb();
976 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
977 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
979 for (x = 0; x < numbuffs; x++) {
980 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
981 skb = lp->rx_skbuff[x];
982 for (i = 0; i < size; i++) {
983 printk("%02x ", *(skb->data + i));
984 }
985 printk("\n");
986 }
987 }
989 x = 0;
990 rc = 0;
991 while (x < numbuffs && !rc) {
992 skb = lp->rx_skbuff[x];
993 packet = lp->tx_skbuff[x]->data;
994 for (i = 0; i < size; i++) {
995 if (*(skb->data + i) != packet[i]) {
996 if (netif_msg_hw(lp))
997 printk(KERN_DEBUG
998 "%s: Error in compare! %2x - %02x %02x\n",
999 dev->name, i, *(skb->data + i),
1000 packet[i]);
1001 rc = 1;
1002 break;
1005 x++;
1008 clean_up:
1009 *data1 = rc;
1010 pcnet32_purge_tx_ring(dev);
1012 x = a->read_csr(ioaddr, CSR15);
1013 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1015 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1016 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1018 if (netif_running(dev)) {
1019 spin_unlock_irqrestore(&lp->lock, flags);
1020 pcnet32_open(dev);
1021 } else {
1022 pcnet32_purge_rx_ring(dev);
1023 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1024 spin_unlock_irqrestore(&lp->lock, flags);
1027 return (rc);
1028 } /* end pcnet32_loopback_test */
1030 static void pcnet32_led_blink_callback(struct net_device *dev)
1032 struct pcnet32_private *lp = dev->priv;
1033 struct pcnet32_access *a = &lp->a;
1034 ulong ioaddr = dev->base_addr;
1035 unsigned long flags;
1036 int i;
1038 spin_lock_irqsave(&lp->lock, flags);
1039 for (i = 4; i < 8; i++) {
1040 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1042 spin_unlock_irqrestore(&lp->lock, flags);
1044 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1047 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1049 struct pcnet32_private *lp = dev->priv;
1050 struct pcnet32_access *a = &lp->a;
1051 ulong ioaddr = dev->base_addr;
1052 unsigned long flags;
1053 int i, regs[4];
1055 if (!lp->blink_timer.function) {
1056 init_timer(&lp->blink_timer);
1057 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1058 lp->blink_timer.data = (unsigned long)dev;
1061 /* Save the current value of the bcrs */
1062 spin_lock_irqsave(&lp->lock, flags);
1063 for (i = 4; i < 8; i++) {
1064 regs[i - 4] = a->read_bcr(ioaddr, i);
1066 spin_unlock_irqrestore(&lp->lock, flags);
1068 mod_timer(&lp->blink_timer, jiffies);
1069 set_current_state(TASK_INTERRUPTIBLE);
1071 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1072 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1074 msleep_interruptible(data * 1000);
1075 del_timer_sync(&lp->blink_timer);
1077 /* Restore the original value of the bcrs */
1078 spin_lock_irqsave(&lp->lock, flags);
1079 for (i = 4; i < 8; i++) {
1080 a->write_bcr(ioaddr, i, regs[i - 4]);
1082 spin_unlock_irqrestore(&lp->lock, flags);
1084 return 0;
1087 /*
1088 * lp->lock must be held.
1089 */
1090 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1091 int can_sleep)
1093 int csr5;
1094 struct pcnet32_private *lp = dev->priv;
1095 struct pcnet32_access *a = &lp->a;
1096 ulong ioaddr = dev->base_addr;
1097 int ticks;
1099 /* really old chips have to be stopped. */
1100 if (lp->chip_version < PCNET32_79C970A)
1101 return 0;
1103 /* set SUSPEND (SPND) - CSR5 bit 0 */
1104 csr5 = a->read_csr(ioaddr, CSR5);
1105 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1107 /* poll waiting for bit to be set */
1108 ticks = 0;
1109 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1110 spin_unlock_irqrestore(&lp->lock, *flags);
1111 if (can_sleep)
1112 msleep(1);
1113 else
1114 mdelay(1);
1115 spin_lock_irqsave(&lp->lock, *flags);
1116 ticks++;
1117 if (ticks > 200) {
1118 if (netif_msg_hw(lp))
1119 printk(KERN_DEBUG
1120 "%s: Error getting into suspend!\n",
1121 dev->name);
1122 return 0;
1125 return 1;
1128 #define PCNET32_REGS_PER_PHY 32
1129 #define PCNET32_MAX_PHYS 32
1130 static int pcnet32_get_regs_len(struct net_device *dev)
1132 struct pcnet32_private *lp = dev->priv;
1133 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1135 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1138 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1139 void *ptr)
1141 int i, csr0;
1142 u16 *buff = ptr;
1143 struct pcnet32_private *lp = dev->priv;
1144 struct pcnet32_access *a = &lp->a;
1145 ulong ioaddr = dev->base_addr;
1146 unsigned long flags;
1148 spin_lock_irqsave(&lp->lock, flags);
1150 csr0 = a->read_csr(ioaddr, CSR0);
1151 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1152 pcnet32_suspend(dev, &flags, 1);
1154 /* read address PROM */
1155 for (i = 0; i < 16; i += 2)
1156 *buff++ = inw(ioaddr + i);
1158 /* read control and status registers */
1159 for (i = 0; i < 90; i++) {
1160 *buff++ = a->read_csr(ioaddr, i);
1163 *buff++ = a->read_csr(ioaddr, 112);
1164 *buff++ = a->read_csr(ioaddr, 114);
1166 /* read bus configuration registers */
1167 for (i = 0; i < 30; i++) {
1168 *buff++ = a->read_bcr(ioaddr, i);
1170 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1171 for (i = 31; i < 36; i++) {
1172 *buff++ = a->read_bcr(ioaddr, i);
1175 /* read mii phy registers */
1176 if (lp->mii) {
1177 int j;
1178 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1179 if (lp->phymask & (1 << j)) {
1180 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1181 lp->a.write_bcr(ioaddr, 33,
1182 (j << 5) | i);
1183 *buff++ = lp->a.read_bcr(ioaddr, 34);
1189 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1190 int csr5;
1192 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1193 csr5 = a->read_csr(ioaddr, CSR5);
1194 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1197 spin_unlock_irqrestore(&lp->lock, flags);
1200 static struct ethtool_ops pcnet32_ethtool_ops = {
1201 .get_settings = pcnet32_get_settings,
1202 .set_settings = pcnet32_set_settings,
1203 .get_drvinfo = pcnet32_get_drvinfo,
1204 .get_msglevel = pcnet32_get_msglevel,
1205 .set_msglevel = pcnet32_set_msglevel,
1206 .nway_reset = pcnet32_nway_reset,
1207 .get_link = pcnet32_get_link,
1208 .get_ringparam = pcnet32_get_ringparam,
1209 .set_ringparam = pcnet32_set_ringparam,
1210 .get_tx_csum = ethtool_op_get_tx_csum,
1211 .get_sg = ethtool_op_get_sg,
1212 .get_tso = ethtool_op_get_tso,
1213 .get_strings = pcnet32_get_strings,
1214 .self_test_count = pcnet32_self_test_count,
1215 .self_test = pcnet32_ethtool_test,
1216 .phys_id = pcnet32_phys_id,
1217 .get_regs_len = pcnet32_get_regs_len,
1218 .get_regs = pcnet32_get_regs,
1219 .get_perm_addr = ethtool_op_get_perm_addr,
1220 };
1222 /* only probes for non-PCI devices, the rest are handled by
1223 * pci_register_driver via pcnet32_probe_pci */
1225 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1227 unsigned int *port, ioaddr;
1229 /* search for PCnet32 VLB cards at known addresses */
1230 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1231 if (request_region
1232 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1233 /* check if there is really a pcnet chip on that ioaddr */
1234 if ((inb(ioaddr + 14) == 0x57)
1235 && (inb(ioaddr + 15) == 0x57)) {
1236 pcnet32_probe1(ioaddr, 0, NULL);
1237 } else {
1238 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1244 static int __devinit
1245 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1247 unsigned long ioaddr;
1248 int err;
1250 err = pci_enable_device(pdev);
1251 if (err < 0) {
1252 if (pcnet32_debug & NETIF_MSG_PROBE)
1253 printk(KERN_ERR PFX
1254 "failed to enable device -- err=%d\n", err);
1255 return err;
1257 pci_set_master(pdev);
1259 ioaddr = pci_resource_start(pdev, 0);
1260 if (!ioaddr) {
1261 if (pcnet32_debug & NETIF_MSG_PROBE)
1262 printk(KERN_ERR PFX
1263 "card has no PCI IO resources, aborting\n");
1264 return -ENODEV;
1267 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1268 if (pcnet32_debug & NETIF_MSG_PROBE)
1269 printk(KERN_ERR PFX
1270 "architecture does not support 32bit PCI busmaster DMA\n");
1271 return -ENODEV;
1273 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1274 NULL) {
1275 if (pcnet32_debug & NETIF_MSG_PROBE)
1276 printk(KERN_ERR PFX
1277 "io address range already allocated\n");
1278 return -EBUSY;
1281 err = pcnet32_probe1(ioaddr, 1, pdev);
1282 if (err < 0) {
1283 pci_disable_device(pdev);
1285 return err;
1288 /* pcnet32_probe1
1289 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1290 * pdev will be NULL when called from pcnet32_probe_vlbus.
1291 */
1292 static int __devinit
1293 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1295 struct pcnet32_private *lp;
1296 dma_addr_t lp_dma_addr;
1297 int i, media;
1298 int fdx, mii, fset, dxsuflo;
1299 int chip_version;
1300 char *chipname;
1301 struct net_device *dev;
1302 struct pcnet32_access *a = NULL;
1303 u8 promaddr[6];
1304 int ret = -ENODEV;
1306 /* reset the chip */
1307 pcnet32_wio_reset(ioaddr);
1309 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1310 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1311 a = &pcnet32_wio;
1312 } else {
1313 pcnet32_dwio_reset(ioaddr);
1314 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1315 && pcnet32_dwio_check(ioaddr)) {
1316 a = &pcnet32_dwio;
1317 } else
1318 goto err_release_region;
1321 chip_version =
1322 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1323 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1324 printk(KERN_INFO " PCnet chip version is %#x.\n",
1325 chip_version);
1326 if ((chip_version & 0xfff) != 0x003) {
1327 if (pcnet32_debug & NETIF_MSG_PROBE)
1328 printk(KERN_INFO PFX "Unsupported chip version.\n");
1329 goto err_release_region;
1332 /* initialize variables */
1333 fdx = mii = fset = dxsuflo = 0;
1334 chip_version = (chip_version >> 12) & 0xffff;
1336 switch (chip_version) {
1337 case 0x2420:
1338 chipname = "PCnet/PCI 79C970"; /* PCI */
1339 break;
1340 case 0x2430:
1341 if (shared)
1342 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1343 else
1344 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1345 break;
1346 case 0x2621:
1347 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1348 fdx = 1;
1349 break;
1350 case 0x2623:
1351 chipname = "PCnet/FAST 79C971"; /* PCI */
1352 fdx = 1;
1353 mii = 1;
1354 fset = 1;
1355 break;
1356 case 0x2624:
1357 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1358 fdx = 1;
1359 mii = 1;
1360 fset = 1;
1361 break;
1362 case 0x2625:
1363 chipname = "PCnet/FAST III 79C973"; /* PCI */
1364 fdx = 1;
1365 mii = 1;
1366 break;
1367 case 0x2626:
1368 chipname = "PCnet/Home 79C978"; /* PCI */
1369 fdx = 1;
1370 /*
1371 * This is based on specs published at www.amd.com. This section
1372 * assumes that a card with a 79C978 wants to go into standard
1373 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1374 * and the module option homepna=1 can select this instead.
1375 */
1376 media = a->read_bcr(ioaddr, 49);
1377 media &= ~3; /* default to 10Mb ethernet */
1378 if (cards_found < MAX_UNITS && homepna[cards_found])
1379 media |= 1; /* switch to home wiring mode */
1380 if (pcnet32_debug & NETIF_MSG_PROBE)
1381 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1382 (media & 1) ? "1" : "10");
1383 a->write_bcr(ioaddr, 49, media);
1384 break;
1385 case 0x2627:
1386 chipname = "PCnet/FAST III 79C975"; /* PCI */
1387 fdx = 1;
1388 mii = 1;
1389 break;
1390 case 0x2628:
1391 chipname = "PCnet/PRO 79C976";
1392 fdx = 1;
1393 mii = 1;
1394 break;
1395 default:
1396 if (pcnet32_debug & NETIF_MSG_PROBE)
1397 printk(KERN_INFO PFX
1398 "PCnet version %#x, no PCnet32 chip.\n",
1399 chip_version);
1400 goto err_release_region;
1403 /*
1404 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1405 * starting until the packet is loaded. Strike one for reliability, lose
1406 * one for latency - although on PCI this isnt a big loss. Older chips
1407 * have FIFO's smaller than a packet, so you can't do this.
1408 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1409 */
1411 if (fset) {
1412 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1413 a->write_csr(ioaddr, 80,
1414 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1415 dxsuflo = 1;
1418 dev = alloc_etherdev(0);
1419 if (!dev) {
1420 if (pcnet32_debug & NETIF_MSG_PROBE)
1421 printk(KERN_ERR PFX "Memory allocation failed.\n");
1422 ret = -ENOMEM;
1423 goto err_release_region;
1425 SET_NETDEV_DEV(dev, &pdev->dev);
1427 if (pcnet32_debug & NETIF_MSG_PROBE)
1428 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1430 /* In most chips, after a chip reset, the ethernet address is read from the
1431 * station address PROM at the base address and programmed into the
1432 * "Physical Address Registers" CSR12-14.
1433 * As a precautionary measure, we read the PROM values and complain if
1434 * they disagree with the CSRs. If they miscompare, and the PROM addr
1435 * is valid, then the PROM addr is used.
1436 */
1437 for (i = 0; i < 3; i++) {
1438 unsigned int val;
1439 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1440 /* There may be endianness issues here. */
1441 dev->dev_addr[2 * i] = val & 0x0ff;
1442 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1445 /* read PROM address and compare with CSR address */
1446 for (i = 0; i < 6; i++)
1447 promaddr[i] = inb(ioaddr + i);
1449 if (memcmp(promaddr, dev->dev_addr, 6)
1450 || !is_valid_ether_addr(dev->dev_addr)) {
1451 if (is_valid_ether_addr(promaddr)) {
1452 if (pcnet32_debug & NETIF_MSG_PROBE) {
1453 printk(" warning: CSR address invalid,\n");
1454 printk(KERN_INFO
1455 " using instead PROM address of");
1457 memcpy(dev->dev_addr, promaddr, 6);
1460 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1462 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1463 if (!is_valid_ether_addr(dev->perm_addr))
1464 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1466 if (pcnet32_debug & NETIF_MSG_PROBE) {
1467 for (i = 0; i < 6; i++)
1468 printk(" %2.2x", dev->dev_addr[i]);
1470 /* Version 0x2623 and 0x2624 */
1471 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1472 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1473 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1474 switch (i >> 10) {
1475 case 0:
1476 printk(" 20 bytes,");
1477 break;
1478 case 1:
1479 printk(" 64 bytes,");
1480 break;
1481 case 2:
1482 printk(" 128 bytes,");
1483 break;
1484 case 3:
1485 printk("~220 bytes,");
1486 break;
1488 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1489 printk(" BCR18(%x):", i & 0xffff);
1490 if (i & (1 << 5))
1491 printk("BurstWrEn ");
1492 if (i & (1 << 6))
1493 printk("BurstRdEn ");
1494 if (i & (1 << 7))
1495 printk("DWordIO ");
1496 if (i & (1 << 11))
1497 printk("NoUFlow ");
1498 i = a->read_bcr(ioaddr, 25);
1499 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1500 i = a->read_bcr(ioaddr, 26);
1501 printk(" SRAM_BND=0x%04x,", i << 8);
1502 i = a->read_bcr(ioaddr, 27);
1503 if (i & (1 << 14))
1504 printk("LowLatRx");
1508 dev->base_addr = ioaddr;
1509 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1510 if ((lp =
1511 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1512 if (pcnet32_debug & NETIF_MSG_PROBE)
1513 printk(KERN_ERR PFX
1514 "Consistent memory allocation failed.\n");
1515 ret = -ENOMEM;
1516 goto err_free_netdev;
1519 memset(lp, 0, sizeof(*lp));
1520 lp->dma_addr = lp_dma_addr;
1521 lp->pci_dev = pdev;
1523 spin_lock_init(&lp->lock);
1525 SET_MODULE_OWNER(dev);
1526 SET_NETDEV_DEV(dev, &pdev->dev);
1527 dev->priv = lp;
1528 lp->name = chipname;
1529 lp->shared_irq = shared;
1530 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1531 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1532 lp->tx_mod_mask = lp->tx_ring_size - 1;
1533 lp->rx_mod_mask = lp->rx_ring_size - 1;
1534 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1535 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1536 lp->mii_if.full_duplex = fdx;
1537 lp->mii_if.phy_id_mask = 0x1f;
1538 lp->mii_if.reg_num_mask = 0x1f;
1539 lp->dxsuflo = dxsuflo;
1540 lp->mii = mii;
1541 lp->chip_version = chip_version;
1542 lp->msg_enable = pcnet32_debug;
1543 if ((cards_found >= MAX_UNITS)
1544 || (options[cards_found] > sizeof(options_mapping)))
1545 lp->options = PCNET32_PORT_ASEL;
1546 else
1547 lp->options = options_mapping[options[cards_found]];
1548 lp->mii_if.dev = dev;
1549 lp->mii_if.mdio_read = mdio_read;
1550 lp->mii_if.mdio_write = mdio_write;
1552 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1553 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1554 lp->options |= PCNET32_PORT_FD;
1556 if (!a) {
1557 if (pcnet32_debug & NETIF_MSG_PROBE)
1558 printk(KERN_ERR PFX "No access methods\n");
1559 ret = -ENODEV;
1560 goto err_free_consistent;
1562 lp->a = *a;
1564 /* prior to register_netdev, dev->name is not yet correct */
1565 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1566 ret = -ENOMEM;
1567 goto err_free_ring;
1569 /* detect special T1/E1 WAN card by checking for MAC address */
1570 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1571 && dev->dev_addr[2] == 0x75)
1572 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1574 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1575 lp->init_block.tlen_rlen =
1576 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1577 for (i = 0; i < 6; i++)
1578 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1579 lp->init_block.filter[0] = 0x00000000;
1580 lp->init_block.filter[1] = 0x00000000;
1581 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1582 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1584 /* switch pcnet32 to 32bit mode */
1585 a->write_bcr(ioaddr, 20, 2);
1587 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1588 init_block)) & 0xffff);
1589 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1590 init_block)) >> 16);
1592 if (pdev) { /* use the IRQ provided by PCI */
1593 dev->irq = pdev->irq;
1594 if (pcnet32_debug & NETIF_MSG_PROBE)
1595 printk(" assigned IRQ %d.\n", dev->irq);
1596 } else {
1597 unsigned long irq_mask = probe_irq_on();
1599 /*
1600 * To auto-IRQ we enable the initialization-done and DMA error
1601 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1602 * boards will work.
1603 */
1604 /* Trigger an initialization just for the interrupt. */
1605 a->write_csr(ioaddr, 0, 0x41);
1606 mdelay(1);
1608 dev->irq = probe_irq_off(irq_mask);
1609 if (!dev->irq) {
1610 if (pcnet32_debug & NETIF_MSG_PROBE)
1611 printk(", failed to detect IRQ line.\n");
1612 ret = -ENODEV;
1613 goto err_free_ring;
1615 if (pcnet32_debug & NETIF_MSG_PROBE)
1616 printk(", probed IRQ %d.\n", dev->irq);
1619 /* Set the mii phy_id so that we can query the link state */
1620 if (lp->mii) {
1621 /* lp->phycount and lp->phymask are set to 0 by memset above */
1623 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1624 /* scan for PHYs */
1625 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1626 unsigned short id1, id2;
1628 id1 = mdio_read(dev, i, MII_PHYSID1);
1629 if (id1 == 0xffff)
1630 continue;
1631 id2 = mdio_read(dev, i, MII_PHYSID2);
1632 if (id2 == 0xffff)
1633 continue;
1634 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1635 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1636 lp->phycount++;
1637 lp->phymask |= (1 << i);
1638 lp->mii_if.phy_id = i;
1639 if (pcnet32_debug & NETIF_MSG_PROBE)
1640 printk(KERN_INFO PFX
1641 "Found PHY %04x:%04x at address %d.\n",
1642 id1, id2, i);
1644 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1645 if (lp->phycount > 1) {
1646 lp->options |= PCNET32_PORT_MII;
1650 init_timer(&lp->watchdog_timer);
1651 lp->watchdog_timer.data = (unsigned long)dev;
1652 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1654 /* The PCNET32-specific entries in the device structure. */
1655 dev->open = &pcnet32_open;
1656 dev->hard_start_xmit = &pcnet32_start_xmit;
1657 dev->stop = &pcnet32_close;
1658 dev->get_stats = &pcnet32_get_stats;
1659 dev->set_multicast_list = &pcnet32_set_multicast_list;
1660 dev->do_ioctl = &pcnet32_ioctl;
1661 dev->ethtool_ops = &pcnet32_ethtool_ops;
1662 dev->tx_timeout = pcnet32_tx_timeout;
1663 dev->watchdog_timeo = (5 * HZ);
1665 #ifdef CONFIG_NET_POLL_CONTROLLER
1666 dev->poll_controller = pcnet32_poll_controller;
1667 #endif
1669 /* Fill in the generic fields of the device structure. */
1670 if (register_netdev(dev))
1671 goto err_free_ring;
1673 if (pdev) {
1674 pci_set_drvdata(pdev, dev);
1675 } else {
1676 lp->next = pcnet32_dev;
1677 pcnet32_dev = dev;
1680 if (pcnet32_debug & NETIF_MSG_PROBE)
1681 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1682 cards_found++;
1684 /* enable LED writes */
1685 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1687 return 0;
1689 err_free_ring:
1690 pcnet32_free_ring(dev);
1691 err_free_consistent:
1692 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1693 err_free_netdev:
1694 free_netdev(dev);
1695 err_release_region:
1696 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1697 return ret;
1700 /* if any allocation fails, caller must also call pcnet32_free_ring */
1701 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1703 struct pcnet32_private *lp = dev->priv;
1705 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1706 sizeof(struct pcnet32_tx_head) *
1707 lp->tx_ring_size,
1708 &lp->tx_ring_dma_addr);
1709 if (lp->tx_ring == NULL) {
1710 if (netif_msg_drv(lp))
1711 printk("\n" KERN_ERR PFX
1712 "%s: Consistent memory allocation failed.\n",
1713 name);
1714 return -ENOMEM;
1717 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1718 sizeof(struct pcnet32_rx_head) *
1719 lp->rx_ring_size,
1720 &lp->rx_ring_dma_addr);
1721 if (lp->rx_ring == NULL) {
1722 if (netif_msg_drv(lp))
1723 printk("\n" KERN_ERR PFX
1724 "%s: Consistent memory allocation failed.\n",
1725 name);
1726 return -ENOMEM;
1729 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1730 GFP_ATOMIC);
1731 if (!lp->tx_dma_addr) {
1732 if (netif_msg_drv(lp))
1733 printk("\n" KERN_ERR PFX
1734 "%s: Memory allocation failed.\n", name);
1735 return -ENOMEM;
1738 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1739 GFP_ATOMIC);
1740 if (!lp->rx_dma_addr) {
1741 if (netif_msg_drv(lp))
1742 printk("\n" KERN_ERR PFX
1743 "%s: Memory allocation failed.\n", name);
1744 return -ENOMEM;
1747 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1748 GFP_ATOMIC);
1749 if (!lp->tx_skbuff) {
1750 if (netif_msg_drv(lp))
1751 printk("\n" KERN_ERR PFX
1752 "%s: Memory allocation failed.\n", name);
1753 return -ENOMEM;
1756 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1757 GFP_ATOMIC);
1758 if (!lp->rx_skbuff) {
1759 if (netif_msg_drv(lp))
1760 printk("\n" KERN_ERR PFX
1761 "%s: Memory allocation failed.\n", name);
1762 return -ENOMEM;
1765 return 0;
1768 static void pcnet32_free_ring(struct net_device *dev)
1770 struct pcnet32_private *lp = dev->priv;
1772 kfree(lp->tx_skbuff);
1773 lp->tx_skbuff = NULL;
1775 kfree(lp->rx_skbuff);
1776 lp->rx_skbuff = NULL;
1778 kfree(lp->tx_dma_addr);
1779 lp->tx_dma_addr = NULL;
1781 kfree(lp->rx_dma_addr);
1782 lp->rx_dma_addr = NULL;
1784 if (lp->tx_ring) {
1785 pci_free_consistent(lp->pci_dev,
1786 sizeof(struct pcnet32_tx_head) *
1787 lp->tx_ring_size, lp->tx_ring,
1788 lp->tx_ring_dma_addr);
1789 lp->tx_ring = NULL;
1792 if (lp->rx_ring) {
1793 pci_free_consistent(lp->pci_dev,
1794 sizeof(struct pcnet32_rx_head) *
1795 lp->rx_ring_size, lp->rx_ring,
1796 lp->rx_ring_dma_addr);
1797 lp->rx_ring = NULL;
1801 static int pcnet32_open(struct net_device *dev)
1803 struct pcnet32_private *lp = dev->priv;
1804 unsigned long ioaddr = dev->base_addr;
1805 u16 val;
1806 int i;
1807 int rc;
1808 unsigned long flags;
1810 if (request_irq(dev->irq, &pcnet32_interrupt,
1811 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
1812 (void *)dev)) {
1813 return -EAGAIN;
1816 spin_lock_irqsave(&lp->lock, flags);
1817 /* Check for a valid station address */
1818 if (!is_valid_ether_addr(dev->dev_addr)) {
1819 rc = -EINVAL;
1820 goto err_free_irq;
1823 /* Reset the PCNET32 */
1824 lp->a.reset(ioaddr);
1826 /* switch pcnet32 to 32bit mode */
1827 lp->a.write_bcr(ioaddr, 20, 2);
1829 if (netif_msg_ifup(lp))
1830 printk(KERN_DEBUG
1831 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1832 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
1833 (u32) (lp->rx_ring_dma_addr),
1834 (u32) (lp->dma_addr +
1835 offsetof(struct pcnet32_private, init_block)));
1837 /* set/reset autoselect bit */
1838 val = lp->a.read_bcr(ioaddr, 2) & ~2;
1839 if (lp->options & PCNET32_PORT_ASEL)
1840 val |= 2;
1841 lp->a.write_bcr(ioaddr, 2, val);
1843 /* handle full duplex setting */
1844 if (lp->mii_if.full_duplex) {
1845 val = lp->a.read_bcr(ioaddr, 9) & ~3;
1846 if (lp->options & PCNET32_PORT_FD) {
1847 val |= 1;
1848 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1849 val |= 2;
1850 } else if (lp->options & PCNET32_PORT_ASEL) {
1851 /* workaround of xSeries250, turn on for 79C975 only */
1852 if (lp->chip_version == 0x2627)
1853 val |= 3;
1855 lp->a.write_bcr(ioaddr, 9, val);
1858 /* set/reset GPSI bit in test register */
1859 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
1860 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1861 val |= 0x10;
1862 lp->a.write_csr(ioaddr, 124, val);
1864 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1865 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
1866 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1867 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
1868 if (lp->options & PCNET32_PORT_ASEL) {
1869 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1870 if (netif_msg_link(lp))
1871 printk(KERN_DEBUG
1872 "%s: Setting 100Mb-Full Duplex.\n",
1873 dev->name);
1876 if (lp->phycount < 2) {
1877 /*
1878 * 24 Jun 2004 according AMD, in order to change the PHY,
1879 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1880 * duplex, and/or enable auto negotiation, and clear DANAS
1881 */
1882 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1883 lp->a.write_bcr(ioaddr, 32,
1884 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1885 /* disable Auto Negotiation, set 10Mpbs, HD */
1886 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1887 if (lp->options & PCNET32_PORT_FD)
1888 val |= 0x10;
1889 if (lp->options & PCNET32_PORT_100)
1890 val |= 0x08;
1891 lp->a.write_bcr(ioaddr, 32, val);
1892 } else {
1893 if (lp->options & PCNET32_PORT_ASEL) {
1894 lp->a.write_bcr(ioaddr, 32,
1895 lp->a.read_bcr(ioaddr,
1896 32) | 0x0080);
1897 /* enable auto negotiate, setup, disable fd */
1898 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1899 val |= 0x20;
1900 lp->a.write_bcr(ioaddr, 32, val);
1903 } else {
1904 int first_phy = -1;
1905 u16 bmcr;
1906 u32 bcr9;
1907 struct ethtool_cmd ecmd;
1909 /*
1910 * There is really no good other way to handle multiple PHYs
1911 * other than turning off all automatics
1912 */
1913 val = lp->a.read_bcr(ioaddr, 2);
1914 lp->a.write_bcr(ioaddr, 2, val & ~2);
1915 val = lp->a.read_bcr(ioaddr, 32);
1916 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
1918 if (!(lp->options & PCNET32_PORT_ASEL)) {
1919 /* setup ecmd */
1920 ecmd.port = PORT_MII;
1921 ecmd.transceiver = XCVR_INTERNAL;
1922 ecmd.autoneg = AUTONEG_DISABLE;
1923 ecmd.speed =
1924 lp->
1925 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1926 bcr9 = lp->a.read_bcr(ioaddr, 9);
1928 if (lp->options & PCNET32_PORT_FD) {
1929 ecmd.duplex = DUPLEX_FULL;
1930 bcr9 |= (1 << 0);
1931 } else {
1932 ecmd.duplex = DUPLEX_HALF;
1933 bcr9 |= ~(1 << 0);
1935 lp->a.write_bcr(ioaddr, 9, bcr9);
1938 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1939 if (lp->phymask & (1 << i)) {
1940 /* isolate all but the first PHY */
1941 bmcr = mdio_read(dev, i, MII_BMCR);
1942 if (first_phy == -1) {
1943 first_phy = i;
1944 mdio_write(dev, i, MII_BMCR,
1945 bmcr & ~BMCR_ISOLATE);
1946 } else {
1947 mdio_write(dev, i, MII_BMCR,
1948 bmcr | BMCR_ISOLATE);
1950 /* use mii_ethtool_sset to setup PHY */
1951 lp->mii_if.phy_id = i;
1952 ecmd.phy_address = i;
1953 if (lp->options & PCNET32_PORT_ASEL) {
1954 mii_ethtool_gset(&lp->mii_if, &ecmd);
1955 ecmd.autoneg = AUTONEG_ENABLE;
1957 mii_ethtool_sset(&lp->mii_if, &ecmd);
1960 lp->mii_if.phy_id = first_phy;
1961 if (netif_msg_link(lp))
1962 printk(KERN_INFO "%s: Using PHY number %d.\n",
1963 dev->name, first_phy);
1966 #ifdef DO_DXSUFLO
1967 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1968 val = lp->a.read_csr(ioaddr, 3);
1969 val |= 0x40;
1970 lp->a.write_csr(ioaddr, 3, val);
1972 #endif
1974 lp->init_block.mode =
1975 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1976 pcnet32_load_multicast(dev);
1978 if (pcnet32_init_ring(dev)) {
1979 rc = -ENOMEM;
1980 goto err_free_ring;
1983 /* Re-initialize the PCNET32, and start it when done. */
1984 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
1985 offsetof(struct pcnet32_private,
1986 init_block)) & 0xffff);
1987 lp->a.write_csr(ioaddr, 2,
1988 (lp->dma_addr +
1989 offsetof(struct pcnet32_private, init_block)) >> 16);
1991 lp->a.write_csr(ioaddr, 4, 0x0915);
1992 lp->a.write_csr(ioaddr, 0, 0x0001);
1994 netif_start_queue(dev);
1996 if (lp->chip_version >= PCNET32_79C970A) {
1997 /* Print the link status and start the watchdog */
1998 pcnet32_check_media(dev, 1);
1999 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2002 i = 0;
2003 while (i++ < 100)
2004 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
2005 break;
2006 /*
2007 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2008 * reports that doing so triggers a bug in the '974.
2009 */
2010 lp->a.write_csr(ioaddr, 0, 0x0042);
2012 if (netif_msg_ifup(lp))
2013 printk(KERN_DEBUG
2014 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2015 dev->name, i,
2016 (u32) (lp->dma_addr +
2017 offsetof(struct pcnet32_private, init_block)),
2018 lp->a.read_csr(ioaddr, 0));
2020 spin_unlock_irqrestore(&lp->lock, flags);
2022 return 0; /* Always succeed */
2024 err_free_ring:
2025 /* free any allocated skbuffs */
2026 pcnet32_purge_rx_ring(dev);
2028 /*
2029 * Switch back to 16bit mode to avoid problems with dumb
2030 * DOS packet driver after a warm reboot
2031 */
2032 lp->a.write_bcr(ioaddr, 20, 4);
2034 err_free_irq:
2035 spin_unlock_irqrestore(&lp->lock, flags);
2036 free_irq(dev->irq, dev);
2037 return rc;
2040 /*
2041 * The LANCE has been halted for one reason or another (busmaster memory
2042 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2043 * etc.). Modern LANCE variants always reload their ring-buffer
2044 * configuration when restarted, so we must reinitialize our ring
2045 * context before restarting. As part of this reinitialization,
2046 * find all packets still on the Tx ring and pretend that they had been
2047 * sent (in effect, drop the packets on the floor) - the higher-level
2048 * protocols will time out and retransmit. It'd be better to shuffle
2049 * these skbs to a temp list and then actually re-Tx them after
2050 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2051 */
2053 static void pcnet32_purge_tx_ring(struct net_device *dev)
2055 struct pcnet32_private *lp = dev->priv;
2056 int i;
2058 for (i = 0; i < lp->tx_ring_size; i++) {
2059 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2060 wmb(); /* Make sure adapter sees owner change */
2061 if (lp->tx_skbuff[i]) {
2062 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2063 lp->tx_skbuff[i]->len,
2064 PCI_DMA_TODEVICE);
2065 dev_kfree_skb_any(lp->tx_skbuff[i]);
2067 lp->tx_skbuff[i] = NULL;
2068 lp->tx_dma_addr[i] = 0;
2072 /* Initialize the PCNET32 Rx and Tx rings. */
2073 static int pcnet32_init_ring(struct net_device *dev)
2075 struct pcnet32_private *lp = dev->priv;
2076 int i;
2078 lp->tx_full = 0;
2079 lp->cur_rx = lp->cur_tx = 0;
2080 lp->dirty_rx = lp->dirty_tx = 0;
2082 for (i = 0; i < lp->rx_ring_size; i++) {
2083 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2084 if (rx_skbuff == NULL) {
2085 if (!
2086 (rx_skbuff = lp->rx_skbuff[i] =
2087 dev_alloc_skb(PKT_BUF_SZ))) {
2088 /* there is not much, we can do at this point */
2089 if (pcnet32_debug & NETIF_MSG_DRV)
2090 printk(KERN_ERR
2091 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2092 dev->name);
2093 return -1;
2095 skb_reserve(rx_skbuff, 2);
2098 rmb();
2099 if (lp->rx_dma_addr[i] == 0)
2100 lp->rx_dma_addr[i] =
2101 pci_map_single(lp->pci_dev, rx_skbuff->data,
2102 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2103 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2104 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2105 wmb(); /* Make sure owner changes after all others are visible */
2106 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2108 /* The Tx buffer address is filled in as needed, but we do need to clear
2109 * the upper ownership bit. */
2110 for (i = 0; i < lp->tx_ring_size; i++) {
2111 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2112 wmb(); /* Make sure adapter sees owner change */
2113 lp->tx_ring[i].base = 0;
2114 lp->tx_dma_addr[i] = 0;
2117 lp->init_block.tlen_rlen =
2118 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2119 for (i = 0; i < 6; i++)
2120 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2121 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2122 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2123 wmb(); /* Make sure all changes are visible */
2124 return 0;
2127 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2128 * then flush the pending transmit operations, re-initialize the ring,
2129 * and tell the chip to initialize.
2130 */
2131 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2133 struct pcnet32_private *lp = dev->priv;
2134 unsigned long ioaddr = dev->base_addr;
2135 int i;
2137 /* wait for stop */
2138 for (i = 0; i < 100; i++)
2139 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
2140 break;
2142 if (i >= 100 && netif_msg_drv(lp))
2143 printk(KERN_ERR
2144 "%s: pcnet32_restart timed out waiting for stop.\n",
2145 dev->name);
2147 pcnet32_purge_tx_ring(dev);
2148 if (pcnet32_init_ring(dev))
2149 return;
2151 /* ReInit Ring */
2152 lp->a.write_csr(ioaddr, 0, 1);
2153 i = 0;
2154 while (i++ < 1000)
2155 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
2156 break;
2158 lp->a.write_csr(ioaddr, 0, csr0_bits);
2161 static void pcnet32_tx_timeout(struct net_device *dev)
2163 struct pcnet32_private *lp = dev->priv;
2164 unsigned long ioaddr = dev->base_addr, flags;
2166 spin_lock_irqsave(&lp->lock, flags);
2167 /* Transmitter timeout, serious problems. */
2168 if (pcnet32_debug & NETIF_MSG_DRV)
2169 printk(KERN_ERR
2170 "%s: transmit timed out, status %4.4x, resetting.\n",
2171 dev->name, lp->a.read_csr(ioaddr, 0));
2172 lp->a.write_csr(ioaddr, 0, 0x0004);
2173 lp->stats.tx_errors++;
2174 if (netif_msg_tx_err(lp)) {
2175 int i;
2176 printk(KERN_DEBUG
2177 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2178 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2179 lp->cur_rx);
2180 for (i = 0; i < lp->rx_ring_size; i++)
2181 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2182 le32_to_cpu(lp->rx_ring[i].base),
2183 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2184 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2185 le16_to_cpu(lp->rx_ring[i].status));
2186 for (i = 0; i < lp->tx_ring_size; i++)
2187 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2188 le32_to_cpu(lp->tx_ring[i].base),
2189 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2190 le32_to_cpu(lp->tx_ring[i].misc),
2191 le16_to_cpu(lp->tx_ring[i].status));
2192 printk("\n");
2194 pcnet32_restart(dev, 0x0042);
2196 dev->trans_start = jiffies;
2197 netif_wake_queue(dev);
2199 spin_unlock_irqrestore(&lp->lock, flags);
2202 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2204 struct pcnet32_private *lp = dev->priv;
2205 unsigned long ioaddr = dev->base_addr;
2206 u16 status;
2207 int entry;
2208 unsigned long flags;
2210 spin_lock_irqsave(&lp->lock, flags);
2212 if (netif_msg_tx_queued(lp)) {
2213 printk(KERN_DEBUG
2214 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2215 dev->name, lp->a.read_csr(ioaddr, 0));
2218 /* Default status -- will not enable Successful-TxDone
2219 * interrupt when that option is available to us.
2220 */
2221 status = 0x8300;
2223 /* Fill in a Tx ring entry */
2225 /* Mask to ring buffer boundary. */
2226 entry = lp->cur_tx & lp->tx_mod_mask;
2228 /* Caution: the write order is important here, set the status
2229 * with the "ownership" bits last. */
2231 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2233 lp->tx_ring[entry].misc = 0x00000000;
2235 lp->tx_skbuff[entry] = skb;
2236 lp->tx_dma_addr[entry] =
2237 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2238 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2239 wmb(); /* Make sure owner changes after all others are visible */
2240 lp->tx_ring[entry].status = le16_to_cpu(status);
2242 lp->cur_tx++;
2243 lp->stats.tx_bytes += skb->len;
2245 /* Trigger an immediate send poll. */
2246 lp->a.write_csr(ioaddr, 0, 0x0048);
2248 dev->trans_start = jiffies;
2250 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2251 lp->tx_full = 1;
2252 netif_stop_queue(dev);
2254 spin_unlock_irqrestore(&lp->lock, flags);
2255 return 0;
2258 /* The PCNET32 interrupt handler. */
2259 static irqreturn_t
2260 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2262 struct net_device *dev = dev_id;
2263 struct pcnet32_private *lp;
2264 unsigned long ioaddr;
2265 u16 csr0, rap;
2266 int boguscnt = max_interrupt_work;
2267 int must_restart;
2269 if (!dev) {
2270 if (pcnet32_debug & NETIF_MSG_INTR)
2271 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2272 __FUNCTION__, irq);
2273 return IRQ_NONE;
2276 ioaddr = dev->base_addr;
2277 lp = dev->priv;
2279 spin_lock(&lp->lock);
2281 rap = lp->a.read_rap(ioaddr);
2282 while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2283 if (csr0 == 0xffff) {
2284 break; /* PCMCIA remove happened */
2286 /* Acknowledge all of the current interrupt sources ASAP. */
2287 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2289 must_restart = 0;
2291 if (netif_msg_intr(lp))
2292 printk(KERN_DEBUG
2293 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2294 dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2296 if (csr0 & 0x0400) /* Rx interrupt */
2297 pcnet32_rx(dev);
2299 if (csr0 & 0x0200) { /* Tx-done interrupt */
2300 unsigned int dirty_tx = lp->dirty_tx;
2301 int delta;
2303 while (dirty_tx != lp->cur_tx) {
2304 int entry = dirty_tx & lp->tx_mod_mask;
2305 int status =
2306 (short)le16_to_cpu(lp->tx_ring[entry].
2307 status);
2309 if (status < 0)
2310 break; /* It still hasn't been Txed */
2312 lp->tx_ring[entry].base = 0;
2314 if (status & 0x4000) {
2315 /* There was an major error, log it. */
2316 int err_status =
2317 le32_to_cpu(lp->tx_ring[entry].
2318 misc);
2319 lp->stats.tx_errors++;
2320 if (netif_msg_tx_err(lp))
2321 printk(KERN_ERR
2322 "%s: Tx error status=%04x err_status=%08x\n",
2323 dev->name, status,
2324 err_status);
2325 if (err_status & 0x04000000)
2326 lp->stats.tx_aborted_errors++;
2327 if (err_status & 0x08000000)
2328 lp->stats.tx_carrier_errors++;
2329 if (err_status & 0x10000000)
2330 lp->stats.tx_window_errors++;
2331 #ifndef DO_DXSUFLO
2332 if (err_status & 0x40000000) {
2333 lp->stats.tx_fifo_errors++;
2334 /* Ackk! On FIFO errors the Tx unit is turned off! */
2335 /* Remove this verbosity later! */
2336 if (netif_msg_tx_err(lp))
2337 printk(KERN_ERR
2338 "%s: Tx FIFO error! CSR0=%4.4x\n",
2339 dev->name, csr0);
2340 must_restart = 1;
2342 #else
2343 if (err_status & 0x40000000) {
2344 lp->stats.tx_fifo_errors++;
2345 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
2346 /* Ackk! On FIFO errors the Tx unit is turned off! */
2347 /* Remove this verbosity later! */
2348 if (netif_msg_tx_err
2349 (lp))
2350 printk(KERN_ERR
2351 "%s: Tx FIFO error! CSR0=%4.4x\n",
2352 dev->
2353 name,
2354 csr0);
2355 must_restart = 1;
2358 #endif
2359 } else {
2360 if (status & 0x1800)
2361 lp->stats.collisions++;
2362 lp->stats.tx_packets++;
2365 /* We must free the original skb */
2366 if (lp->tx_skbuff[entry]) {
2367 pci_unmap_single(lp->pci_dev,
2368 lp->tx_dma_addr[entry],
2369 lp->tx_skbuff[entry]->
2370 len, PCI_DMA_TODEVICE);
2371 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2372 lp->tx_skbuff[entry] = NULL;
2373 lp->tx_dma_addr[entry] = 0;
2375 dirty_tx++;
2378 delta =
2379 (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
2380 lp->tx_ring_size);
2381 if (delta > lp->tx_ring_size) {
2382 if (netif_msg_drv(lp))
2383 printk(KERN_ERR
2384 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2385 dev->name, dirty_tx, lp->cur_tx,
2386 lp->tx_full);
2387 dirty_tx += lp->tx_ring_size;
2388 delta -= lp->tx_ring_size;
2391 if (lp->tx_full &&
2392 netif_queue_stopped(dev) &&
2393 delta < lp->tx_ring_size - 2) {
2394 /* The ring is no longer full, clear tbusy. */
2395 lp->tx_full = 0;
2396 netif_wake_queue(dev);
2398 lp->dirty_tx = dirty_tx;
2401 /* Log misc errors. */
2402 if (csr0 & 0x4000)
2403 lp->stats.tx_errors++; /* Tx babble. */
2404 if (csr0 & 0x1000) {
2405 /*
2406 * this happens when our receive ring is full. This shouldn't
2407 * be a problem as we will see normal rx interrupts for the frames
2408 * in the receive ring. But there are some PCI chipsets (I can
2409 * reproduce this on SP3G with Intel saturn chipset) which have
2410 * sometimes problems and will fill up the receive ring with
2411 * error descriptors. In this situation we don't get a rx
2412 * interrupt, but a missed frame interrupt sooner or later.
2413 * So we try to clean up our receive ring here.
2414 */
2415 pcnet32_rx(dev);
2416 lp->stats.rx_errors++; /* Missed a Rx frame. */
2418 if (csr0 & 0x0800) {
2419 if (netif_msg_drv(lp))
2420 printk(KERN_ERR
2421 "%s: Bus master arbitration failure, status %4.4x.\n",
2422 dev->name, csr0);
2423 /* unlike for the lance, there is no restart needed */
2426 if (must_restart) {
2427 /* reset the chip to clear the error condition, then restart */
2428 lp->a.reset(ioaddr);
2429 lp->a.write_csr(ioaddr, 4, 0x0915);
2430 pcnet32_restart(dev, 0x0002);
2431 netif_wake_queue(dev);
2435 /* Set interrupt enable. */
2436 lp->a.write_csr(ioaddr, 0, 0x0040);
2437 lp->a.write_rap(ioaddr, rap);
2439 if (netif_msg_intr(lp))
2440 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2441 dev->name, lp->a.read_csr(ioaddr, 0));
2443 spin_unlock(&lp->lock);
2445 return IRQ_HANDLED;
2448 static int pcnet32_rx(struct net_device *dev)
2450 struct pcnet32_private *lp = dev->priv;
2451 int entry = lp->cur_rx & lp->rx_mod_mask;
2452 int boguscnt = lp->rx_ring_size / 2;
2454 /* If we own the next entry, it's a new packet. Send it up. */
2455 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2456 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2458 if (status != 0x03) { /* There was an error. */
2459 /*
2460 * There is a tricky error noted by John Murphy,
2461 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2462 * buffers it's possible for a jabber packet to use two
2463 * buffers, with only the last correctly noting the error.
2464 */
2465 if (status & 0x01) /* Only count a general error at the */
2466 lp->stats.rx_errors++; /* end of a packet. */
2467 if (status & 0x20)
2468 lp->stats.rx_frame_errors++;
2469 if (status & 0x10)
2470 lp->stats.rx_over_errors++;
2471 if (status & 0x08)
2472 lp->stats.rx_crc_errors++;
2473 if (status & 0x04)
2474 lp->stats.rx_fifo_errors++;
2475 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
2476 } else {
2477 /* Malloc up new buffer, compatible with net-2e. */
2478 short pkt_len =
2479 (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
2480 - 4;
2481 struct sk_buff *skb;
2483 /* Discard oversize frames. */
2484 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2485 if (netif_msg_drv(lp))
2486 printk(KERN_ERR
2487 "%s: Impossible packet size %d!\n",
2488 dev->name, pkt_len);
2489 lp->stats.rx_errors++;
2490 } else if (pkt_len < 60) {
2491 if (netif_msg_rx_err(lp))
2492 printk(KERN_ERR "%s: Runt packet!\n",
2493 dev->name);
2494 lp->stats.rx_errors++;
2495 } else {
2496 int rx_in_place = 0;
2498 if (pkt_len > rx_copybreak) {
2499 struct sk_buff *newskb;
2501 if ((newskb =
2502 dev_alloc_skb(PKT_BUF_SZ))) {
2503 skb_reserve(newskb, 2);
2504 skb = lp->rx_skbuff[entry];
2505 pci_unmap_single(lp->pci_dev,
2506 lp->
2507 rx_dma_addr
2508 [entry],
2509 PKT_BUF_SZ - 2,
2510 PCI_DMA_FROMDEVICE);
2511 skb_put(skb, pkt_len);
2512 lp->rx_skbuff[entry] = newskb;
2513 newskb->dev = dev;
2514 lp->rx_dma_addr[entry] =
2515 pci_map_single(lp->pci_dev,
2516 newskb->data,
2517 PKT_BUF_SZ -
2518 2,
2519 PCI_DMA_FROMDEVICE);
2520 lp->rx_ring[entry].base =
2521 le32_to_cpu(lp->
2522 rx_dma_addr
2523 [entry]);
2524 rx_in_place = 1;
2525 } else
2526 skb = NULL;
2527 } else {
2528 skb = dev_alloc_skb(pkt_len + 2);
2531 if (skb == NULL) {
2532 int i;
2533 if (netif_msg_drv(lp))
2534 printk(KERN_ERR
2535 "%s: Memory squeeze, deferring packet.\n",
2536 dev->name);
2537 for (i = 0; i < lp->rx_ring_size; i++)
2538 if ((short)
2539 le16_to_cpu(lp->
2540 rx_ring[(entry +
2541 i)
2542 & lp->
2543 rx_mod_mask].
2544 status) < 0)
2545 break;
2547 if (i > lp->rx_ring_size - 2) {
2548 lp->stats.rx_dropped++;
2549 lp->rx_ring[entry].status |=
2550 le16_to_cpu(0x8000);
2551 wmb(); /* Make sure adapter sees owner change */
2552 lp->cur_rx++;
2554 break;
2556 skb->dev = dev;
2557 if (!rx_in_place) {
2558 skb_reserve(skb, 2); /* 16 byte align */
2559 skb_put(skb, pkt_len); /* Make room */
2560 pci_dma_sync_single_for_cpu(lp->pci_dev,
2561 lp->
2562 rx_dma_addr
2563 [entry],
2564 PKT_BUF_SZ -
2565 2,
2566 PCI_DMA_FROMDEVICE);
2567 eth_copy_and_sum(skb,
2568 (unsigned char *)(lp->
2569 rx_skbuff
2570 [entry]->
2571 data),
2572 pkt_len, 0);
2573 pci_dma_sync_single_for_device(lp->
2574 pci_dev,
2575 lp->
2576 rx_dma_addr
2577 [entry],
2578 PKT_BUF_SZ
2579 - 2,
2580 PCI_DMA_FROMDEVICE);
2582 lp->stats.rx_bytes += skb->len;
2583 skb->protocol = eth_type_trans(skb, dev);
2584 netif_rx(skb);
2585 dev->last_rx = jiffies;
2586 lp->stats.rx_packets++;
2589 /*
2590 * The docs say that the buffer length isn't touched, but Andrew Boyd
2591 * of QNX reports that some revs of the 79C965 clear it.
2592 */
2593 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2594 wmb(); /* Make sure owner changes after all others are visible */
2595 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2596 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2597 if (--boguscnt <= 0)
2598 break; /* don't stay in loop forever */
2601 return 0;
2604 static int pcnet32_close(struct net_device *dev)
2606 unsigned long ioaddr = dev->base_addr;
2607 struct pcnet32_private *lp = dev->priv;
2608 unsigned long flags;
2610 del_timer_sync(&lp->watchdog_timer);
2612 netif_stop_queue(dev);
2614 spin_lock_irqsave(&lp->lock, flags);
2616 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2618 if (netif_msg_ifdown(lp))
2619 printk(KERN_DEBUG
2620 "%s: Shutting down ethercard, status was %2.2x.\n",
2621 dev->name, lp->a.read_csr(ioaddr, 0));
2623 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2624 lp->a.write_csr(ioaddr, 0, 0x0004);
2626 /*
2627 * Switch back to 16bit mode to avoid problems with dumb
2628 * DOS packet driver after a warm reboot
2629 */
2630 lp->a.write_bcr(ioaddr, 20, 4);
2632 spin_unlock_irqrestore(&lp->lock, flags);
2634 free_irq(dev->irq, dev);
2636 spin_lock_irqsave(&lp->lock, flags);
2638 pcnet32_purge_rx_ring(dev);
2639 pcnet32_purge_tx_ring(dev);
2641 spin_unlock_irqrestore(&lp->lock, flags);
2643 return 0;
2646 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2648 struct pcnet32_private *lp = dev->priv;
2649 unsigned long ioaddr = dev->base_addr;
2650 u16 saved_addr;
2651 unsigned long flags;
2653 spin_lock_irqsave(&lp->lock, flags);
2654 saved_addr = lp->a.read_rap(ioaddr);
2655 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2656 lp->a.write_rap(ioaddr, saved_addr);
2657 spin_unlock_irqrestore(&lp->lock, flags);
2659 return &lp->stats;
2662 /* taken from the sunlance driver, which it took from the depca driver */
2663 static void pcnet32_load_multicast(struct net_device *dev)
2665 struct pcnet32_private *lp = dev->priv;
2666 volatile struct pcnet32_init_block *ib = &lp->init_block;
2667 volatile u16 *mcast_table = (u16 *) & ib->filter;
2668 struct dev_mc_list *dmi = dev->mc_list;
2669 unsigned long ioaddr = dev->base_addr;
2670 char *addrs;
2671 int i;
2672 u32 crc;
2674 /* set all multicast bits */
2675 if (dev->flags & IFF_ALLMULTI) {
2676 ib->filter[0] = 0xffffffff;
2677 ib->filter[1] = 0xffffffff;
2678 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2679 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2680 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2681 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2682 return;
2684 /* clear the multicast filter */
2685 ib->filter[0] = 0;
2686 ib->filter[1] = 0;
2688 /* Add addresses */
2689 for (i = 0; i < dev->mc_count; i++) {
2690 addrs = dmi->dmi_addr;
2691 dmi = dmi->next;
2693 /* multicast address? */
2694 if (!(*addrs & 1))
2695 continue;
2697 crc = ether_crc_le(6, addrs);
2698 crc = crc >> 26;
2699 mcast_table[crc >> 4] =
2700 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2701 (1 << (crc & 0xf)));
2703 for (i = 0; i < 4; i++)
2704 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2705 le16_to_cpu(mcast_table[i]));
2706 return;
2709 /*
2710 * Set or clear the multicast filter for this adaptor.
2711 */
2712 static void pcnet32_set_multicast_list(struct net_device *dev)
2714 unsigned long ioaddr = dev->base_addr, flags;
2715 struct pcnet32_private *lp = dev->priv;
2716 int csr15, suspended;
2718 spin_lock_irqsave(&lp->lock, flags);
2719 suspended = pcnet32_suspend(dev, &flags, 0);
2720 csr15 = lp->a.read_csr(ioaddr, CSR15);
2721 if (dev->flags & IFF_PROMISC) {
2722 /* Log any net taps. */
2723 if (netif_msg_hw(lp))
2724 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2725 dev->name);
2726 lp->init_block.mode =
2727 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2728 7);
2729 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2730 } else {
2731 lp->init_block.mode =
2732 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2733 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2734 pcnet32_load_multicast(dev);
2737 if (suspended) {
2738 int csr5;
2739 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2740 csr5 = lp->a.read_csr(ioaddr, CSR5);
2741 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2742 } else {
2743 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2744 pcnet32_restart(dev, CSR0_NORMAL);
2745 netif_wake_queue(dev);
2748 spin_unlock_irqrestore(&lp->lock, flags);
2751 /* This routine assumes that the lp->lock is held */
2752 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2754 struct pcnet32_private *lp = dev->priv;
2755 unsigned long ioaddr = dev->base_addr;
2756 u16 val_out;
2758 if (!lp->mii)
2759 return 0;
2761 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2762 val_out = lp->a.read_bcr(ioaddr, 34);
2764 return val_out;
2767 /* This routine assumes that the lp->lock is held */
2768 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2770 struct pcnet32_private *lp = dev->priv;
2771 unsigned long ioaddr = dev->base_addr;
2773 if (!lp->mii)
2774 return;
2776 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2777 lp->a.write_bcr(ioaddr, 34, val);
2780 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2782 struct pcnet32_private *lp = dev->priv;
2783 int rc;
2784 unsigned long flags;
2786 /* SIOC[GS]MIIxxx ioctls */
2787 if (lp->mii) {
2788 spin_lock_irqsave(&lp->lock, flags);
2789 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2790 spin_unlock_irqrestore(&lp->lock, flags);
2791 } else {
2792 rc = -EOPNOTSUPP;
2795 return rc;
2798 static int pcnet32_check_otherphy(struct net_device *dev)
2800 struct pcnet32_private *lp = dev->priv;
2801 struct mii_if_info mii = lp->mii_if;
2802 u16 bmcr;
2803 int i;
2805 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2806 if (i == lp->mii_if.phy_id)
2807 continue; /* skip active phy */
2808 if (lp->phymask & (1 << i)) {
2809 mii.phy_id = i;
2810 if (mii_link_ok(&mii)) {
2811 /* found PHY with active link */
2812 if (netif_msg_link(lp))
2813 printk(KERN_INFO
2814 "%s: Using PHY number %d.\n",
2815 dev->name, i);
2817 /* isolate inactive phy */
2818 bmcr =
2819 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2820 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2821 bmcr | BMCR_ISOLATE);
2823 /* de-isolate new phy */
2824 bmcr = mdio_read(dev, i, MII_BMCR);
2825 mdio_write(dev, i, MII_BMCR,
2826 bmcr & ~BMCR_ISOLATE);
2828 /* set new phy address */
2829 lp->mii_if.phy_id = i;
2830 return 1;
2834 return 0;
2837 /*
2838 * Show the status of the media. Similar to mii_check_media however it
2839 * correctly shows the link speed for all (tested) pcnet32 variants.
2840 * Devices with no mii just report link state without speed.
2842 * Caller is assumed to hold and release the lp->lock.
2843 */
2845 static void pcnet32_check_media(struct net_device *dev, int verbose)
2847 struct pcnet32_private *lp = dev->priv;
2848 int curr_link;
2849 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2850 u32 bcr9;
2852 if (lp->mii) {
2853 curr_link = mii_link_ok(&lp->mii_if);
2854 } else {
2855 ulong ioaddr = dev->base_addr; /* card base I/O address */
2856 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2858 if (!curr_link) {
2859 if (prev_link || verbose) {
2860 netif_carrier_off(dev);
2861 if (netif_msg_link(lp))
2862 printk(KERN_INFO "%s: link down\n", dev->name);
2864 if (lp->phycount > 1) {
2865 curr_link = pcnet32_check_otherphy(dev);
2866 prev_link = 0;
2868 } else if (verbose || !prev_link) {
2869 netif_carrier_on(dev);
2870 if (lp->mii) {
2871 if (netif_msg_link(lp)) {
2872 struct ethtool_cmd ecmd;
2873 mii_ethtool_gset(&lp->mii_if, &ecmd);
2874 printk(KERN_INFO
2875 "%s: link up, %sMbps, %s-duplex\n",
2876 dev->name,
2877 (ecmd.speed == SPEED_100) ? "100" : "10",
2878 (ecmd.duplex ==
2879 DUPLEX_FULL) ? "full" : "half");
2881 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2882 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2883 if (lp->mii_if.full_duplex)
2884 bcr9 |= (1 << 0);
2885 else
2886 bcr9 &= ~(1 << 0);
2887 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2889 } else {
2890 if (netif_msg_link(lp))
2891 printk(KERN_INFO "%s: link up\n", dev->name);
2896 /*
2897 * Check for loss of link and link establishment.
2898 * Can not use mii_check_media because it does nothing if mode is forced.
2899 */
2901 static void pcnet32_watchdog(struct net_device *dev)
2903 struct pcnet32_private *lp = dev->priv;
2904 unsigned long flags;
2906 /* Print the link status if it has changed */
2907 spin_lock_irqsave(&lp->lock, flags);
2908 pcnet32_check_media(dev, 0);
2909 spin_unlock_irqrestore(&lp->lock, flags);
2911 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2914 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2916 struct net_device *dev = pci_get_drvdata(pdev);
2918 if (dev) {
2919 struct pcnet32_private *lp = dev->priv;
2921 unregister_netdev(dev);
2922 pcnet32_free_ring(dev);
2923 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2924 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2925 free_netdev(dev);
2926 pci_disable_device(pdev);
2927 pci_set_drvdata(pdev, NULL);
2931 static struct pci_driver pcnet32_driver = {
2932 .name = DRV_NAME,
2933 .probe = pcnet32_probe_pci,
2934 .remove = __devexit_p(pcnet32_remove_one),
2935 .id_table = pcnet32_pci_tbl,
2936 };
2938 /* An additional parameter that may be passed in... */
2939 static int debug = -1;
2940 static int tx_start_pt = -1;
2941 static int pcnet32_have_pci;
2943 module_param(debug, int, 0);
2944 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2945 module_param(max_interrupt_work, int, 0);
2946 MODULE_PARM_DESC(max_interrupt_work,
2947 DRV_NAME " maximum events handled per interrupt");
2948 module_param(rx_copybreak, int, 0);
2949 MODULE_PARM_DESC(rx_copybreak,
2950 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2951 module_param(tx_start_pt, int, 0);
2952 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2953 module_param(pcnet32vlb, int, 0);
2954 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2955 module_param_array(options, int, NULL, 0);
2956 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2957 module_param_array(full_duplex, int, NULL, 0);
2958 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2959 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2960 module_param_array(homepna, int, NULL, 0);
2961 MODULE_PARM_DESC(homepna,
2962 DRV_NAME
2963 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2965 MODULE_AUTHOR("Thomas Bogendoerfer");
2966 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2967 MODULE_LICENSE("GPL");
2969 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2971 static int __init pcnet32_init_module(void)
2973 printk(KERN_INFO "%s", version);
2975 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2977 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2978 tx_start = tx_start_pt;
2980 /* find the PCI devices */
2981 if (!pci_module_init(&pcnet32_driver))
2982 pcnet32_have_pci = 1;
2984 /* should we find any remaining VLbus devices ? */
2985 if (pcnet32vlb)
2986 pcnet32_probe_vlbus(pcnet32_portlist);
2988 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2989 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2991 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2994 static void __exit pcnet32_cleanup_module(void)
2996 struct net_device *next_dev;
2998 while (pcnet32_dev) {
2999 struct pcnet32_private *lp = pcnet32_dev->priv;
3000 next_dev = lp->next;
3001 unregister_netdev(pcnet32_dev);
3002 pcnet32_free_ring(pcnet32_dev);
3003 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3004 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3005 free_netdev(pcnet32_dev);
3006 pcnet32_dev = next_dev;
3009 if (pcnet32_have_pci)
3010 pci_unregister_driver(&pcnet32_driver);
3013 module_init(pcnet32_init_module);
3014 module_exit(pcnet32_cleanup_module);
3016 /*
3017 * Local variables:
3018 * c-indent-level: 4
3019 * tab-width: 8
3020 * End:
3021 */