ia64/linux-2.6.18-xen.hg

view drivers/net/ns83820.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/smp_lock.h>
108 #include <linux/workqueue.h>
109 #include <linux/init.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/timer.h>
116 #include <linux/if_vlan.h>
117 #include <linux/rtnetlink.h>
118 #include <linux/jiffies.h>
120 #include <asm/io.h>
121 #include <asm/uaccess.h>
122 #include <asm/system.h>
124 #define DRV_NAME "ns83820"
126 /* Global parameters. See module_param near the bottom. */
127 static int ihr = 2;
128 static int reset_phy = 0;
129 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
131 /* Dprintk is used for more interesting debug events */
132 #undef Dprintk
133 #define Dprintk dprintk
135 /* tunables */
136 #define RX_BUF_SIZE 1500 /* 8192 */
137 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
138 #define NS83820_VLAN_ACCEL_SUPPORT
139 #endif
141 /* Must not exceed ~65000. */
142 #define NR_RX_DESC 64
143 #define NR_TX_DESC 128
145 /* not tunable */
146 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148 #define MIN_TX_DESC_FREE 8
150 /* register defines */
151 #define CFGCS 0x04
153 #define CR_TXE 0x00000001
154 #define CR_TXD 0x00000002
155 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
156 * The Receive engine skips one descriptor and moves
157 * onto the next one!! */
158 #define CR_RXE 0x00000004
159 #define CR_RXD 0x00000008
160 #define CR_TXR 0x00000010
161 #define CR_RXR 0x00000020
162 #define CR_SWI 0x00000080
163 #define CR_RST 0x00000100
165 #define PTSCR_EEBIST_FAIL 0x00000001
166 #define PTSCR_EEBIST_EN 0x00000002
167 #define PTSCR_EELOAD_EN 0x00000004
168 #define PTSCR_RBIST_FAIL 0x000001b8
169 #define PTSCR_RBIST_DONE 0x00000200
170 #define PTSCR_RBIST_EN 0x00000400
171 #define PTSCR_RBIST_RST 0x00002000
173 #define MEAR_EEDI 0x00000001
174 #define MEAR_EEDO 0x00000002
175 #define MEAR_EECLK 0x00000004
176 #define MEAR_EESEL 0x00000008
177 #define MEAR_MDIO 0x00000010
178 #define MEAR_MDDIR 0x00000020
179 #define MEAR_MDC 0x00000040
181 #define ISR_TXDESC3 0x40000000
182 #define ISR_TXDESC2 0x20000000
183 #define ISR_TXDESC1 0x10000000
184 #define ISR_TXDESC0 0x08000000
185 #define ISR_RXDESC3 0x04000000
186 #define ISR_RXDESC2 0x02000000
187 #define ISR_RXDESC1 0x01000000
188 #define ISR_RXDESC0 0x00800000
189 #define ISR_TXRCMP 0x00400000
190 #define ISR_RXRCMP 0x00200000
191 #define ISR_DPERR 0x00100000
192 #define ISR_SSERR 0x00080000
193 #define ISR_RMABT 0x00040000
194 #define ISR_RTABT 0x00020000
195 #define ISR_RXSOVR 0x00010000
196 #define ISR_HIBINT 0x00008000
197 #define ISR_PHY 0x00004000
198 #define ISR_PME 0x00002000
199 #define ISR_SWI 0x00001000
200 #define ISR_MIB 0x00000800
201 #define ISR_TXURN 0x00000400
202 #define ISR_TXIDLE 0x00000200
203 #define ISR_TXERR 0x00000100
204 #define ISR_TXDESC 0x00000080
205 #define ISR_TXOK 0x00000040
206 #define ISR_RXORN 0x00000020
207 #define ISR_RXIDLE 0x00000010
208 #define ISR_RXEARLY 0x00000008
209 #define ISR_RXERR 0x00000004
210 #define ISR_RXDESC 0x00000002
211 #define ISR_RXOK 0x00000001
213 #define TXCFG_CSI 0x80000000
214 #define TXCFG_HBI 0x40000000
215 #define TXCFG_MLB 0x20000000
216 #define TXCFG_ATP 0x10000000
217 #define TXCFG_ECRETRY 0x00800000
218 #define TXCFG_BRST_DIS 0x00080000
219 #define TXCFG_MXDMA1024 0x00000000
220 #define TXCFG_MXDMA512 0x00700000
221 #define TXCFG_MXDMA256 0x00600000
222 #define TXCFG_MXDMA128 0x00500000
223 #define TXCFG_MXDMA64 0x00400000
224 #define TXCFG_MXDMA32 0x00300000
225 #define TXCFG_MXDMA16 0x00200000
226 #define TXCFG_MXDMA8 0x00100000
228 #define CFG_LNKSTS 0x80000000
229 #define CFG_SPDSTS 0x60000000
230 #define CFG_SPDSTS1 0x40000000
231 #define CFG_SPDSTS0 0x20000000
232 #define CFG_DUPSTS 0x10000000
233 #define CFG_TBI_EN 0x01000000
234 #define CFG_MODE_1000 0x00400000
235 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
236 * Read the Phy response and then configure the MAC accordingly */
237 #define CFG_AUTO_1000 0x00200000
238 #define CFG_PINT_CTL 0x001c0000
239 #define CFG_PINT_DUPSTS 0x00100000
240 #define CFG_PINT_LNKSTS 0x00080000
241 #define CFG_PINT_SPDSTS 0x00040000
242 #define CFG_TMRTEST 0x00020000
243 #define CFG_MRM_DIS 0x00010000
244 #define CFG_MWI_DIS 0x00008000
245 #define CFG_T64ADDR 0x00004000
246 #define CFG_PCI64_DET 0x00002000
247 #define CFG_DATA64_EN 0x00001000
248 #define CFG_M64ADDR 0x00000800
249 #define CFG_PHY_RST 0x00000400
250 #define CFG_PHY_DIS 0x00000200
251 #define CFG_EXTSTS_EN 0x00000100
252 #define CFG_REQALG 0x00000080
253 #define CFG_SB 0x00000040
254 #define CFG_POW 0x00000020
255 #define CFG_EXD 0x00000010
256 #define CFG_PESEL 0x00000008
257 #define CFG_BROM_DIS 0x00000004
258 #define CFG_EXT_125 0x00000002
259 #define CFG_BEM 0x00000001
261 #define EXTSTS_UDPPKT 0x00200000
262 #define EXTSTS_TCPPKT 0x00080000
263 #define EXTSTS_IPPKT 0x00020000
264 #define EXTSTS_VPKT 0x00010000
265 #define EXTSTS_VTG_MASK 0x0000ffff
267 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
269 #define MIBC_MIBS 0x00000008
270 #define MIBC_ACLR 0x00000004
271 #define MIBC_FRZ 0x00000002
272 #define MIBC_WRN 0x00000001
274 #define PCR_PSEN (1 << 31)
275 #define PCR_PS_MCAST (1 << 30)
276 #define PCR_PS_DA (1 << 29)
277 #define PCR_STHI_8 (3 << 23)
278 #define PCR_STLO_4 (1 << 23)
279 #define PCR_FFHI_8K (3 << 21)
280 #define PCR_FFLO_4K (1 << 21)
281 #define PCR_PAUSE_CNT 0xFFFE
283 #define RXCFG_AEP 0x80000000
284 #define RXCFG_ARP 0x40000000
285 #define RXCFG_STRIPCRC 0x20000000
286 #define RXCFG_RX_FD 0x10000000
287 #define RXCFG_ALP 0x08000000
288 #define RXCFG_AIRL 0x04000000
289 #define RXCFG_MXDMA512 0x00700000
290 #define RXCFG_DRTH 0x0000003e
291 #define RXCFG_DRTH0 0x00000002
293 #define RFCR_RFEN 0x80000000
294 #define RFCR_AAB 0x40000000
295 #define RFCR_AAM 0x20000000
296 #define RFCR_AAU 0x10000000
297 #define RFCR_APM 0x08000000
298 #define RFCR_APAT 0x07800000
299 #define RFCR_APAT3 0x04000000
300 #define RFCR_APAT2 0x02000000
301 #define RFCR_APAT1 0x01000000
302 #define RFCR_APAT0 0x00800000
303 #define RFCR_AARP 0x00400000
304 #define RFCR_MHEN 0x00200000
305 #define RFCR_UHEN 0x00100000
306 #define RFCR_ULM 0x00080000
308 #define VRCR_RUDPE 0x00000080
309 #define VRCR_RTCPE 0x00000040
310 #define VRCR_RIPE 0x00000020
311 #define VRCR_IPEN 0x00000010
312 #define VRCR_DUTF 0x00000008
313 #define VRCR_DVTF 0x00000004
314 #define VRCR_VTREN 0x00000002
315 #define VRCR_VTDEN 0x00000001
317 #define VTCR_PPCHK 0x00000008
318 #define VTCR_GCHK 0x00000004
319 #define VTCR_VPPTI 0x00000002
320 #define VTCR_VGTI 0x00000001
322 #define CR 0x00
323 #define CFG 0x04
324 #define MEAR 0x08
325 #define PTSCR 0x0c
326 #define ISR 0x10
327 #define IMR 0x14
328 #define IER 0x18
329 #define IHR 0x1c
330 #define TXDP 0x20
331 #define TXDP_HI 0x24
332 #define TXCFG 0x28
333 #define GPIOR 0x2c
334 #define RXDP 0x30
335 #define RXDP_HI 0x34
336 #define RXCFG 0x38
337 #define PQCR 0x3c
338 #define WCSR 0x40
339 #define PCR 0x44
340 #define RFCR 0x48
341 #define RFDR 0x4c
343 #define SRR 0x58
345 #define VRCR 0xbc
346 #define VTCR 0xc0
347 #define VDR 0xc4
348 #define CCSR 0xcc
350 #define TBICR 0xe0
351 #define TBISR 0xe4
352 #define TANAR 0xe8
353 #define TANLPAR 0xec
354 #define TANER 0xf0
355 #define TESR 0xf4
357 #define TBICR_MR_AN_ENABLE 0x00001000
358 #define TBICR_MR_RESTART_AN 0x00000200
360 #define TBISR_MR_LINK_STATUS 0x00000020
361 #define TBISR_MR_AN_COMPLETE 0x00000004
363 #define TANAR_PS2 0x00000100
364 #define TANAR_PS1 0x00000080
365 #define TANAR_HALF_DUP 0x00000040
366 #define TANAR_FULL_DUP 0x00000020
368 #define GPIOR_GP5_OE 0x00000200
369 #define GPIOR_GP4_OE 0x00000100
370 #define GPIOR_GP3_OE 0x00000080
371 #define GPIOR_GP2_OE 0x00000040
372 #define GPIOR_GP1_OE 0x00000020
373 #define GPIOR_GP3_OUT 0x00000004
374 #define GPIOR_GP1_OUT 0x00000001
376 #define LINK_AUTONEGOTIATE 0x01
377 #define LINK_DOWN 0x02
378 #define LINK_UP 0x04
380 #define HW_ADDR_LEN sizeof(dma_addr_t)
381 #define desc_addr_set(desc, addr) \
382 do { \
383 ((desc)[0] = cpu_to_le32(addr)); \
384 if (HW_ADDR_LEN == 8) \
385 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
386 } while(0)
387 #define desc_addr_get(desc) \
388 (le32_to_cpu((desc)[0]) | \
389 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
391 #define DESC_LINK 0
392 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
393 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
394 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
396 #define CMDSTS_OWN 0x80000000
397 #define CMDSTS_MORE 0x40000000
398 #define CMDSTS_INTR 0x20000000
399 #define CMDSTS_ERR 0x10000000
400 #define CMDSTS_OK 0x08000000
401 #define CMDSTS_RUNT 0x00200000
402 #define CMDSTS_LEN_MASK 0x0000ffff
404 #define CMDSTS_DEST_MASK 0x01800000
405 #define CMDSTS_DEST_SELF 0x00800000
406 #define CMDSTS_DEST_MULTI 0x01000000
408 #define DESC_SIZE 8 /* Should be cache line sized */
410 struct rx_info {
411 spinlock_t lock;
412 int up;
413 long idle;
415 struct sk_buff *skbs[NR_RX_DESC];
417 u32 *next_rx_desc;
418 u16 next_rx, next_empty;
420 u32 *descs;
421 dma_addr_t phy_descs;
422 };
425 struct ns83820 {
426 struct net_device_stats stats;
427 u8 __iomem *base;
429 struct pci_dev *pci_dev;
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
438 unsigned ihr;
439 struct work_struct tq_refill;
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
444 u32 CFG_cache;
446 u32 MEAR_cache;
447 u32 IMR_cache;
449 unsigned linkstate;
451 spinlock_t tx_lock;
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
461 char pad[16] __attribute__((aligned(16)));
462 u32 *tx_descs;
463 dma_addr_t tx_phy_descs;
465 struct timer_list tx_watchdog;
466 };
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
504 dev->vlgrp = grp;
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
510 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
511 {
512 struct ns83820 *dev = PRIV(ndev);
514 spin_lock_irq(&dev->misc_lock);
515 spin_lock(&dev->tx_lock);
516 if (dev->vlgrp)
517 dev->vlgrp->vlan_devices[vid] = NULL;
518 spin_unlock(&dev->tx_lock);
519 spin_unlock_irq(&dev->misc_lock);
520 }
521 #endif
523 /* Packet Receiver
524 *
525 * The hardware supports linked lists of receive descriptors for
526 * which ownership is transfered back and forth by means of an
527 * ownership bit. While the hardware does support the use of a
528 * ring for receive descriptors, we only make use of a chain in
529 * an attempt to reduce bus traffic under heavy load scenarios.
530 * This will also make bugs a bit more obvious. The current code
531 * only makes use of a single rx chain; I hope to implement
532 * priority based rx for version 1.0. Goal: even under overload
533 * conditions, still route realtime traffic with as low jitter as
534 * possible.
535 */
536 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
537 {
538 desc_addr_set(desc + DESC_LINK, link);
539 desc_addr_set(desc + DESC_BUFPTR, buf);
540 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
541 mb();
542 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
543 }
545 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
546 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
547 {
548 unsigned next_empty;
549 u32 cmdsts;
550 u32 *sg;
551 dma_addr_t buf;
553 next_empty = dev->rx_info.next_empty;
555 /* don't overrun last rx marker */
556 if (unlikely(nr_rx_empty(dev) <= 2)) {
557 kfree_skb(skb);
558 return 1;
559 }
561 #if 0
562 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
563 dev->rx_info.next_empty,
564 dev->rx_info.nr_used,
565 dev->rx_info.next_rx
566 );
567 #endif
569 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
570 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
571 dev->rx_info.skbs[next_empty] = skb;
573 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
574 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
575 buf = pci_map_single(dev->pci_dev, skb->data,
576 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
577 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
578 /* update link of previous rx */
579 if (likely(next_empty != dev->rx_info.next_rx))
580 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
582 return 0;
583 }
585 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
586 {
587 struct ns83820 *dev = PRIV(ndev);
588 unsigned i;
589 unsigned long flags = 0;
591 if (unlikely(nr_rx_empty(dev) <= 2))
592 return 0;
594 dprintk("rx_refill(%p)\n", ndev);
595 if (gfp == GFP_ATOMIC)
596 spin_lock_irqsave(&dev->rx_info.lock, flags);
597 for (i=0; i<NR_RX_DESC; i++) {
598 struct sk_buff *skb;
599 long res;
600 /* extra 16 bytes for alignment */
601 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
602 if (unlikely(!skb))
603 break;
605 res = (long)skb->data & 0xf;
606 res = 0x10 - res;
607 res &= 0xf;
608 skb_reserve(skb, res);
610 skb->dev = ndev;
611 if (gfp != GFP_ATOMIC)
612 spin_lock_irqsave(&dev->rx_info.lock, flags);
613 res = ns83820_add_rx_skb(dev, skb);
614 if (gfp != GFP_ATOMIC)
615 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
616 if (res) {
617 i = 1;
618 break;
619 }
620 }
621 if (gfp == GFP_ATOMIC)
622 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
624 return i ? 0 : -ENOMEM;
625 }
627 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
628 static void fastcall rx_refill_atomic(struct net_device *ndev)
629 {
630 rx_refill(ndev, GFP_ATOMIC);
631 }
633 /* REFILL */
634 static inline void queue_refill(void *_dev)
635 {
636 struct net_device *ndev = _dev;
637 struct ns83820 *dev = PRIV(ndev);
639 rx_refill(ndev, GFP_KERNEL);
640 if (dev->rx_info.up)
641 kick_rx(ndev);
642 }
644 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
645 {
646 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
647 }
649 static void FASTCALL(phy_intr(struct net_device *ndev));
650 static void fastcall phy_intr(struct net_device *ndev)
651 {
652 struct ns83820 *dev = PRIV(ndev);
653 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
654 u32 cfg, new_cfg;
655 u32 tbisr, tanar, tanlpar;
656 int speed, fullduplex, newlinkstate;
658 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
660 if (dev->CFG_cache & CFG_TBI_EN) {
661 /* we have an optical transceiver */
662 tbisr = readl(dev->base + TBISR);
663 tanar = readl(dev->base + TANAR);
664 tanlpar = readl(dev->base + TANLPAR);
665 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
666 tbisr, tanar, tanlpar);
668 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
669 && (tanar & TANAR_FULL_DUP)) ) {
671 /* both of us are full duplex */
672 writel(readl(dev->base + TXCFG)
673 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
674 dev->base + TXCFG);
675 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
676 dev->base + RXCFG);
677 /* Light up full duplex LED */
678 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
679 dev->base + GPIOR);
681 } else if(((tanlpar & TANAR_HALF_DUP)
682 && (tanar & TANAR_HALF_DUP))
683 || ((tanlpar & TANAR_FULL_DUP)
684 && (tanar & TANAR_HALF_DUP))
685 || ((tanlpar & TANAR_HALF_DUP)
686 && (tanar & TANAR_FULL_DUP))) {
688 /* one or both of us are half duplex */
689 writel((readl(dev->base + TXCFG)
690 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
691 dev->base + TXCFG);
692 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
693 dev->base + RXCFG);
694 /* Turn off full duplex LED */
695 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
696 dev->base + GPIOR);
697 }
699 speed = 4; /* 1000F */
701 } else {
702 /* we have a copper transceiver */
703 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
705 if (cfg & CFG_SPDSTS1)
706 new_cfg |= CFG_MODE_1000;
707 else
708 new_cfg &= ~CFG_MODE_1000;
710 speed = ((cfg / CFG_SPDSTS0) & 3);
711 fullduplex = (cfg & CFG_DUPSTS);
713 if (fullduplex) {
714 new_cfg |= CFG_SB;
715 writel(readl(dev->base + TXCFG)
716 | TXCFG_CSI | TXCFG_HBI,
717 dev->base + TXCFG);
718 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
719 dev->base + RXCFG);
720 } else {
721 writel(readl(dev->base + TXCFG)
722 & ~(TXCFG_CSI | TXCFG_HBI),
723 dev->base + TXCFG);
724 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
725 dev->base + RXCFG);
726 }
728 if ((cfg & CFG_LNKSTS) &&
729 ((new_cfg ^ dev->CFG_cache) != 0)) {
730 writel(new_cfg, dev->base + CFG);
731 dev->CFG_cache = new_cfg;
732 }
734 dev->CFG_cache &= ~CFG_SPDSTS;
735 dev->CFG_cache |= cfg & CFG_SPDSTS;
736 }
738 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
740 if (newlinkstate & LINK_UP
741 && dev->linkstate != newlinkstate) {
742 netif_start_queue(ndev);
743 netif_wake_queue(ndev);
744 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
745 ndev->name,
746 speeds[speed],
747 fullduplex ? "full" : "half");
748 } else if (newlinkstate & LINK_DOWN
749 && dev->linkstate != newlinkstate) {
750 netif_stop_queue(ndev);
751 printk(KERN_INFO "%s: link now down.\n", ndev->name);
752 }
754 dev->linkstate = newlinkstate;
755 }
757 static int ns83820_setup_rx(struct net_device *ndev)
758 {
759 struct ns83820 *dev = PRIV(ndev);
760 unsigned i;
761 int ret;
763 dprintk("ns83820_setup_rx(%p)\n", ndev);
765 dev->rx_info.idle = 1;
766 dev->rx_info.next_rx = 0;
767 dev->rx_info.next_rx_desc = dev->rx_info.descs;
768 dev->rx_info.next_empty = 0;
770 for (i=0; i<NR_RX_DESC; i++)
771 clear_rx_desc(dev, i);
773 writel(0, dev->base + RXDP_HI);
774 writel(dev->rx_info.phy_descs, dev->base + RXDP);
776 ret = rx_refill(ndev, GFP_KERNEL);
777 if (!ret) {
778 dprintk("starting receiver\n");
779 /* prevent the interrupt handler from stomping on us */
780 spin_lock_irq(&dev->rx_info.lock);
782 writel(0x0001, dev->base + CCSR);
783 writel(0, dev->base + RFCR);
784 writel(0x7fc00000, dev->base + RFCR);
785 writel(0xffc00000, dev->base + RFCR);
787 dev->rx_info.up = 1;
789 phy_intr(ndev);
791 /* Okay, let it rip */
792 spin_lock_irq(&dev->misc_lock);
793 dev->IMR_cache |= ISR_PHY;
794 dev->IMR_cache |= ISR_RXRCMP;
795 //dev->IMR_cache |= ISR_RXERR;
796 //dev->IMR_cache |= ISR_RXOK;
797 dev->IMR_cache |= ISR_RXORN;
798 dev->IMR_cache |= ISR_RXSOVR;
799 dev->IMR_cache |= ISR_RXDESC;
800 dev->IMR_cache |= ISR_RXIDLE;
801 dev->IMR_cache |= ISR_TXDESC;
802 dev->IMR_cache |= ISR_TXIDLE;
804 writel(dev->IMR_cache, dev->base + IMR);
805 writel(1, dev->base + IER);
806 spin_unlock(&dev->misc_lock);
808 kick_rx(ndev);
810 spin_unlock_irq(&dev->rx_info.lock);
811 }
812 return ret;
813 }
815 static void ns83820_cleanup_rx(struct ns83820 *dev)
816 {
817 unsigned i;
818 unsigned long flags;
820 dprintk("ns83820_cleanup_rx(%p)\n", dev);
822 /* disable receive interrupts */
823 spin_lock_irqsave(&dev->misc_lock, flags);
824 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
825 writel(dev->IMR_cache, dev->base + IMR);
826 spin_unlock_irqrestore(&dev->misc_lock, flags);
828 /* synchronize with the interrupt handler and kill it */
829 dev->rx_info.up = 0;
830 synchronize_irq(dev->pci_dev->irq);
832 /* touch the pci bus... */
833 readl(dev->base + IMR);
835 /* assumes the transmitter is already disabled and reset */
836 writel(0, dev->base + RXDP_HI);
837 writel(0, dev->base + RXDP);
839 for (i=0; i<NR_RX_DESC; i++) {
840 struct sk_buff *skb = dev->rx_info.skbs[i];
841 dev->rx_info.skbs[i] = NULL;
842 clear_rx_desc(dev, i);
843 if (skb)
844 kfree_skb(skb);
845 }
846 }
848 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
849 static void fastcall ns83820_rx_kick(struct net_device *ndev)
850 {
851 struct ns83820 *dev = PRIV(ndev);
852 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
853 if (dev->rx_info.up) {
854 rx_refill_atomic(ndev);
855 kick_rx(ndev);
856 }
857 }
859 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
860 schedule_work(&dev->tq_refill);
861 else
862 kick_rx(ndev);
863 if (dev->rx_info.idle)
864 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
865 }
867 /* rx_irq
868 *
869 */
870 static void FASTCALL(rx_irq(struct net_device *ndev));
871 static void fastcall rx_irq(struct net_device *ndev)
872 {
873 struct ns83820 *dev = PRIV(ndev);
874 struct rx_info *info = &dev->rx_info;
875 unsigned next_rx;
876 int rx_rc, len;
877 u32 cmdsts, *desc;
878 unsigned long flags;
879 int nr = 0;
881 dprintk("rx_irq(%p)\n", ndev);
882 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
883 readl(dev->base + RXDP),
884 (long)(dev->rx_info.phy_descs),
885 (int)dev->rx_info.next_rx,
886 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
887 (int)dev->rx_info.next_empty,
888 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
889 );
891 spin_lock_irqsave(&info->lock, flags);
892 if (!info->up)
893 goto out;
895 dprintk("walking descs\n");
896 next_rx = info->next_rx;
897 desc = info->next_rx_desc;
898 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
899 (cmdsts != CMDSTS_OWN)) {
900 struct sk_buff *skb;
901 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
902 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
904 dprintk("cmdsts: %08x\n", cmdsts);
905 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
906 dprintk("extsts: %08x\n", extsts);
908 skb = info->skbs[next_rx];
909 info->skbs[next_rx] = NULL;
910 info->next_rx = (next_rx + 1) % NR_RX_DESC;
912 mb();
913 clear_rx_desc(dev, next_rx);
915 pci_unmap_single(dev->pci_dev, bufptr,
916 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
917 len = cmdsts & CMDSTS_LEN_MASK;
918 #ifdef NS83820_VLAN_ACCEL_SUPPORT
919 /* NH: As was mentioned below, this chip is kinda
920 * brain dead about vlan tag stripping. Frames
921 * that are 64 bytes with a vlan header appended
922 * like arp frames, or pings, are flagged as Runts
923 * when the tag is stripped and hardware. This
924 * also means that the OK bit in the descriptor
925 * is cleared when the frame comes in so we have
926 * to do a specific length check here to make sure
927 * the frame would have been ok, had we not stripped
928 * the tag.
929 */
930 if (likely((CMDSTS_OK & cmdsts) ||
931 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
932 #else
933 if (likely(CMDSTS_OK & cmdsts)) {
934 #endif
935 skb_put(skb, len);
936 if (unlikely(!skb))
937 goto netdev_mangle_me_harder_failed;
938 if (cmdsts & CMDSTS_DEST_MULTI)
939 dev->stats.multicast ++;
940 dev->stats.rx_packets ++;
941 dev->stats.rx_bytes += len;
942 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 } else {
945 skb->ip_summed = CHECKSUM_NONE;
946 }
947 skb->protocol = eth_type_trans(skb, ndev);
948 #ifdef NS83820_VLAN_ACCEL_SUPPORT
949 if(extsts & EXTSTS_VPKT) {
950 unsigned short tag;
951 tag = ntohs(extsts & EXTSTS_VTG_MASK);
952 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
953 } else {
954 rx_rc = netif_rx(skb);
955 }
956 #else
957 rx_rc = netif_rx(skb);
958 #endif
959 if (NET_RX_DROP == rx_rc) {
960 netdev_mangle_me_harder_failed:
961 dev->stats.rx_dropped ++;
962 }
963 } else {
964 kfree_skb(skb);
965 }
967 nr++;
968 next_rx = info->next_rx;
969 desc = info->descs + (DESC_SIZE * next_rx);
970 }
971 info->next_rx = next_rx;
972 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
974 out:
975 if (0 && !nr) {
976 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
977 }
979 spin_unlock_irqrestore(&info->lock, flags);
980 }
982 static void rx_action(unsigned long _dev)
983 {
984 struct net_device *ndev = (void *)_dev;
985 struct ns83820 *dev = PRIV(ndev);
986 rx_irq(ndev);
987 writel(ihr, dev->base + IHR);
989 spin_lock_irq(&dev->misc_lock);
990 dev->IMR_cache |= ISR_RXDESC;
991 writel(dev->IMR_cache, dev->base + IMR);
992 spin_unlock_irq(&dev->misc_lock);
994 rx_irq(ndev);
995 ns83820_rx_kick(ndev);
996 }
998 /* Packet Transmit code
999 */
1000 static inline void kick_tx(struct ns83820 *dev)
1002 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1003 dev, dev->tx_idx, dev->tx_free_idx);
1004 writel(CR_TXE, dev->base + CR);
1007 /* No spinlock needed on the transmit irq path as the interrupt handler is
1008 * serialized.
1009 */
1010 static void do_tx_done(struct net_device *ndev)
1012 struct ns83820 *dev = PRIV(ndev);
1013 u32 cmdsts, tx_done_idx, *desc;
1015 dprintk("do_tx_done(%p)\n", ndev);
1016 tx_done_idx = dev->tx_done_idx;
1017 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1019 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1020 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1021 while ((tx_done_idx != dev->tx_free_idx) &&
1022 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1023 struct sk_buff *skb;
1024 unsigned len;
1025 dma_addr_t addr;
1027 if (cmdsts & CMDSTS_ERR)
1028 dev->stats.tx_errors ++;
1029 if (cmdsts & CMDSTS_OK)
1030 dev->stats.tx_packets ++;
1031 if (cmdsts & CMDSTS_OK)
1032 dev->stats.tx_bytes += cmdsts & 0xffff;
1034 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1035 tx_done_idx, dev->tx_free_idx, cmdsts);
1036 skb = dev->tx_skbs[tx_done_idx];
1037 dev->tx_skbs[tx_done_idx] = NULL;
1038 dprintk("done(%p)\n", skb);
1040 len = cmdsts & CMDSTS_LEN_MASK;
1041 addr = desc_addr_get(desc + DESC_BUFPTR);
1042 if (skb) {
1043 pci_unmap_single(dev->pci_dev,
1044 addr,
1045 len,
1046 PCI_DMA_TODEVICE);
1047 dev_kfree_skb_irq(skb);
1048 atomic_dec(&dev->nr_tx_skbs);
1049 } else
1050 pci_unmap_page(dev->pci_dev,
1051 addr,
1052 len,
1053 PCI_DMA_TODEVICE);
1055 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1056 dev->tx_done_idx = tx_done_idx;
1057 desc[DESC_CMDSTS] = cpu_to_le32(0);
1058 mb();
1059 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1062 /* Allow network stack to resume queueing packets after we've
1063 * finished transmitting at least 1/4 of the packets in the queue.
1064 */
1065 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1066 dprintk("start_queue(%p)\n", ndev);
1067 netif_start_queue(ndev);
1068 netif_wake_queue(ndev);
1072 static void ns83820_cleanup_tx(struct ns83820 *dev)
1074 unsigned i;
1076 for (i=0; i<NR_TX_DESC; i++) {
1077 struct sk_buff *skb = dev->tx_skbs[i];
1078 dev->tx_skbs[i] = NULL;
1079 if (skb) {
1080 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1081 pci_unmap_single(dev->pci_dev,
1082 desc_addr_get(desc + DESC_BUFPTR),
1083 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1084 PCI_DMA_TODEVICE);
1085 dev_kfree_skb_irq(skb);
1086 atomic_dec(&dev->nr_tx_skbs);
1090 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1093 /* transmit routine. This code relies on the network layer serializing
1094 * its calls in, but will run happily in parallel with the interrupt
1095 * handler. This code currently has provisions for fragmenting tx buffers
1096 * while trying to track down a bug in either the zero copy code or
1097 * the tx fifo (hence the MAX_FRAG_LEN).
1098 */
1099 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1101 struct ns83820 *dev = PRIV(ndev);
1102 u32 free_idx, cmdsts, extsts;
1103 int nr_free, nr_frags;
1104 unsigned tx_done_idx, last_idx;
1105 dma_addr_t buf;
1106 unsigned len;
1107 skb_frag_t *frag;
1108 int stopped = 0;
1109 int do_intr = 0;
1110 volatile u32 *first_desc;
1112 dprintk("ns83820_hard_start_xmit\n");
1114 nr_frags = skb_shinfo(skb)->nr_frags;
1115 again:
1116 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1117 netif_stop_queue(ndev);
1118 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1119 return 1;
1120 netif_start_queue(ndev);
1123 last_idx = free_idx = dev->tx_free_idx;
1124 tx_done_idx = dev->tx_done_idx;
1125 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1126 nr_free -= 1;
1127 if (nr_free <= nr_frags) {
1128 dprintk("stop_queue - not enough(%p)\n", ndev);
1129 netif_stop_queue(ndev);
1131 /* Check again: we may have raced with a tx done irq */
1132 if (dev->tx_done_idx != tx_done_idx) {
1133 dprintk("restart queue(%p)\n", ndev);
1134 netif_start_queue(ndev);
1135 goto again;
1137 return 1;
1140 if (free_idx == dev->tx_intr_idx) {
1141 do_intr = 1;
1142 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1145 nr_free -= nr_frags;
1146 if (nr_free < MIN_TX_DESC_FREE) {
1147 dprintk("stop_queue - last entry(%p)\n", ndev);
1148 netif_stop_queue(ndev);
1149 stopped = 1;
1152 frag = skb_shinfo(skb)->frags;
1153 if (!nr_frags)
1154 frag = NULL;
1155 extsts = 0;
1156 if (skb->ip_summed == CHECKSUM_HW) {
1157 extsts |= EXTSTS_IPPKT;
1158 if (IPPROTO_TCP == skb->nh.iph->protocol)
1159 extsts |= EXTSTS_TCPPKT;
1160 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1161 extsts |= EXTSTS_UDPPKT;
1164 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1165 if(vlan_tx_tag_present(skb)) {
1166 /* fetch the vlan tag info out of the
1167 * ancilliary data if the vlan code
1168 * is using hw vlan acceleration
1169 */
1170 short tag = vlan_tx_tag_get(skb);
1171 extsts |= (EXTSTS_VPKT | htons(tag));
1173 #endif
1175 len = skb->len;
1176 if (nr_frags)
1177 len -= skb->data_len;
1178 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1180 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1182 for (;;) {
1183 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1185 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1186 (unsigned long long)buf);
1187 last_idx = free_idx;
1188 free_idx = (free_idx + 1) % NR_TX_DESC;
1189 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1190 desc_addr_set(desc + DESC_BUFPTR, buf);
1191 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1193 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1194 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1195 cmdsts |= len;
1196 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1198 if (!nr_frags)
1199 break;
1201 buf = pci_map_page(dev->pci_dev, frag->page,
1202 frag->page_offset,
1203 frag->size, PCI_DMA_TODEVICE);
1204 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1205 (long long)buf, (long) page_to_pfn(frag->page),
1206 frag->page_offset);
1207 len = frag->size;
1208 frag++;
1209 nr_frags--;
1211 dprintk("done pkt\n");
1213 spin_lock_irq(&dev->tx_lock);
1214 dev->tx_skbs[last_idx] = skb;
1215 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1216 dev->tx_free_idx = free_idx;
1217 atomic_inc(&dev->nr_tx_skbs);
1218 spin_unlock_irq(&dev->tx_lock);
1220 kick_tx(dev);
1222 /* Check again: we may have raced with a tx done irq */
1223 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1224 netif_start_queue(ndev);
1226 /* set the transmit start time to catch transmit timeouts */
1227 ndev->trans_start = jiffies;
1228 return 0;
1231 static void ns83820_update_stats(struct ns83820 *dev)
1233 u8 __iomem *base = dev->base;
1235 /* the DP83820 will freeze counters, so we need to read all of them */
1236 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1237 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1238 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1239 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1240 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1241 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1242 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1243 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1244 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1245 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1246 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1249 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1251 struct ns83820 *dev = PRIV(ndev);
1253 /* somewhat overkill */
1254 spin_lock_irq(&dev->misc_lock);
1255 ns83820_update_stats(dev);
1256 spin_unlock_irq(&dev->misc_lock);
1258 return &dev->stats;
1261 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1263 struct ns83820 *dev = PRIV(ndev);
1264 strcpy(info->driver, "ns83820");
1265 strcpy(info->version, VERSION);
1266 strcpy(info->bus_info, pci_name(dev->pci_dev));
1269 static u32 ns83820_get_link(struct net_device *ndev)
1271 struct ns83820 *dev = PRIV(ndev);
1272 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1273 return cfg & CFG_LNKSTS ? 1 : 0;
1276 static struct ethtool_ops ops = {
1277 .get_drvinfo = ns83820_get_drvinfo,
1278 .get_link = ns83820_get_link
1279 };
1281 /* this function is called in irq context from the ISR */
1282 static void ns83820_mib_isr(struct ns83820 *dev)
1284 unsigned long flags;
1285 spin_lock_irqsave(&dev->misc_lock, flags);
1286 ns83820_update_stats(dev);
1287 spin_unlock_irqrestore(&dev->misc_lock, flags);
1290 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1291 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1293 struct net_device *ndev = data;
1294 struct ns83820 *dev = PRIV(ndev);
1295 u32 isr;
1296 dprintk("ns83820_irq(%p)\n", ndev);
1298 dev->ihr = 0;
1300 isr = readl(dev->base + ISR);
1301 dprintk("irq: %08x\n", isr);
1302 ns83820_do_isr(ndev, isr);
1303 return IRQ_HANDLED;
1306 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1308 struct ns83820 *dev = PRIV(ndev);
1309 unsigned long flags;
1311 #ifdef DEBUG
1312 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1313 Dprintk("odd isr? 0x%08x\n", isr);
1314 #endif
1316 if (ISR_RXIDLE & isr) {
1317 dev->rx_info.idle = 1;
1318 Dprintk("oh dear, we are idle\n");
1319 ns83820_rx_kick(ndev);
1322 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1323 prefetch(dev->rx_info.next_rx_desc);
1325 spin_lock_irqsave(&dev->misc_lock, flags);
1326 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1327 writel(dev->IMR_cache, dev->base + IMR);
1328 spin_unlock_irqrestore(&dev->misc_lock, flags);
1330 tasklet_schedule(&dev->rx_tasklet);
1331 //rx_irq(ndev);
1332 //writel(4, dev->base + IHR);
1335 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1336 ns83820_rx_kick(ndev);
1338 if (unlikely(ISR_RXSOVR & isr)) {
1339 //printk("overrun: rxsovr\n");
1340 dev->stats.rx_fifo_errors ++;
1343 if (unlikely(ISR_RXORN & isr)) {
1344 //printk("overrun: rxorn\n");
1345 dev->stats.rx_fifo_errors ++;
1348 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1349 writel(CR_RXE, dev->base + CR);
1351 if (ISR_TXIDLE & isr) {
1352 u32 txdp;
1353 txdp = readl(dev->base + TXDP);
1354 dprintk("txdp: %08x\n", txdp);
1355 txdp -= dev->tx_phy_descs;
1356 dev->tx_idx = txdp / (DESC_SIZE * 4);
1357 if (dev->tx_idx >= NR_TX_DESC) {
1358 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1359 dev->tx_idx = 0;
1361 /* The may have been a race between a pci originated read
1362 * and the descriptor update from the cpu. Just in case,
1363 * kick the transmitter if the hardware thinks it is on a
1364 * different descriptor than we are.
1365 */
1366 if (dev->tx_idx != dev->tx_free_idx)
1367 kick_tx(dev);
1370 /* Defer tx ring processing until more than a minimum amount of
1371 * work has accumulated
1372 */
1373 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1374 spin_lock_irqsave(&dev->tx_lock, flags);
1375 do_tx_done(ndev);
1376 spin_unlock_irqrestore(&dev->tx_lock, flags);
1378 /* Disable TxOk if there are no outstanding tx packets.
1379 */
1380 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1381 (dev->IMR_cache & ISR_TXOK)) {
1382 spin_lock_irqsave(&dev->misc_lock, flags);
1383 dev->IMR_cache &= ~ISR_TXOK;
1384 writel(dev->IMR_cache, dev->base + IMR);
1385 spin_unlock_irqrestore(&dev->misc_lock, flags);
1389 /* The TxIdle interrupt can come in before the transmit has
1390 * completed. Normally we reap packets off of the combination
1391 * of TxDesc and TxIdle and leave TxOk disabled (since it
1392 * occurs on every packet), but when no further irqs of this
1393 * nature are expected, we must enable TxOk.
1394 */
1395 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1396 spin_lock_irqsave(&dev->misc_lock, flags);
1397 dev->IMR_cache |= ISR_TXOK;
1398 writel(dev->IMR_cache, dev->base + IMR);
1399 spin_unlock_irqrestore(&dev->misc_lock, flags);
1402 /* MIB interrupt: one of the statistics counters is about to overflow */
1403 if (unlikely(ISR_MIB & isr))
1404 ns83820_mib_isr(dev);
1406 /* PHY: Link up/down/negotiation state change */
1407 if (unlikely(ISR_PHY & isr))
1408 phy_intr(ndev);
1410 #if 0 /* Still working on the interrupt mitigation strategy */
1411 if (dev->ihr)
1412 writel(dev->ihr, dev->base + IHR);
1413 #endif
1416 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1418 Dprintk("resetting chip...\n");
1419 writel(which, dev->base + CR);
1420 do {
1421 schedule();
1422 } while (readl(dev->base + CR) & which);
1423 Dprintk("okay!\n");
1426 static int ns83820_stop(struct net_device *ndev)
1428 struct ns83820 *dev = PRIV(ndev);
1430 /* FIXME: protect against interrupt handler? */
1431 del_timer_sync(&dev->tx_watchdog);
1433 /* disable interrupts */
1434 writel(0, dev->base + IMR);
1435 writel(0, dev->base + IER);
1436 readl(dev->base + IER);
1438 dev->rx_info.up = 0;
1439 synchronize_irq(dev->pci_dev->irq);
1441 ns83820_do_reset(dev, CR_RST);
1443 synchronize_irq(dev->pci_dev->irq);
1445 spin_lock_irq(&dev->misc_lock);
1446 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1447 spin_unlock_irq(&dev->misc_lock);
1449 ns83820_cleanup_rx(dev);
1450 ns83820_cleanup_tx(dev);
1452 return 0;
1455 static void ns83820_tx_timeout(struct net_device *ndev)
1457 struct ns83820 *dev = PRIV(ndev);
1458 u32 tx_done_idx, *desc;
1459 unsigned long flags;
1461 spin_lock_irqsave(&dev->tx_lock, flags);
1463 tx_done_idx = dev->tx_done_idx;
1464 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1466 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1467 ndev->name,
1468 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1470 #if defined(DEBUG)
1472 u32 isr;
1473 isr = readl(dev->base + ISR);
1474 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1475 ns83820_do_isr(ndev, isr);
1477 #endif
1479 do_tx_done(ndev);
1481 tx_done_idx = dev->tx_done_idx;
1482 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1484 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1485 ndev->name,
1486 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1488 spin_unlock_irqrestore(&dev->tx_lock, flags);
1491 static void ns83820_tx_watch(unsigned long data)
1493 struct net_device *ndev = (void *)data;
1494 struct ns83820 *dev = PRIV(ndev);
1496 #if defined(DEBUG)
1497 printk("ns83820_tx_watch: %u %u %d\n",
1498 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1499 );
1500 #endif
1502 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1503 dev->tx_done_idx != dev->tx_free_idx) {
1504 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1505 ndev->name,
1506 dev->tx_done_idx, dev->tx_free_idx,
1507 atomic_read(&dev->nr_tx_skbs));
1508 ns83820_tx_timeout(ndev);
1511 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1514 static int ns83820_open(struct net_device *ndev)
1516 struct ns83820 *dev = PRIV(ndev);
1517 unsigned i;
1518 u32 desc;
1519 int ret;
1521 dprintk("ns83820_open\n");
1523 writel(0, dev->base + PQCR);
1525 ret = ns83820_setup_rx(ndev);
1526 if (ret)
1527 goto failed;
1529 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1530 for (i=0; i<NR_TX_DESC; i++) {
1531 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1532 = cpu_to_le32(
1533 dev->tx_phy_descs
1534 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1537 dev->tx_idx = 0;
1538 dev->tx_done_idx = 0;
1539 desc = dev->tx_phy_descs;
1540 writel(0, dev->base + TXDP_HI);
1541 writel(desc, dev->base + TXDP);
1543 init_timer(&dev->tx_watchdog);
1544 dev->tx_watchdog.data = (unsigned long)ndev;
1545 dev->tx_watchdog.function = ns83820_tx_watch;
1546 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1548 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1550 return 0;
1552 failed:
1553 ns83820_stop(ndev);
1554 return ret;
1557 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1559 unsigned i;
1560 for (i=0; i<3; i++) {
1561 u32 data;
1563 /* Read from the perfect match memory: this is loaded by
1564 * the chip from the EEPROM via the EELOAD self test.
1565 */
1566 writel(i*2, dev->base + RFCR);
1567 data = readl(dev->base + RFDR);
1569 *mac++ = data;
1570 *mac++ = data >> 8;
1574 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1576 if (new_mtu > RX_BUF_SIZE)
1577 return -EINVAL;
1578 ndev->mtu = new_mtu;
1579 return 0;
1582 static void ns83820_set_multicast(struct net_device *ndev)
1584 struct ns83820 *dev = PRIV(ndev);
1585 u8 __iomem *rfcr = dev->base + RFCR;
1586 u32 and_mask = 0xffffffff;
1587 u32 or_mask = 0;
1588 u32 val;
1590 if (ndev->flags & IFF_PROMISC)
1591 or_mask |= RFCR_AAU | RFCR_AAM;
1592 else
1593 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1595 if (ndev->flags & IFF_ALLMULTI)
1596 or_mask |= RFCR_AAM;
1597 else
1598 and_mask &= ~RFCR_AAM;
1600 spin_lock_irq(&dev->misc_lock);
1601 val = (readl(rfcr) & and_mask) | or_mask;
1602 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1603 writel(val & ~RFCR_RFEN, rfcr);
1604 writel(val, rfcr);
1605 spin_unlock_irq(&dev->misc_lock);
1608 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1610 struct ns83820 *dev = PRIV(ndev);
1611 int timed_out = 0;
1612 unsigned long start;
1613 u32 status;
1614 int loops = 0;
1616 dprintk("%s: start %s\n", ndev->name, name);
1618 start = jiffies;
1620 writel(enable, dev->base + PTSCR);
1621 for (;;) {
1622 loops++;
1623 status = readl(dev->base + PTSCR);
1624 if (!(status & enable))
1625 break;
1626 if (status & done)
1627 break;
1628 if (status & fail)
1629 break;
1630 if (time_after_eq(jiffies, start + HZ)) {
1631 timed_out = 1;
1632 break;
1634 schedule_timeout_uninterruptible(1);
1637 if (status & fail)
1638 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1639 ndev->name, name, status, fail);
1640 else if (timed_out)
1641 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1642 ndev->name, name, status);
1644 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1647 #ifdef PHY_CODE_IS_FINISHED
1648 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1650 /* drive MDC low */
1651 dev->MEAR_cache &= ~MEAR_MDC;
1652 writel(dev->MEAR_cache, dev->base + MEAR);
1653 readl(dev->base + MEAR);
1655 /* enable output, set bit */
1656 dev->MEAR_cache |= MEAR_MDDIR;
1657 if (bit)
1658 dev->MEAR_cache |= MEAR_MDIO;
1659 else
1660 dev->MEAR_cache &= ~MEAR_MDIO;
1662 /* set the output bit */
1663 writel(dev->MEAR_cache, dev->base + MEAR);
1664 readl(dev->base + MEAR);
1666 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1667 udelay(1);
1669 /* drive MDC high causing the data bit to be latched */
1670 dev->MEAR_cache |= MEAR_MDC;
1671 writel(dev->MEAR_cache, dev->base + MEAR);
1672 readl(dev->base + MEAR);
1674 /* Wait again... */
1675 udelay(1);
1678 static int ns83820_mii_read_bit(struct ns83820 *dev)
1680 int bit;
1682 /* drive MDC low, disable output */
1683 dev->MEAR_cache &= ~MEAR_MDC;
1684 dev->MEAR_cache &= ~MEAR_MDDIR;
1685 writel(dev->MEAR_cache, dev->base + MEAR);
1686 readl(dev->base + MEAR);
1688 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1689 udelay(1);
1691 /* drive MDC high causing the data bit to be latched */
1692 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1693 dev->MEAR_cache |= MEAR_MDC;
1694 writel(dev->MEAR_cache, dev->base + MEAR);
1696 /* Wait again... */
1697 udelay(1);
1699 return bit;
1702 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1704 unsigned data = 0;
1705 int i;
1707 /* read some garbage so that we eventually sync up */
1708 for (i=0; i<64; i++)
1709 ns83820_mii_read_bit(dev);
1711 ns83820_mii_write_bit(dev, 0); /* start */
1712 ns83820_mii_write_bit(dev, 1);
1713 ns83820_mii_write_bit(dev, 1); /* opcode read */
1714 ns83820_mii_write_bit(dev, 0);
1716 /* write out the phy address: 5 bits, msb first */
1717 for (i=0; i<5; i++)
1718 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1720 /* write out the register address, 5 bits, msb first */
1721 for (i=0; i<5; i++)
1722 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1724 ns83820_mii_read_bit(dev); /* turn around cycles */
1725 ns83820_mii_read_bit(dev);
1727 /* read in the register data, 16 bits msb first */
1728 for (i=0; i<16; i++) {
1729 data <<= 1;
1730 data |= ns83820_mii_read_bit(dev);
1733 return data;
1736 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1738 int i;
1740 /* read some garbage so that we eventually sync up */
1741 for (i=0; i<64; i++)
1742 ns83820_mii_read_bit(dev);
1744 ns83820_mii_write_bit(dev, 0); /* start */
1745 ns83820_mii_write_bit(dev, 1);
1746 ns83820_mii_write_bit(dev, 0); /* opcode read */
1747 ns83820_mii_write_bit(dev, 1);
1749 /* write out the phy address: 5 bits, msb first */
1750 for (i=0; i<5; i++)
1751 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1753 /* write out the register address, 5 bits, msb first */
1754 for (i=0; i<5; i++)
1755 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1757 ns83820_mii_read_bit(dev); /* turn around cycles */
1758 ns83820_mii_read_bit(dev);
1760 /* read in the register data, 16 bits msb first */
1761 for (i=0; i<16; i++)
1762 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1764 return data;
1767 static void ns83820_probe_phy(struct net_device *ndev)
1769 struct ns83820 *dev = PRIV(ndev);
1770 static int first;
1771 int i;
1772 #define MII_PHYIDR1 0x02
1773 #define MII_PHYIDR2 0x03
1775 #if 0
1776 if (!first) {
1777 unsigned tmp;
1778 ns83820_mii_read_reg(dev, 1, 0x09);
1779 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1781 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1782 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1783 udelay(1300);
1784 ns83820_mii_read_reg(dev, 1, 0x09);
1786 #endif
1787 first = 1;
1789 for (i=1; i<2; i++) {
1790 int j;
1791 unsigned a, b;
1792 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1793 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1795 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1796 // ndev->name, i, a, b);
1798 for (j=0; j<0x16; j+=4) {
1799 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1800 ndev->name, j,
1801 ns83820_mii_read_reg(dev, i, 0 + j),
1802 ns83820_mii_read_reg(dev, i, 1 + j),
1803 ns83820_mii_read_reg(dev, i, 2 + j),
1804 ns83820_mii_read_reg(dev, i, 3 + j)
1805 );
1809 unsigned a, b;
1810 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1811 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1812 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1813 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1815 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1816 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1817 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1818 dprintk("version: 0x%04x 0x%04x\n", a, b);
1821 #endif
1823 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1825 struct net_device *ndev;
1826 struct ns83820 *dev;
1827 long addr;
1828 int err;
1829 int using_dac = 0;
1831 /* See if we can set the dma mask early on; failure is fatal. */
1832 if (sizeof(dma_addr_t) == 8 &&
1833 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1834 using_dac = 1;
1835 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1836 using_dac = 0;
1837 } else {
1838 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1839 return -ENODEV;
1842 ndev = alloc_etherdev(sizeof(struct ns83820));
1843 dev = PRIV(ndev);
1844 err = -ENOMEM;
1845 if (!dev)
1846 goto out;
1848 spin_lock_init(&dev->rx_info.lock);
1849 spin_lock_init(&dev->tx_lock);
1850 spin_lock_init(&dev->misc_lock);
1851 dev->pci_dev = pci_dev;
1853 SET_MODULE_OWNER(ndev);
1854 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1856 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1857 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1859 err = pci_enable_device(pci_dev);
1860 if (err) {
1861 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1862 goto out_free;
1865 pci_set_master(pci_dev);
1866 addr = pci_resource_start(pci_dev, 1);
1867 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1868 dev->tx_descs = pci_alloc_consistent(pci_dev,
1869 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1870 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1871 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1872 err = -ENOMEM;
1873 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1874 goto out_disable;
1876 dprintk("%p: %08lx %p: %08lx\n",
1877 dev->tx_descs, (long)dev->tx_phy_descs,
1878 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1880 /* disable interrupts */
1881 writel(0, dev->base + IMR);
1882 writel(0, dev->base + IER);
1883 readl(dev->base + IER);
1885 dev->IMR_cache = 0;
1887 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1888 DRV_NAME, ndev);
1889 if (err) {
1890 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1891 pci_dev->irq, err);
1892 goto out_disable;
1895 /*
1896 * FIXME: we are holding rtnl_lock() over obscenely long area only
1897 * because some of the setup code uses dev->name. It's Wrong(tm) -
1898 * we should be using driver-specific names for all that stuff.
1899 * For now that will do, but we really need to come back and kill
1900 * most of the dev_alloc_name() users later.
1901 */
1902 rtnl_lock();
1903 err = dev_alloc_name(ndev, ndev->name);
1904 if (err < 0) {
1905 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1906 goto out_free_irq;
1909 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1910 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1911 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1913 ndev->open = ns83820_open;
1914 ndev->stop = ns83820_stop;
1915 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1916 ndev->get_stats = ns83820_get_stats;
1917 ndev->change_mtu = ns83820_change_mtu;
1918 ndev->set_multicast_list = ns83820_set_multicast;
1919 SET_ETHTOOL_OPS(ndev, &ops);
1920 ndev->tx_timeout = ns83820_tx_timeout;
1921 ndev->watchdog_timeo = 5 * HZ;
1922 pci_set_drvdata(pci_dev, ndev);
1924 ns83820_do_reset(dev, CR_RST);
1926 /* Must reset the ram bist before running it */
1927 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1928 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1929 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1930 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1931 PTSCR_EEBIST_FAIL);
1932 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1934 /* I love config registers */
1935 dev->CFG_cache = readl(dev->base + CFG);
1937 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1938 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1939 ndev->name);
1940 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1941 if (!(dev->CFG_cache & CFG_DATA64_EN))
1942 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1943 ndev->name);
1944 } else
1945 dev->CFG_cache &= ~(CFG_DATA64_EN);
1947 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1948 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1949 CFG_M64ADDR);
1950 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1951 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1952 dev->CFG_cache |= CFG_REQALG;
1953 dev->CFG_cache |= CFG_POW;
1954 dev->CFG_cache |= CFG_TMRTEST;
1956 /* When compiled with 64 bit addressing, we must always enable
1957 * the 64 bit descriptor format.
1958 */
1959 if (sizeof(dma_addr_t) == 8)
1960 dev->CFG_cache |= CFG_M64ADDR;
1961 if (using_dac)
1962 dev->CFG_cache |= CFG_T64ADDR;
1964 /* Big endian mode does not seem to do what the docs suggest */
1965 dev->CFG_cache &= ~CFG_BEM;
1967 /* setup optical transceiver if we have one */
1968 if (dev->CFG_cache & CFG_TBI_EN) {
1969 printk(KERN_INFO "%s: enabling optical transceiver\n",
1970 ndev->name);
1971 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1973 /* setup auto negotiation feature advertisement */
1974 writel(readl(dev->base + TANAR)
1975 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1976 dev->base + TANAR);
1978 /* start auto negotiation */
1979 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1980 dev->base + TBICR);
1981 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1982 dev->linkstate = LINK_AUTONEGOTIATE;
1984 dev->CFG_cache |= CFG_MODE_1000;
1987 writel(dev->CFG_cache, dev->base + CFG);
1988 dprintk("CFG: %08x\n", dev->CFG_cache);
1990 if (reset_phy) {
1991 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1992 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1993 msleep(10);
1994 writel(dev->CFG_cache, dev->base + CFG);
1997 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1998 * the PCI layer. FIXME.
1999 */
2000 if (readl(dev->base + SRR))
2001 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2002 #endif
2004 /* Note! The DMA burst size interacts with packet
2005 * transmission, such that the largest packet that
2006 * can be transmitted is 8192 - FLTH - burst size.
2007 * If only the transmit fifo was larger...
2008 */
2009 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2010 * some DELL and COMPAQ SMP systems */
2011 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2012 | ((1600 / 32) * 0x100),
2013 dev->base + TXCFG);
2015 /* Flush the interrupt holdoff timer */
2016 writel(0x000, dev->base + IHR);
2017 writel(0x100, dev->base + IHR);
2018 writel(0x000, dev->base + IHR);
2020 /* Set Rx to full duplex, don't accept runt, errored, long or length
2021 * range errored packets. Use 512 byte DMA.
2022 */
2023 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2024 * some DELL and COMPAQ SMP systems
2025 * Turn on ALP, only we are accpeting Jumbo Packets */
2026 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2027 | RXCFG_STRIPCRC
2028 //| RXCFG_ALP
2029 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2031 /* Disable priority queueing */
2032 writel(0, dev->base + PQCR);
2034 /* Enable IP checksum validation and detetion of VLAN headers.
2035 * Note: do not set the reject options as at least the 0x102
2036 * revision of the chip does not properly accept IP fragments
2037 * at least for UDP.
2038 */
2039 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2040 * the MAC it calculates the packetsize AFTER stripping the VLAN
2041 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2042 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2043 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2044 * it discrards it!. These guys......
2045 * also turn on tag stripping if hardware acceleration is enabled
2046 */
2047 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2048 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2049 #else
2050 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2051 #endif
2052 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2054 /* Enable per-packet TCP/UDP/IP checksumming
2055 * and per packet vlan tag insertion if
2056 * vlan hardware acceleration is enabled
2057 */
2058 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2059 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2060 #else
2061 #define VTCR_INIT_VALUE VTCR_PPCHK
2062 #endif
2063 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2065 /* Ramit : Enable async and sync pause frames */
2066 /* writel(0, dev->base + PCR); */
2067 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2068 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2069 dev->base + PCR);
2071 /* Disable Wake On Lan */
2072 writel(0, dev->base + WCSR);
2074 ns83820_getmac(dev, ndev->dev_addr);
2076 /* Yes, we support dumb IP checksum on transmit */
2077 ndev->features |= NETIF_F_SG;
2078 ndev->features |= NETIF_F_IP_CSUM;
2080 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2081 /* We also support hardware vlan acceleration */
2082 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2083 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2084 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2085 #endif
2087 if (using_dac) {
2088 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2089 ndev->name);
2090 ndev->features |= NETIF_F_HIGHDMA;
2093 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2094 ndev->name,
2095 (unsigned)readl(dev->base + SRR) >> 8,
2096 (unsigned)readl(dev->base + SRR) & 0xff,
2097 ndev->dev_addr[0], ndev->dev_addr[1],
2098 ndev->dev_addr[2], ndev->dev_addr[3],
2099 ndev->dev_addr[4], ndev->dev_addr[5],
2100 addr, pci_dev->irq,
2101 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2102 );
2104 #ifdef PHY_CODE_IS_FINISHED
2105 ns83820_probe_phy(ndev);
2106 #endif
2108 err = register_netdevice(ndev);
2109 if (err) {
2110 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2111 goto out_cleanup;
2113 rtnl_unlock();
2115 return 0;
2117 out_cleanup:
2118 writel(0, dev->base + IMR); /* paranoia */
2119 writel(0, dev->base + IER);
2120 readl(dev->base + IER);
2121 out_free_irq:
2122 rtnl_unlock();
2123 free_irq(pci_dev->irq, ndev);
2124 out_disable:
2125 if (dev->base)
2126 iounmap(dev->base);
2127 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2128 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2129 pci_disable_device(pci_dev);
2130 out_free:
2131 free_netdev(ndev);
2132 pci_set_drvdata(pci_dev, NULL);
2133 out:
2134 return err;
2137 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2139 struct net_device *ndev = pci_get_drvdata(pci_dev);
2140 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2142 if (!ndev) /* paranoia */
2143 return;
2145 writel(0, dev->base + IMR); /* paranoia */
2146 writel(0, dev->base + IER);
2147 readl(dev->base + IER);
2149 unregister_netdev(ndev);
2150 free_irq(dev->pci_dev->irq, ndev);
2151 iounmap(dev->base);
2152 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2153 dev->tx_descs, dev->tx_phy_descs);
2154 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2155 dev->rx_info.descs, dev->rx_info.phy_descs);
2156 pci_disable_device(dev->pci_dev);
2157 free_netdev(ndev);
2158 pci_set_drvdata(pci_dev, NULL);
2161 static struct pci_device_id ns83820_pci_tbl[] = {
2162 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2163 { 0, },
2164 };
2166 static struct pci_driver driver = {
2167 .name = "ns83820",
2168 .id_table = ns83820_pci_tbl,
2169 .probe = ns83820_init_one,
2170 .remove = __devexit_p(ns83820_remove_one),
2171 #if 0 /* FIXME: implement */
2172 .suspend = ,
2173 .resume = ,
2174 #endif
2175 };
2178 static int __init ns83820_init(void)
2180 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2181 return pci_module_init(&driver);
2184 static void __exit ns83820_exit(void)
2186 pci_unregister_driver(&driver);
2189 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2190 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2191 MODULE_LICENSE("GPL");
2193 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2195 module_param(lnksts, int, 0);
2196 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2198 module_param(ihr, int, 0);
2199 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2201 module_param(reset_phy, int, 0);
2202 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2204 module_init(ns83820_init);
2205 module_exit(ns83820_exit);