ia64/linux-2.6.18-xen.hg

view drivers/net/mipsnet.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6 #ifndef __MIPSNET_H
7 #define __MIPSNET_H
9 /*
10 * Id of this Net device, as seen by the core.
11 */
12 #define MIPS_NET_DEV_ID ((uint64_t) \
13 ((uint64_t)'M'<< 0)| \
14 ((uint64_t)'I'<< 8)| \
15 ((uint64_t)'P'<<16)| \
16 ((uint64_t)'S'<<24)| \
17 ((uint64_t)'N'<<32)| \
18 ((uint64_t)'E'<<40)| \
19 ((uint64_t)'T'<<48)| \
20 ((uint64_t)'0'<<56))
22 /*
23 * Net status/control block as seen by sw in the core.
24 * (Why not use bit fields? can't be bothered with cross-platform struct
25 * packing.)
26 */
27 typedef struct _net_control_block {
28 /// dev info for probing
29 /// reads as MIPSNET%d where %d is some form of version
30 uint64_t devId; /*0x00 */
32 /*
33 * read only busy flag.
34 * Set and cleared by the Net Device to indicate that an rx or a tx
35 * is in progress.
36 */
37 uint32_t busy; /*0x08 */
39 /*
40 * Set by the Net Device.
41 * The device will set it once data has been received.
42 * The value is the number of bytes that should be read from
43 * rxDataBuffer. The value will decrease till 0 until all the data
44 * from rxDataBuffer has been read.
45 */
46 uint32_t rxDataCount; /*0x0c */
47 #define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
49 /*
50 * Settable from the MIPS core, cleared by the Net Device.
51 * The core should set the number of bytes it wants to send,
52 * then it should write those bytes of data to txDataBuffer.
53 * The device will clear txDataCount has been processed (not necessarily sent).
54 */
55 uint32_t txDataCount; /*0x10 */
57 /*
58 * Interrupt control
59 *
60 * Used to clear the interrupted generated by this dev.
61 * Write a 1 to clear the interrupt. (except bit31).
62 *
63 * Bit0 is set if it was a tx-done interrupt.
64 * Bit1 is set when new rx-data is available.
65 * Until this bit is cleared there will be no other RXs.
66 *
67 * Bit31 is used for testing, it clears after a read.
68 * Writing 1 to this bit will cause an interrupt to be generated.
69 * To clear the test interrupt, write 0 to this register.
70 */
71 uint32_t interruptControl; /*0x14 */
72 #define MIPSNET_INTCTL_TXDONE ((uint32_t)(1<< 0))
73 #define MIPSNET_INTCTL_RXDONE ((uint32_t)(1<< 1))
74 #define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1<<31))
75 #define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE|MIPSNET_INTCTL_RXDONE|MIPSNET_INTCTL_TESTBIT)
77 /*
78 * Readonly core-specific interrupt info for the device to signal the core.
79 * The meaning of the contents of this field might change.
80 */
81 /*###\todo: the whole memIntf interrupt scheme is messy: the device should have
82 * no control what so ever of what VPE/register set is being used.
83 * The MemIntf should only expose interrupt lines, and something in the
84 * config should be responsible for the line<->core/vpe bindings.
85 */
86 uint32_t interruptInfo; /*0x18 */
88 /*
89 * This is where the received data is read out.
90 * There is more data to read until rxDataReady is 0.
91 * Only 1 byte at this regs offset is used.
92 */
93 uint32_t rxDataBuffer; /*0x1c */
95 /*
96 * This is where the data to transmit is written.
97 * Data should be written for the amount specified in the txDataCount register.
98 * Only 1 byte at this regs offset is used.
99 */
100 uint32_t txDataBuffer; /*0x20 */
101 } MIPS_T_NetControl;
103 #define MIPSNET_IO_EXTENT 0x40 /* being generous */
105 #define field_offset(field) ((int)&((MIPS_T_NetControl*)(0))->field)
107 #endif /* __MIPSNET_H */