ia64/linux-2.6.18-xen.hg

view drivers/net/ioc3-eth.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
7 *
8 * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
10 *
11 * References:
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
15 *
16 * To do:
17 *
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
21 * prefetching?
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
28 */
30 #define IOC3_NAME "ioc3-eth"
31 #define IOC3_VERSION "2.6.3-3"
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
36 #include <linux/mm.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/crc32.h>
41 #include <linux/mii.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/dma-mapping.h>
48 #ifdef CONFIG_SERIAL_8250
49 #include <linux/serial_core.h>
50 #include <linux/serial_8250.h>
51 #endif
53 #include <linux/netdevice.h>
54 #include <linux/etherdevice.h>
55 #include <linux/ethtool.h>
56 #include <linux/skbuff.h>
57 #include <net/ip.h>
59 #include <asm/byteorder.h>
60 #include <asm/checksum.h>
61 #include <asm/io.h>
62 #include <asm/pgtable.h>
63 #include <asm/uaccess.h>
64 #include <asm/sn/types.h>
65 #include <asm/sn/sn0/addrs.h>
66 #include <asm/sn/sn0/hubni.h>
67 #include <asm/sn/sn0/hubio.h>
68 #include <asm/sn/klconfig.h>
69 #include <asm/sn/ioc3.h>
70 #include <asm/sn/sn0/ip27.h>
71 #include <asm/pci/bridge.h>
73 /*
74 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
75 * value must be a power of two.
76 */
77 #define RX_BUFFS 64
79 #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
80 #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
82 /* Private per NIC data of the driver. */
83 struct ioc3_private {
84 struct ioc3 *regs;
85 unsigned long *rxr; /* pointer to receiver ring */
86 struct ioc3_etxd *txr;
87 struct sk_buff *rx_skbs[512];
88 struct sk_buff *tx_skbs[128];
89 struct net_device_stats stats;
90 int rx_ci; /* RX consumer index */
91 int rx_pi; /* RX producer index */
92 int tx_ci; /* TX consumer index */
93 int tx_pi; /* TX producer index */
94 int txqlen;
95 u32 emcr, ehar_h, ehar_l;
96 spinlock_t ioc3_lock;
97 struct mii_if_info mii;
98 struct pci_dev *pdev;
100 /* Members used by autonegotiation */
101 struct timer_list ioc3_timer;
102 };
104 static inline struct net_device *priv_netdev(struct ioc3_private *dev)
105 {
106 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
107 }
109 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
110 static void ioc3_set_multicast_list(struct net_device *dev);
111 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
112 static void ioc3_timeout(struct net_device *dev);
113 static inline unsigned int ioc3_hash(const unsigned char *addr);
114 static inline void ioc3_stop(struct ioc3_private *ip);
115 static void ioc3_init(struct net_device *dev);
117 static const char ioc3_str[] = "IOC3 Ethernet";
118 static struct ethtool_ops ioc3_ethtool_ops;
120 /* We use this to acquire receive skb's that we can DMA directly into. */
122 #define IOC3_CACHELINE 128UL
124 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
125 {
126 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
127 }
129 static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
130 unsigned int gfp_mask)
131 {
132 struct sk_buff *skb;
134 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
135 if (likely(skb)) {
136 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
137 if (offset)
138 skb_reserve(skb, offset);
139 }
141 return skb;
142 }
144 static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
145 {
146 #ifdef CONFIG_SGI_IP27
147 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
149 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
150 ((unsigned long)ptr & TO_PHYS_MASK);
151 #else
152 return virt_to_bus(ptr);
153 #endif
154 }
156 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
157 1644 while it's actually 1664. This one was nasty to track down ... */
158 #define RX_OFFSET 10
159 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
161 /* DMA barrier to separate cached and uncached accesses. */
162 #define BARRIER() \
163 __asm__("sync" ::: "memory")
166 #define IOC3_SIZE 0x100000
168 /*
169 * IOC3 is a big endian device
170 *
171 * Unorthodox but makes the users of these macros more readable - the pointer
172 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
173 * in the environment.
174 */
175 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
176 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
177 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
178 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
179 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
180 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
181 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
182 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
183 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
184 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
185 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
186 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
187 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
188 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
189 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
190 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
191 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
192 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
193 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
194 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
195 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
196 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
197 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
198 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
199 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
200 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
201 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
202 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
203 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
204 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
205 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
206 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
207 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
208 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
209 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
210 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
211 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
212 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
213 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
214 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
215 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
216 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
217 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
218 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
219 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
220 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
221 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
222 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
223 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
224 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
225 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
226 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
227 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
229 static inline u32 mcr_pack(u32 pulse, u32 sample)
230 {
231 return (pulse << 10) | (sample << 2);
232 }
234 static int nic_wait(struct ioc3 *ioc3)
235 {
236 u32 mcr;
238 do {
239 mcr = ioc3_r_mcr();
240 } while (!(mcr & 2));
242 return mcr & 1;
243 }
245 static int nic_reset(struct ioc3 *ioc3)
246 {
247 int presence;
249 ioc3_w_mcr(mcr_pack(500, 65));
250 presence = nic_wait(ioc3);
252 ioc3_w_mcr(mcr_pack(0, 500));
253 nic_wait(ioc3);
255 return presence;
256 }
258 static inline int nic_read_bit(struct ioc3 *ioc3)
259 {
260 int result;
262 ioc3_w_mcr(mcr_pack(6, 13));
263 result = nic_wait(ioc3);
264 ioc3_w_mcr(mcr_pack(0, 100));
265 nic_wait(ioc3);
267 return result;
268 }
270 static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
271 {
272 if (bit)
273 ioc3_w_mcr(mcr_pack(6, 110));
274 else
275 ioc3_w_mcr(mcr_pack(80, 30));
277 nic_wait(ioc3);
278 }
280 /*
281 * Read a byte from an iButton device
282 */
283 static u32 nic_read_byte(struct ioc3 *ioc3)
284 {
285 u32 result = 0;
286 int i;
288 for (i = 0; i < 8; i++)
289 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
291 return result;
292 }
294 /*
295 * Write a byte to an iButton device
296 */
297 static void nic_write_byte(struct ioc3 *ioc3, int byte)
298 {
299 int i, bit;
301 for (i = 8; i; i--) {
302 bit = byte & 1;
303 byte >>= 1;
305 nic_write_bit(ioc3, bit);
306 }
307 }
309 static u64 nic_find(struct ioc3 *ioc3, int *last)
310 {
311 int a, b, index, disc;
312 u64 address = 0;
314 nic_reset(ioc3);
315 /* Search ROM. */
316 nic_write_byte(ioc3, 0xf0);
318 /* Algorithm from ``Book of iButton Standards''. */
319 for (index = 0, disc = 0; index < 64; index++) {
320 a = nic_read_bit(ioc3);
321 b = nic_read_bit(ioc3);
323 if (a && b) {
324 printk("NIC search failed (not fatal).\n");
325 *last = 0;
326 return 0;
327 }
329 if (!a && !b) {
330 if (index == *last) {
331 address |= 1UL << index;
332 } else if (index > *last) {
333 address &= ~(1UL << index);
334 disc = index;
335 } else if ((address & (1UL << index)) == 0)
336 disc = index;
337 nic_write_bit(ioc3, address & (1UL << index));
338 continue;
339 } else {
340 if (a)
341 address |= 1UL << index;
342 else
343 address &= ~(1UL << index);
344 nic_write_bit(ioc3, a);
345 continue;
346 }
347 }
349 *last = disc;
351 return address;
352 }
354 static int nic_init(struct ioc3 *ioc3)
355 {
356 const char *type;
357 u8 crc;
358 u8 serial[6];
359 int save = 0, i;
361 type = "unknown";
363 while (1) {
364 u64 reg;
365 reg = nic_find(ioc3, &save);
367 switch (reg & 0xff) {
368 case 0x91:
369 type = "DS1981U";
370 break;
371 default:
372 if (save == 0) {
373 /* Let the caller try again. */
374 return -1;
375 }
376 continue;
377 }
379 nic_reset(ioc3);
381 /* Match ROM. */
382 nic_write_byte(ioc3, 0x55);
383 for (i = 0; i < 8; i++)
384 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
386 reg >>= 8; /* Shift out type. */
387 for (i = 0; i < 6; i++) {
388 serial[i] = reg & 0xff;
389 reg >>= 8;
390 }
391 crc = reg & 0xff;
392 break;
393 }
395 printk("Found %s NIC", type);
396 if (type != "unknown") {
397 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
398 " CRC %02x", serial[0], serial[1], serial[2],
399 serial[3], serial[4], serial[5], crc);
400 }
401 printk(".\n");
403 return 0;
404 }
406 /*
407 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
408 * SN0 / SN00 nodeboards and PCI cards.
409 */
410 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
411 {
412 struct ioc3 *ioc3 = ip->regs;
413 u8 nic[14];
414 int tries = 2; /* There may be some problem with the battery? */
415 int i;
417 ioc3_w_gpcr_s(1 << 21);
419 while (tries--) {
420 if (!nic_init(ioc3))
421 break;
422 udelay(500);
423 }
425 if (tries < 0) {
426 printk("Failed to read MAC address\n");
427 return;
428 }
430 /* Read Memory. */
431 nic_write_byte(ioc3, 0xf0);
432 nic_write_byte(ioc3, 0x00);
433 nic_write_byte(ioc3, 0x00);
435 for (i = 13; i >= 0; i--)
436 nic[i] = nic_read_byte(ioc3);
438 for (i = 2; i < 8; i++)
439 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
440 }
442 /*
443 * Ok, this is hosed by design. It's necessary to know what machine the
444 * NIC is in in order to know how to read the NIC address. We also have
445 * to know if it's a PCI card or a NIC in on the node board ...
446 */
447 static void ioc3_get_eaddr(struct ioc3_private *ip)
448 {
449 int i;
452 ioc3_get_eaddr_nic(ip);
454 printk("Ethernet address is ");
455 for (i = 0; i < 6; i++) {
456 printk("%02x", priv_netdev(ip)->dev_addr[i]);
457 if (i < 5)
458 printk(":");
459 }
460 printk(".\n");
461 }
463 static void __ioc3_set_mac_address(struct net_device *dev)
464 {
465 struct ioc3_private *ip = netdev_priv(dev);
466 struct ioc3 *ioc3 = ip->regs;
468 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
469 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
470 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
471 }
473 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
474 {
475 struct ioc3_private *ip = netdev_priv(dev);
476 struct sockaddr *sa = addr;
478 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
480 spin_lock_irq(&ip->ioc3_lock);
481 __ioc3_set_mac_address(dev);
482 spin_unlock_irq(&ip->ioc3_lock);
484 return 0;
485 }
487 /*
488 * Caller must hold the ioc3_lock ever for MII readers. This is also
489 * used to protect the transmitter side but it's low contention.
490 */
491 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
492 {
493 struct ioc3_private *ip = netdev_priv(dev);
494 struct ioc3 *ioc3 = ip->regs;
496 while (ioc3_r_micr() & MICR_BUSY);
497 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
498 while (ioc3_r_micr() & MICR_BUSY);
500 return ioc3_r_midr_r() & MIDR_DATA_MASK;
501 }
503 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
504 {
505 struct ioc3_private *ip = netdev_priv(dev);
506 struct ioc3 *ioc3 = ip->regs;
508 while (ioc3_r_micr() & MICR_BUSY);
509 ioc3_w_midr_w(data);
510 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
511 while (ioc3_r_micr() & MICR_BUSY);
512 }
514 static int ioc3_mii_init(struct ioc3_private *ip);
516 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
517 {
518 struct ioc3_private *ip = netdev_priv(dev);
519 struct ioc3 *ioc3 = ip->regs;
521 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
522 return &ip->stats;
523 }
525 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
527 static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
528 {
529 struct ethhdr *eh = eth_hdr(skb);
530 uint32_t csum, ehsum;
531 unsigned int proto;
532 struct iphdr *ih;
533 uint16_t *ew;
534 unsigned char *cp;
536 /*
537 * Did hardware handle the checksum at all? The cases we can handle
538 * are:
539 *
540 * - TCP and UDP checksums of IPv4 only.
541 * - IPv6 would be doable but we keep that for later ...
542 * - Only unfragmented packets. Did somebody already tell you
543 * fragmentation is evil?
544 * - don't care about packet size. Worst case when processing a
545 * malformed packet we'll try to access the packet at ip header +
546 * 64 bytes which is still inside the skb. Even in the unlikely
547 * case where the checksum is right the higher layers will still
548 * drop the packet as appropriate.
549 */
550 if (eh->h_proto != ntohs(ETH_P_IP))
551 return;
553 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
554 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
555 return;
557 proto = ih->protocol;
558 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
559 return;
561 /* Same as tx - compute csum of pseudo header */
562 csum = hwsum +
563 (ih->tot_len - (ih->ihl << 2)) +
564 htons((uint16_t)ih->protocol) +
565 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
566 (ih->daddr >> 16) + (ih->daddr & 0xffff);
568 /* Sum up ethernet dest addr, src addr and protocol */
569 ew = (uint16_t *) eh;
570 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
572 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
573 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
575 csum += 0xffff ^ ehsum;
577 /* In the next step we also subtract the 1's complement
578 checksum of the trailing ethernet CRC. */
579 cp = (char *)eh + len; /* points at trailing CRC */
580 if (len & 1) {
581 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
582 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
583 } else {
584 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
585 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
586 }
588 csum = (csum & 0xffff) + (csum >> 16);
589 csum = (csum & 0xffff) + (csum >> 16);
591 if (csum == 0xffff)
592 skb->ip_summed = CHECKSUM_UNNECESSARY;
593 }
594 #endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
596 static inline void ioc3_rx(struct ioc3_private *ip)
597 {
598 struct sk_buff *skb, *new_skb;
599 struct ioc3 *ioc3 = ip->regs;
600 int rx_entry, n_entry, len;
601 struct ioc3_erxbuf *rxb;
602 unsigned long *rxr;
603 u32 w0, err;
605 rxr = (unsigned long *) ip->rxr; /* Ring base */
606 rx_entry = ip->rx_ci; /* RX consume index */
607 n_entry = ip->rx_pi;
609 skb = ip->rx_skbs[rx_entry];
610 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
611 w0 = be32_to_cpu(rxb->w0);
613 while (w0 & ERXBUF_V) {
614 err = be32_to_cpu(rxb->err); /* It's valid ... */
615 if (err & ERXBUF_GOODPKT) {
616 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
617 skb_trim(skb, len);
618 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
620 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
621 if (!new_skb) {
622 /* Ouch, drop packet and just recycle packet
623 to keep the ring filled. */
624 ip->stats.rx_dropped++;
625 new_skb = skb;
626 goto next;
627 }
629 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
630 ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
631 #endif
633 netif_rx(skb);
635 ip->rx_skbs[rx_entry] = NULL; /* Poison */
637 new_skb->dev = priv_netdev(ip);
639 /* Because we reserve afterwards. */
640 skb_put(new_skb, (1664 + RX_OFFSET));
641 rxb = (struct ioc3_erxbuf *) new_skb->data;
642 skb_reserve(new_skb, RX_OFFSET);
644 priv_netdev(ip)->last_rx = jiffies;
645 ip->stats.rx_packets++; /* Statistics */
646 ip->stats.rx_bytes += len;
647 } else {
648 /* The frame is invalid and the skb never
649 reached the network layer so we can just
650 recycle it. */
651 new_skb = skb;
652 ip->stats.rx_errors++;
653 }
654 if (err & ERXBUF_CRCERR) /* Statistics */
655 ip->stats.rx_crc_errors++;
656 if (err & ERXBUF_FRAMERR)
657 ip->stats.rx_frame_errors++;
658 next:
659 ip->rx_skbs[n_entry] = new_skb;
660 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
661 rxb->w0 = 0; /* Clear valid flag */
662 n_entry = (n_entry + 1) & 511; /* Update erpir */
664 /* Now go on to the next ring entry. */
665 rx_entry = (rx_entry + 1) & 511;
666 skb = ip->rx_skbs[rx_entry];
667 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
668 w0 = be32_to_cpu(rxb->w0);
669 }
670 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
671 ip->rx_pi = n_entry;
672 ip->rx_ci = rx_entry;
673 }
675 static inline void ioc3_tx(struct ioc3_private *ip)
676 {
677 unsigned long packets, bytes;
678 struct ioc3 *ioc3 = ip->regs;
679 int tx_entry, o_entry;
680 struct sk_buff *skb;
681 u32 etcir;
683 spin_lock(&ip->ioc3_lock);
684 etcir = ioc3_r_etcir();
686 tx_entry = (etcir >> 7) & 127;
687 o_entry = ip->tx_ci;
688 packets = 0;
689 bytes = 0;
691 while (o_entry != tx_entry) {
692 packets++;
693 skb = ip->tx_skbs[o_entry];
694 bytes += skb->len;
695 dev_kfree_skb_irq(skb);
696 ip->tx_skbs[o_entry] = NULL;
698 o_entry = (o_entry + 1) & 127; /* Next */
700 etcir = ioc3_r_etcir(); /* More pkts sent? */
701 tx_entry = (etcir >> 7) & 127;
702 }
704 ip->stats.tx_packets += packets;
705 ip->stats.tx_bytes += bytes;
706 ip->txqlen -= packets;
708 if (ip->txqlen < 128)
709 netif_wake_queue(priv_netdev(ip));
711 ip->tx_ci = o_entry;
712 spin_unlock(&ip->ioc3_lock);
713 }
715 /*
716 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
717 * software problems, so we should try to recover
718 * more gracefully if this ever happens. In theory we might be flooded
719 * with such error interrupts if something really goes wrong, so we might
720 * also consider to take the interface down.
721 */
722 static void ioc3_error(struct ioc3_private *ip, u32 eisr)
723 {
724 struct net_device *dev = priv_netdev(ip);
725 unsigned char *iface = dev->name;
727 spin_lock(&ip->ioc3_lock);
729 if (eisr & EISR_RXOFLO)
730 printk(KERN_ERR "%s: RX overflow.\n", iface);
731 if (eisr & EISR_RXBUFOFLO)
732 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
733 if (eisr & EISR_RXMEMERR)
734 printk(KERN_ERR "%s: RX PCI error.\n", iface);
735 if (eisr & EISR_RXPARERR)
736 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
737 if (eisr & EISR_TXBUFUFLO)
738 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
739 if (eisr & EISR_TXMEMERR)
740 printk(KERN_ERR "%s: TX PCI error.\n", iface);
742 ioc3_stop(ip);
743 ioc3_init(dev);
744 ioc3_mii_init(ip);
746 netif_wake_queue(dev);
748 spin_unlock(&ip->ioc3_lock);
749 }
751 /* The interrupt handler does all of the Rx thread work and cleans up
752 after the Tx thread. */
753 static irqreturn_t ioc3_interrupt(int irq, void *_dev, struct pt_regs *regs)
754 {
755 struct net_device *dev = (struct net_device *)_dev;
756 struct ioc3_private *ip = netdev_priv(dev);
757 struct ioc3 *ioc3 = ip->regs;
758 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
759 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
760 EISR_TXEXPLICIT | EISR_TXMEMERR;
761 u32 eisr;
763 eisr = ioc3_r_eisr() & enabled;
765 ioc3_w_eisr(eisr);
766 (void) ioc3_r_eisr(); /* Flush */
768 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
769 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
770 ioc3_error(ip, eisr);
771 if (eisr & EISR_RXTIMERINT)
772 ioc3_rx(ip);
773 if (eisr & EISR_TXEXPLICIT)
774 ioc3_tx(ip);
776 return IRQ_HANDLED;
777 }
779 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
780 {
781 struct ioc3 *ioc3 = ip->regs;
783 if (ip->mii.full_duplex) {
784 ioc3_w_etcsr(ETCSR_FD);
785 ip->emcr |= EMCR_DUPLEX;
786 } else {
787 ioc3_w_etcsr(ETCSR_HD);
788 ip->emcr &= ~EMCR_DUPLEX;
789 }
790 ioc3_w_emcr(ip->emcr);
791 }
793 static void ioc3_timer(unsigned long data)
794 {
795 struct ioc3_private *ip = (struct ioc3_private *) data;
797 /* Print the link status if it has changed */
798 mii_check_media(&ip->mii, 1, 0);
799 ioc3_setup_duplex(ip);
801 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
802 add_timer(&ip->ioc3_timer);
803 }
805 /*
806 * Try to find a PHY. There is no apparent relation between the MII addresses
807 * in the SGI documentation and what we find in reality, so we simply probe
808 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
809 * onboard IOC3s has the special oddity that probing doesn't seem to find it
810 * yet the interface seems to work fine, so if probing fails we for now will
811 * simply default to PHY 31 instead of bailing out.
812 */
813 static int ioc3_mii_init(struct ioc3_private *ip)
814 {
815 struct net_device *dev = priv_netdev(ip);
816 int i, found = 0, res = 0;
817 int ioc3_phy_workaround = 1;
818 u16 word;
820 for (i = 0; i < 32; i++) {
821 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
823 if (word != 0xffff && word != 0x0000) {
824 found = 1;
825 break; /* Found a PHY */
826 }
827 }
829 if (!found) {
830 if (ioc3_phy_workaround)
831 i = 31;
832 else {
833 ip->mii.phy_id = -1;
834 res = -ENODEV;
835 goto out;
836 }
837 }
839 ip->mii.phy_id = i;
840 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
841 ip->ioc3_timer.data = (unsigned long) ip;
842 ip->ioc3_timer.function = &ioc3_timer;
843 add_timer(&ip->ioc3_timer);
845 out:
846 return res;
847 }
849 static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
850 {
851 struct sk_buff *skb;
852 int i;
854 for (i = ip->rx_ci; i & 15; i++) {
855 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
856 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
857 }
858 ip->rx_pi &= 511;
859 ip->rx_ci &= 511;
861 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
862 struct ioc3_erxbuf *rxb;
863 skb = ip->rx_skbs[i];
864 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
865 rxb->w0 = 0;
866 }
867 }
869 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
870 {
871 struct sk_buff *skb;
872 int i;
874 for (i=0; i < 128; i++) {
875 skb = ip->tx_skbs[i];
876 if (skb) {
877 ip->tx_skbs[i] = NULL;
878 dev_kfree_skb_any(skb);
879 }
880 ip->txr[i].cmd = 0;
881 }
882 ip->tx_pi = 0;
883 ip->tx_ci = 0;
884 }
886 static void ioc3_free_rings(struct ioc3_private *ip)
887 {
888 struct sk_buff *skb;
889 int rx_entry, n_entry;
891 if (ip->txr) {
892 ioc3_clean_tx_ring(ip);
893 free_pages((unsigned long)ip->txr, 2);
894 ip->txr = NULL;
895 }
897 if (ip->rxr) {
898 n_entry = ip->rx_ci;
899 rx_entry = ip->rx_pi;
901 while (n_entry != rx_entry) {
902 skb = ip->rx_skbs[n_entry];
903 if (skb)
904 dev_kfree_skb_any(skb);
906 n_entry = (n_entry + 1) & 511;
907 }
908 free_page((unsigned long)ip->rxr);
909 ip->rxr = NULL;
910 }
911 }
913 static void ioc3_alloc_rings(struct net_device *dev)
914 {
915 struct ioc3_private *ip = netdev_priv(dev);
916 struct ioc3_erxbuf *rxb;
917 unsigned long *rxr;
918 int i;
920 if (ip->rxr == NULL) {
921 /* Allocate and initialize rx ring. 4kb = 512 entries */
922 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
923 rxr = (unsigned long *) ip->rxr;
924 if (!rxr)
925 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
927 /* Now the rx buffers. The RX ring may be larger but
928 we only allocate 16 buffers for now. Need to tune
929 this for performance and memory later. */
930 for (i = 0; i < RX_BUFFS; i++) {
931 struct sk_buff *skb;
933 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
934 if (!skb) {
935 show_free_areas();
936 continue;
937 }
939 ip->rx_skbs[i] = skb;
940 skb->dev = dev;
942 /* Because we reserve afterwards. */
943 skb_put(skb, (1664 + RX_OFFSET));
944 rxb = (struct ioc3_erxbuf *) skb->data;
945 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
946 skb_reserve(skb, RX_OFFSET);
947 }
948 ip->rx_ci = 0;
949 ip->rx_pi = RX_BUFFS;
950 }
952 if (ip->txr == NULL) {
953 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
954 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
955 if (!ip->txr)
956 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
957 ip->tx_pi = 0;
958 ip->tx_ci = 0;
959 }
960 }
962 static void ioc3_init_rings(struct net_device *dev)
963 {
964 struct ioc3_private *ip = netdev_priv(dev);
965 struct ioc3 *ioc3 = ip->regs;
966 unsigned long ring;
968 ioc3_free_rings(ip);
969 ioc3_alloc_rings(dev);
971 ioc3_clean_rx_ring(ip);
972 ioc3_clean_tx_ring(ip);
974 /* Now the rx ring base, consume & produce registers. */
975 ring = ioc3_map(ip->rxr, 0);
976 ioc3_w_erbr_h(ring >> 32);
977 ioc3_w_erbr_l(ring & 0xffffffff);
978 ioc3_w_ercir(ip->rx_ci << 3);
979 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
981 ring = ioc3_map(ip->txr, 0);
983 ip->txqlen = 0; /* nothing queued */
985 /* Now the tx ring base, consume & produce registers. */
986 ioc3_w_etbr_h(ring >> 32);
987 ioc3_w_etbr_l(ring & 0xffffffff);
988 ioc3_w_etpir(ip->tx_pi << 7);
989 ioc3_w_etcir(ip->tx_ci << 7);
990 (void) ioc3_r_etcir(); /* Flush */
991 }
993 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
994 {
995 struct ioc3 *ioc3 = ip->regs;
996 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
997 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
998 unsigned int pattern = 0x5555;
1000 /* Assume the larger size SSRAM and enable parity checking */
1001 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
1003 *ssram0 = pattern;
1004 *ssram1 = ~pattern & IOC3_SSRAM_DM;
1006 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
1007 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
1008 /* set ssram size to 64 KB */
1009 ip->emcr = EMCR_RAMPAR;
1010 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
1011 } else
1012 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
1015 static void ioc3_init(struct net_device *dev)
1017 struct ioc3_private *ip = netdev_priv(dev);
1018 struct ioc3 *ioc3 = ip->regs;
1020 del_timer(&ip->ioc3_timer); /* Kill if running */
1022 ioc3_w_emcr(EMCR_RST); /* Reset */
1023 (void) ioc3_r_emcr(); /* Flush WB */
1024 udelay(4); /* Give it time ... */
1025 ioc3_w_emcr(0);
1026 (void) ioc3_r_emcr();
1028 /* Misc registers */
1029 #ifdef CONFIG_SGI_IP27
1030 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1031 #else
1032 ioc3_w_erbar(0); /* Let PCI API get it right */
1033 #endif
1034 (void) ioc3_r_etcdc(); /* Clear on read */
1035 ioc3_w_ercsr(15); /* RX low watermark */
1036 ioc3_w_ertr(0); /* Interrupt immediately */
1037 __ioc3_set_mac_address(dev);
1038 ioc3_w_ehar_h(ip->ehar_h);
1039 ioc3_w_ehar_l(ip->ehar_l);
1040 ioc3_w_ersr(42); /* XXX should be random */
1042 ioc3_init_rings(dev);
1044 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1045 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1046 ioc3_w_emcr(ip->emcr);
1047 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1048 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1049 EISR_TXEXPLICIT | EISR_TXMEMERR);
1050 (void) ioc3_r_eier();
1053 static inline void ioc3_stop(struct ioc3_private *ip)
1055 struct ioc3 *ioc3 = ip->regs;
1057 ioc3_w_emcr(0); /* Shutup */
1058 ioc3_w_eier(0); /* Disable interrupts */
1059 (void) ioc3_r_eier(); /* Flush */
1062 static int ioc3_open(struct net_device *dev)
1064 struct ioc3_private *ip = netdev_priv(dev);
1066 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1067 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1069 return -EAGAIN;
1072 ip->ehar_h = 0;
1073 ip->ehar_l = 0;
1074 ioc3_init(dev);
1076 netif_start_queue(dev);
1077 return 0;
1080 static int ioc3_close(struct net_device *dev)
1082 struct ioc3_private *ip = netdev_priv(dev);
1084 del_timer(&ip->ioc3_timer);
1086 netif_stop_queue(dev);
1088 ioc3_stop(ip);
1089 free_irq(dev->irq, dev);
1091 ioc3_free_rings(ip);
1092 return 0;
1095 /*
1096 * MENET cards have four IOC3 chips, which are attached to two sets of
1097 * PCI slot resources each: the primary connections are on slots
1098 * 0..3 and the secondaries are on 4..7
1100 * All four ethernets are brought out to connectors; six serial ports
1101 * (a pair from each of the first three IOC3s) are brought out to
1102 * MiniDINs; all other subdevices are left swinging in the wind, leave
1103 * them disabled.
1104 */
1105 static inline int ioc3_is_menet(struct pci_dev *pdev)
1107 struct pci_dev *dev;
1109 return pdev->bus->parent == NULL
1110 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0)))
1111 && dev->vendor == PCI_VENDOR_ID_SGI
1112 && dev->device == PCI_DEVICE_ID_SGI_IOC3
1113 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0)))
1114 && dev->vendor == PCI_VENDOR_ID_SGI
1115 && dev->device == PCI_DEVICE_ID_SGI_IOC3
1116 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0)))
1117 && dev->vendor == PCI_VENDOR_ID_SGI
1118 && dev->device == PCI_DEVICE_ID_SGI_IOC3;
1121 #ifdef CONFIG_SERIAL_8250
1122 /*
1123 * Note about serial ports and consoles:
1124 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1125 * connected to the master node (look in ip27_setup_console() and
1126 * ip27prom_console_write()).
1128 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1129 * addresses on a partitioned machine. Since we currently use the ioc3
1130 * serial ports, we use dynamic serial port discovery that the serial.c
1131 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1132 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1133 * than UARTB's, although UARTA on o200s has traditionally been known as
1134 * port 0. So, we just use one serial port from each ioc3 (since the
1135 * serial driver adds addresses to get to higher ports).
1137 * The first one to do a register_console becomes the preferred console
1138 * (if there is no kernel command line console= directive). /dev/console
1139 * (ie 5, 1) is then "aliased" into the device number returned by the
1140 * "device" routine referred to in this console structure
1141 * (ip27prom_console_dev).
1143 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1144 * around ioc3 oddities in this respect.
1146 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
1147 */
1149 static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1151 struct uart_port port;
1153 /*
1154 * We need to recognice and treat the fourth MENET serial as it
1155 * does not have an SuperIO chip attached to it, therefore attempting
1156 * to access it will result in bus errors. We call something an
1157 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1158 * in it. This is paranoid but we want to avoid blowing up on a
1159 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1160 * not paranoid enough ...
1161 */
1162 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1163 return;
1165 /*
1166 * Register to interrupt zero because we share the interrupt with
1167 * the serial driver which we don't properly support yet.
1169 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already
1170 * been registered.
1171 */
1172 memset(&port, 0, sizeof(port));
1173 port.irq = 0;
1174 port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1175 port.iotype = UPIO_MEM;
1176 port.regshift = 0;
1177 port.uartclk = 22000000 / 3;
1179 port.membase = (unsigned char *) &ioc3->sregs.uarta;
1180 serial8250_register_port(&port);
1182 port.membase = (unsigned char *) &ioc3->sregs.uartb;
1183 serial8250_register_port(&port);
1185 #endif
1187 static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1189 unsigned int sw_physid1, sw_physid2;
1190 struct net_device *dev = NULL;
1191 struct ioc3_private *ip;
1192 struct ioc3 *ioc3;
1193 unsigned long ioc3_base, ioc3_size;
1194 u32 vendor, model, rev;
1195 int err, pci_using_dac;
1197 /* Configure DMA attributes. */
1198 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1199 if (!err) {
1200 pci_using_dac = 1;
1201 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1202 if (err < 0) {
1203 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1204 "for consistent allocations\n", pci_name(pdev));
1205 goto out;
1207 } else {
1208 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1209 if (err) {
1210 printk(KERN_ERR "%s: No usable DMA configuration, "
1211 "aborting.\n", pci_name(pdev));
1212 goto out;
1214 pci_using_dac = 0;
1217 if (pci_enable_device(pdev))
1218 return -ENODEV;
1220 dev = alloc_etherdev(sizeof(struct ioc3_private));
1221 if (!dev) {
1222 err = -ENOMEM;
1223 goto out_disable;
1226 if (pci_using_dac)
1227 dev->features |= NETIF_F_HIGHDMA;
1229 err = pci_request_regions(pdev, "ioc3");
1230 if (err)
1231 goto out_free;
1233 SET_MODULE_OWNER(dev);
1234 SET_NETDEV_DEV(dev, &pdev->dev);
1236 ip = netdev_priv(dev);
1238 dev->irq = pdev->irq;
1240 ioc3_base = pci_resource_start(pdev, 0);
1241 ioc3_size = pci_resource_len(pdev, 0);
1242 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1243 if (!ioc3) {
1244 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1245 pci_name(pdev));
1246 err = -ENOMEM;
1247 goto out_res;
1249 ip->regs = ioc3;
1251 #ifdef CONFIG_SERIAL_8250
1252 ioc3_serial_probe(pdev, ioc3);
1253 #endif
1255 spin_lock_init(&ip->ioc3_lock);
1256 init_timer(&ip->ioc3_timer);
1258 ioc3_stop(ip);
1259 ioc3_init(dev);
1261 ip->pdev = pdev;
1263 ip->mii.phy_id_mask = 0x1f;
1264 ip->mii.reg_num_mask = 0x1f;
1265 ip->mii.dev = dev;
1266 ip->mii.mdio_read = ioc3_mdio_read;
1267 ip->mii.mdio_write = ioc3_mdio_write;
1269 ioc3_mii_init(ip);
1271 if (ip->mii.phy_id == -1) {
1272 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1273 pci_name(pdev));
1274 err = -ENODEV;
1275 goto out_stop;
1278 ioc3_ssram_disc(ip);
1279 ioc3_get_eaddr(ip);
1281 /* The IOC3-specific entries in the device structure. */
1282 dev->open = ioc3_open;
1283 dev->hard_start_xmit = ioc3_start_xmit;
1284 dev->tx_timeout = ioc3_timeout;
1285 dev->watchdog_timeo = 5 * HZ;
1286 dev->stop = ioc3_close;
1287 dev->get_stats = ioc3_get_stats;
1288 dev->do_ioctl = ioc3_ioctl;
1289 dev->set_multicast_list = ioc3_set_multicast_list;
1290 dev->set_mac_address = ioc3_set_mac_address;
1291 dev->ethtool_ops = &ioc3_ethtool_ops;
1292 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1293 dev->features = NETIF_F_IP_CSUM;
1294 #endif
1296 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1297 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1299 err = register_netdev(dev);
1300 if (err)
1301 goto out_stop;
1303 mii_check_media(&ip->mii, 1, 1);
1304 ioc3_setup_duplex(ip);
1306 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1307 model = (sw_physid2 >> 4) & 0x3f;
1308 rev = sw_physid2 & 0xf;
1309 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1310 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1311 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1312 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1314 return 0;
1316 out_stop:
1317 ioc3_stop(ip);
1318 ioc3_free_rings(ip);
1319 out_res:
1320 pci_release_regions(pdev);
1321 out_free:
1322 free_netdev(dev);
1323 out_disable:
1324 /*
1325 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1326 * such a weird device ...
1327 */
1328 out:
1329 return err;
1332 static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1334 struct net_device *dev = pci_get_drvdata(pdev);
1335 struct ioc3_private *ip = netdev_priv(dev);
1336 struct ioc3 *ioc3 = ip->regs;
1338 unregister_netdev(dev);
1339 iounmap(ioc3);
1340 pci_release_regions(pdev);
1341 free_netdev(dev);
1342 /*
1343 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1344 * such a weird device ...
1345 */
1348 static struct pci_device_id ioc3_pci_tbl[] = {
1349 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1350 { 0 }
1351 };
1352 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1354 static struct pci_driver ioc3_driver = {
1355 .name = "ioc3-eth",
1356 .id_table = ioc3_pci_tbl,
1357 .probe = ioc3_probe,
1358 .remove = __devexit_p(ioc3_remove_one),
1359 };
1361 static int __init ioc3_init_module(void)
1363 return pci_register_driver(&ioc3_driver);
1366 static void __exit ioc3_cleanup_module(void)
1368 pci_unregister_driver(&ioc3_driver);
1371 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1373 unsigned long data;
1374 struct ioc3_private *ip = netdev_priv(dev);
1375 struct ioc3 *ioc3 = ip->regs;
1376 unsigned int len;
1377 struct ioc3_etxd *desc;
1378 uint32_t w0 = 0;
1379 int produce;
1381 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1382 /*
1383 * IOC3 has a fairly simple minded checksumming hardware which simply
1384 * adds up the 1's complement checksum for the entire packet and
1385 * inserts it at an offset which can be specified in the descriptor
1386 * into the transmit packet. This means we have to compensate for the
1387 * MAC header which should not be summed and the TCP/UDP pseudo headers
1388 * manually.
1389 */
1390 if (skb->ip_summed == CHECKSUM_HW) {
1391 int proto = ntohs(skb->nh.iph->protocol);
1392 unsigned int csoff;
1393 struct iphdr *ih = skb->nh.iph;
1394 uint32_t csum, ehsum;
1395 uint16_t *eh;
1397 /* The MAC header. skb->mac seem the logic approach
1398 to find the MAC header - except it's a NULL pointer ... */
1399 eh = (uint16_t *) skb->data;
1401 /* Sum up dest addr, src addr and protocol */
1402 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1404 /* Fold ehsum. can't use csum_fold which negates also ... */
1405 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1406 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1408 /* Skip IP header; it's sum is always zero and was
1409 already filled in by ip_output.c */
1410 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1411 ih->tot_len - (ih->ihl << 2),
1412 proto, 0xffff ^ ehsum);
1414 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1415 csum = (csum & 0xffff) + (csum >> 16);
1417 csoff = ETH_HLEN + (ih->ihl << 2);
1418 if (proto == IPPROTO_UDP) {
1419 csoff += offsetof(struct udphdr, check);
1420 skb->h.uh->check = csum;
1422 if (proto == IPPROTO_TCP) {
1423 csoff += offsetof(struct tcphdr, check);
1424 skb->h.th->check = csum;
1427 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1429 #endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
1431 spin_lock_irq(&ip->ioc3_lock);
1433 data = (unsigned long) skb->data;
1434 len = skb->len;
1436 produce = ip->tx_pi;
1437 desc = &ip->txr[produce];
1439 if (len <= 104) {
1440 /* Short packet, let's copy it directly into the ring. */
1441 memcpy(desc->data, skb->data, skb->len);
1442 if (len < ETH_ZLEN) {
1443 /* Very short packet, pad with zeros at the end. */
1444 memset(desc->data + len, 0, ETH_ZLEN - len);
1445 len = ETH_ZLEN;
1447 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1448 desc->bufcnt = cpu_to_be32(len);
1449 } else if ((data ^ (data + len - 1)) & 0x4000) {
1450 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1451 unsigned long s1 = b2 - data;
1452 unsigned long s2 = data + len - b2;
1454 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1455 ETXD_B1V | ETXD_B2V | w0);
1456 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1457 (s2 << ETXD_B2CNT_SHIFT));
1458 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1459 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1460 } else {
1461 /* Normal sized packet that doesn't cross a page boundary. */
1462 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1463 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1464 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1467 BARRIER();
1469 dev->trans_start = jiffies;
1470 ip->tx_skbs[produce] = skb; /* Remember skb */
1471 produce = (produce + 1) & 127;
1472 ip->tx_pi = produce;
1473 ioc3_w_etpir(produce << 7); /* Fire ... */
1475 ip->txqlen++;
1477 if (ip->txqlen >= 127)
1478 netif_stop_queue(dev);
1480 spin_unlock_irq(&ip->ioc3_lock);
1482 return 0;
1485 static void ioc3_timeout(struct net_device *dev)
1487 struct ioc3_private *ip = netdev_priv(dev);
1489 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1491 spin_lock_irq(&ip->ioc3_lock);
1493 ioc3_stop(ip);
1494 ioc3_init(dev);
1495 ioc3_mii_init(ip);
1497 spin_unlock_irq(&ip->ioc3_lock);
1499 netif_wake_queue(dev);
1502 /*
1503 * Given a multicast ethernet address, this routine calculates the
1504 * address's bit index in the logical address filter mask
1505 */
1507 static inline unsigned int ioc3_hash(const unsigned char *addr)
1509 unsigned int temp = 0;
1510 u32 crc;
1511 int bits;
1513 crc = ether_crc_le(ETH_ALEN, addr);
1515 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1516 for (bits = 6; --bits >= 0; ) {
1517 temp <<= 1;
1518 temp |= (crc & 0x1);
1519 crc >>= 1;
1522 return temp;
1525 static void ioc3_get_drvinfo (struct net_device *dev,
1526 struct ethtool_drvinfo *info)
1528 struct ioc3_private *ip = netdev_priv(dev);
1530 strcpy (info->driver, IOC3_NAME);
1531 strcpy (info->version, IOC3_VERSION);
1532 strcpy (info->bus_info, pci_name(ip->pdev));
1535 static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1537 struct ioc3_private *ip = netdev_priv(dev);
1538 int rc;
1540 spin_lock_irq(&ip->ioc3_lock);
1541 rc = mii_ethtool_gset(&ip->mii, cmd);
1542 spin_unlock_irq(&ip->ioc3_lock);
1544 return rc;
1547 static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1549 struct ioc3_private *ip = netdev_priv(dev);
1550 int rc;
1552 spin_lock_irq(&ip->ioc3_lock);
1553 rc = mii_ethtool_sset(&ip->mii, cmd);
1554 spin_unlock_irq(&ip->ioc3_lock);
1556 return rc;
1559 static int ioc3_nway_reset(struct net_device *dev)
1561 struct ioc3_private *ip = netdev_priv(dev);
1562 int rc;
1564 spin_lock_irq(&ip->ioc3_lock);
1565 rc = mii_nway_restart(&ip->mii);
1566 spin_unlock_irq(&ip->ioc3_lock);
1568 return rc;
1571 static u32 ioc3_get_link(struct net_device *dev)
1573 struct ioc3_private *ip = netdev_priv(dev);
1574 int rc;
1576 spin_lock_irq(&ip->ioc3_lock);
1577 rc = mii_link_ok(&ip->mii);
1578 spin_unlock_irq(&ip->ioc3_lock);
1580 return rc;
1583 static struct ethtool_ops ioc3_ethtool_ops = {
1584 .get_drvinfo = ioc3_get_drvinfo,
1585 .get_settings = ioc3_get_settings,
1586 .set_settings = ioc3_set_settings,
1587 .nway_reset = ioc3_nway_reset,
1588 .get_link = ioc3_get_link,
1589 };
1591 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1593 struct ioc3_private *ip = netdev_priv(dev);
1594 int rc;
1596 spin_lock_irq(&ip->ioc3_lock);
1597 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1598 spin_unlock_irq(&ip->ioc3_lock);
1600 return rc;
1603 static void ioc3_set_multicast_list(struct net_device *dev)
1605 struct dev_mc_list *dmi = dev->mc_list;
1606 struct ioc3_private *ip = netdev_priv(dev);
1607 struct ioc3 *ioc3 = ip->regs;
1608 u64 ehar = 0;
1609 int i;
1611 netif_stop_queue(dev); /* Lock out others. */
1613 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1614 /* Unconditionally log net taps. */
1615 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1616 ip->emcr |= EMCR_PROMISC;
1617 ioc3_w_emcr(ip->emcr);
1618 (void) ioc3_r_emcr();
1619 } else {
1620 ip->emcr &= ~EMCR_PROMISC;
1621 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1622 (void) ioc3_r_emcr();
1624 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1625 /* Too many for hashing to make sense or we want all
1626 multicast packets anyway, so skip computing all the
1627 hashes and just accept all packets. */
1628 ip->ehar_h = 0xffffffff;
1629 ip->ehar_l = 0xffffffff;
1630 } else {
1631 for (i = 0; i < dev->mc_count; i++) {
1632 char *addr = dmi->dmi_addr;
1633 dmi = dmi->next;
1635 if (!(*addr & 1))
1636 continue;
1638 ehar |= (1UL << ioc3_hash(addr));
1640 ip->ehar_h = ehar >> 32;
1641 ip->ehar_l = ehar & 0xffffffff;
1643 ioc3_w_ehar_h(ip->ehar_h);
1644 ioc3_w_ehar_l(ip->ehar_l);
1647 netif_wake_queue(dev); /* Let us get going again. */
1650 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1651 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1652 MODULE_LICENSE("GPL");
1654 module_init(ioc3_init_module);
1655 module_exit(ioc3_cleanup_module);