ia64/linux-2.6.18-xen.hg

view drivers/net/gianfar.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * drivers/net/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 *
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * Still left to do:
19 * -Add support for module parameters
20 * -Add patch for ethtool phys id
21 */
22 #ifndef __GIANFAR_H
23 #define __GIANFAR_H
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/mm.h>
38 #include <linux/mii.h>
39 #include <linux/phy.h>
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44 #include <linux/module.h>
45 #include <linux/crc32.h>
46 #include <linux/workqueue.h>
47 #include <linux/ethtool.h>
48 #include <linux/netdevice.h>
49 #include <linux/fsl_devices.h>
50 #include "gianfar_mii.h"
52 /* The maximum number of packets to be handled in one call of gfar_poll */
53 #define GFAR_DEV_WEIGHT 64
55 /* Length for FCB */
56 #define GMAC_FCB_LEN 8
58 /* Default padding amount */
59 #define DEFAULT_PADDING 2
61 /* Number of bytes to align the rx bufs to */
62 #define RXBUF_ALIGNMENT 64
64 /* The number of bytes which composes a unit for the purpose of
65 * allocating data buffers. ie-for any given MTU, the data buffer
66 * will be the next highest multiple of 512 bytes. */
67 #define INCREMENTAL_BUFFER_SIZE 512
70 #define MAC_ADDR_LEN 6
72 #define PHY_INIT_TIMEOUT 100000
73 #define GFAR_PHY_CHANGE_TIME 2
75 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
76 #define DRV_NAME "gfar-enet"
77 extern const char gfar_driver_name[];
78 extern const char gfar_driver_version[];
80 /* These need to be powers of 2 for this driver */
81 #ifdef CONFIG_GFAR_NAPI
82 #define DEFAULT_TX_RING_SIZE 256
83 #define DEFAULT_RX_RING_SIZE 256
84 #else
85 #define DEFAULT_TX_RING_SIZE 64
86 #define DEFAULT_RX_RING_SIZE 64
87 #endif
89 #define GFAR_RX_MAX_RING_SIZE 256
90 #define GFAR_TX_MAX_RING_SIZE 256
92 #define GFAR_MAX_FIFO_THRESHOLD 511
93 #define GFAR_MAX_FIFO_STARVE 511
94 #define GFAR_MAX_FIFO_STARVE_OFF 511
96 #define DEFAULT_RX_BUFFER_SIZE 1536
97 #define TX_RING_MOD_MASK(size) (size-1)
98 #define RX_RING_MOD_MASK(size) (size-1)
99 #define JUMBO_BUFFER_SIZE 9728
100 #define JUMBO_FRAME_SIZE 9600
102 #define DEFAULT_FIFO_TX_THR 0x100
103 #define DEFAULT_FIFO_TX_STARVE 0x40
104 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
105 #define DEFAULT_BD_STASH 1
106 #define DEFAULT_STASH_LENGTH 64
107 #define DEFAULT_STASH_INDEX 0
109 /* The number of Exact Match registers */
110 #define GFAR_EM_NUM 15
112 /* Latency of interface clock in nanoseconds */
113 /* Interface clock latency , in this case, means the
114 * time described by a value of 1 in the interrupt
115 * coalescing registers' time fields. Since those fields
116 * refer to the time it takes for 64 clocks to pass, the
117 * latencies are as such:
118 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
119 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
120 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
121 */
122 #define GFAR_GBIT_TIME 512
123 #define GFAR_100_TIME 2560
124 #define GFAR_10_TIME 25600
126 #define DEFAULT_TX_COALESCE 1
127 #define DEFAULT_TXCOUNT 16
128 #define DEFAULT_TXTIME 4
130 #define DEFAULT_RX_COALESCE 1
131 #define DEFAULT_RXCOUNT 16
132 #define DEFAULT_RXTIME 4
134 #define TBIPA_VALUE 0x1f
135 #define MIIMCFG_INIT_VALUE 0x00000007
136 #define MIIMCFG_RESET 0x80000000
137 #define MIIMIND_BUSY 0x00000001
139 /* MAC register bits */
140 #define MACCFG1_SOFT_RESET 0x80000000
141 #define MACCFG1_RESET_RX_MC 0x00080000
142 #define MACCFG1_RESET_TX_MC 0x00040000
143 #define MACCFG1_RESET_RX_FUN 0x00020000
144 #define MACCFG1_RESET_TX_FUN 0x00010000
145 #define MACCFG1_LOOPBACK 0x00000100
146 #define MACCFG1_RX_FLOW 0x00000020
147 #define MACCFG1_TX_FLOW 0x00000010
148 #define MACCFG1_SYNCD_RX_EN 0x00000008
149 #define MACCFG1_RX_EN 0x00000004
150 #define MACCFG1_SYNCD_TX_EN 0x00000002
151 #define MACCFG1_TX_EN 0x00000001
153 #define MACCFG2_INIT_SETTINGS 0x00007205
154 #define MACCFG2_FULL_DUPLEX 0x00000001
155 #define MACCFG2_IF 0x00000300
156 #define MACCFG2_MII 0x00000100
157 #define MACCFG2_GMII 0x00000200
158 #define MACCFG2_HUGEFRAME 0x00000020
159 #define MACCFG2_LENGTHCHECK 0x00000010
161 #define ECNTRL_INIT_SETTINGS 0x00001000
162 #define ECNTRL_TBI_MODE 0x00000020
163 #define ECNTRL_R100 0x00000008
165 #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
167 #define MINFLR_INIT_SETTINGS 0x00000040
169 /* Init to do tx snooping for buffers and descriptors */
170 #define DMACTRL_INIT_SETTINGS 0x000000c3
171 #define DMACTRL_GRS 0x00000010
172 #define DMACTRL_GTS 0x00000008
174 #define TSTAT_CLEAR_THALT 0x80000000
176 /* Interrupt coalescing macros */
177 #define IC_ICEN 0x80000000
178 #define IC_ICFT_MASK 0x1fe00000
179 #define IC_ICFT_SHIFT 21
180 #define mk_ic_icft(x) \
181 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
182 #define IC_ICTT_MASK 0x0000ffff
183 #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
185 #define mk_ic_value(count, time) (IC_ICEN | \
186 mk_ic_icft(count) | \
187 mk_ic_ictt(time))
189 #define RCTRL_PAL_MASK 0x001f0000
190 #define RCTRL_VLEX 0x00002000
191 #define RCTRL_FILREN 0x00001000
192 #define RCTRL_GHTX 0x00000400
193 #define RCTRL_IPCSEN 0x00000200
194 #define RCTRL_TUCSEN 0x00000100
195 #define RCTRL_PRSDEP_MASK 0x000000c0
196 #define RCTRL_PRSDEP_INIT 0x000000c0
197 #define RCTRL_PROM 0x00000008
198 #define RCTRL_EMEN 0x00000002
199 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
200 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
201 #define RCTRL_EXTHASH (RCTRL_GHTX)
202 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
203 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
206 #define RSTAT_CLEAR_RHALT 0x00800000
208 #define TCTRL_IPCSEN 0x00004000
209 #define TCTRL_TUCSEN 0x00002000
210 #define TCTRL_VLINS 0x00001000
211 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
213 #define IEVENT_INIT_CLEAR 0xffffffff
214 #define IEVENT_BABR 0x80000000
215 #define IEVENT_RXC 0x40000000
216 #define IEVENT_BSY 0x20000000
217 #define IEVENT_EBERR 0x10000000
218 #define IEVENT_MSRO 0x04000000
219 #define IEVENT_GTSC 0x02000000
220 #define IEVENT_BABT 0x01000000
221 #define IEVENT_TXC 0x00800000
222 #define IEVENT_TXE 0x00400000
223 #define IEVENT_TXB 0x00200000
224 #define IEVENT_TXF 0x00100000
225 #define IEVENT_LC 0x00040000
226 #define IEVENT_CRL 0x00020000
227 #define IEVENT_XFUN 0x00010000
228 #define IEVENT_RXB0 0x00008000
229 #define IEVENT_GRSC 0x00000100
230 #define IEVENT_RXF0 0x00000080
231 #define IEVENT_FIR 0x00000008
232 #define IEVENT_FIQ 0x00000004
233 #define IEVENT_DPE 0x00000002
234 #define IEVENT_PERR 0x00000001
235 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
236 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
237 #define IEVENT_ERR_MASK \
238 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
239 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
240 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
242 #define IMASK_INIT_CLEAR 0x00000000
243 #define IMASK_BABR 0x80000000
244 #define IMASK_RXC 0x40000000
245 #define IMASK_BSY 0x20000000
246 #define IMASK_EBERR 0x10000000
247 #define IMASK_MSRO 0x04000000
248 #define IMASK_GRSC 0x02000000
249 #define IMASK_BABT 0x01000000
250 #define IMASK_TXC 0x00800000
251 #define IMASK_TXEEN 0x00400000
252 #define IMASK_TXBEN 0x00200000
253 #define IMASK_TXFEN 0x00100000
254 #define IMASK_LC 0x00040000
255 #define IMASK_CRL 0x00020000
256 #define IMASK_XFUN 0x00010000
257 #define IMASK_RXB0 0x00008000
258 #define IMASK_GTSC 0x00000100
259 #define IMASK_RXFEN0 0x00000080
260 #define IMASK_FIR 0x00000008
261 #define IMASK_FIQ 0x00000004
262 #define IMASK_DPE 0x00000002
263 #define IMASK_PERR 0x00000001
264 #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
265 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
266 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
267 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
268 | IMASK_PERR)
270 /* Fifo management */
271 #define FIFO_TX_THR_MASK 0x01ff
272 #define FIFO_TX_STARVE_MASK 0x01ff
273 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
275 /* Attribute fields */
277 /* This enables rx snooping for buffers and descriptors */
278 #define ATTR_BDSTASH 0x00000800
280 #define ATTR_BUFSTASH 0x00004000
282 #define ATTR_SNOOPING 0x000000c0
283 #define ATTR_INIT_SETTINGS ATTR_SNOOPING
285 #define ATTRELI_INIT_SETTINGS 0x0
286 #define ATTRELI_EL_MASK 0x3fff0000
287 #define ATTRELI_EL(x) (x << 16)
288 #define ATTRELI_EI_MASK 0x00003fff
289 #define ATTRELI_EI(x) (x)
292 /* TxBD status field bits */
293 #define TXBD_READY 0x8000
294 #define TXBD_PADCRC 0x4000
295 #define TXBD_WRAP 0x2000
296 #define TXBD_INTERRUPT 0x1000
297 #define TXBD_LAST 0x0800
298 #define TXBD_CRC 0x0400
299 #define TXBD_DEF 0x0200
300 #define TXBD_HUGEFRAME 0x0080
301 #define TXBD_LATECOLLISION 0x0080
302 #define TXBD_RETRYLIMIT 0x0040
303 #define TXBD_RETRYCOUNTMASK 0x003c
304 #define TXBD_UNDERRUN 0x0002
305 #define TXBD_TOE 0x0002
307 /* Tx FCB param bits */
308 #define TXFCB_VLN 0x80
309 #define TXFCB_IP 0x40
310 #define TXFCB_IP6 0x20
311 #define TXFCB_TUP 0x10
312 #define TXFCB_UDP 0x08
313 #define TXFCB_CIP 0x04
314 #define TXFCB_CTU 0x02
315 #define TXFCB_NPH 0x01
316 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
318 /* RxBD status field bits */
319 #define RXBD_EMPTY 0x8000
320 #define RXBD_RO1 0x4000
321 #define RXBD_WRAP 0x2000
322 #define RXBD_INTERRUPT 0x1000
323 #define RXBD_LAST 0x0800
324 #define RXBD_FIRST 0x0400
325 #define RXBD_MISS 0x0100
326 #define RXBD_BROADCAST 0x0080
327 #define RXBD_MULTICAST 0x0040
328 #define RXBD_LARGE 0x0020
329 #define RXBD_NONOCTET 0x0010
330 #define RXBD_SHORT 0x0008
331 #define RXBD_CRCERR 0x0004
332 #define RXBD_OVERRUN 0x0002
333 #define RXBD_TRUNCATED 0x0001
334 #define RXBD_STATS 0x01ff
336 /* Rx FCB status field bits */
337 #define RXFCB_VLN 0x8000
338 #define RXFCB_IP 0x4000
339 #define RXFCB_IP6 0x2000
340 #define RXFCB_TUP 0x1000
341 #define RXFCB_CIP 0x0800
342 #define RXFCB_CTU 0x0400
343 #define RXFCB_EIP 0x0200
344 #define RXFCB_ETU 0x0100
345 #define RXFCB_CSUM_MASK 0x0f00
346 #define RXFCB_PERR_MASK 0x000c
347 #define RXFCB_PERR_BADL3 0x0008
349 struct txbd8
350 {
351 u16 status; /* Status Fields */
352 u16 length; /* Buffer length */
353 u32 bufPtr; /* Buffer Pointer */
354 };
356 struct txfcb {
357 u8 flags;
358 u8 reserved;
359 u8 l4os; /* Level 4 Header Offset */
360 u8 l3os; /* Level 3 Header Offset */
361 u16 phcs; /* Pseudo-header Checksum */
362 u16 vlctl; /* VLAN control word */
363 };
365 struct rxbd8
366 {
367 u16 status; /* Status Fields */
368 u16 length; /* Buffer Length */
369 u32 bufPtr; /* Buffer Pointer */
370 };
372 struct rxfcb {
373 u16 flags;
374 u8 rq; /* Receive Queue index */
375 u8 pro; /* Layer 4 Protocol */
376 u16 reserved;
377 u16 vlctl; /* VLAN control word */
378 };
380 struct rmon_mib
381 {
382 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
383 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
384 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
385 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
386 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
387 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
388 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
389 u32 rbyt; /* 0x.69c - Receive Byte Counter */
390 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
391 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
392 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
393 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
394 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
395 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
396 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
397 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
398 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
399 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
400 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
401 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
402 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
403 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
404 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
405 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
406 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
407 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
408 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
409 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
410 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
411 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
412 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
413 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
414 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
415 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
416 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
417 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
418 u8 res1[4];
419 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
420 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
421 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
422 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
423 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
424 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
425 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
426 u32 car1; /* 0x.730 - Carry Register One */
427 u32 car2; /* 0x.734 - Carry Register Two */
428 u32 cam1; /* 0x.738 - Carry Mask Register One */
429 u32 cam2; /* 0x.73c - Carry Mask Register Two */
430 };
432 struct gfar_extra_stats {
433 u64 kernel_dropped;
434 u64 rx_large;
435 u64 rx_short;
436 u64 rx_nonoctet;
437 u64 rx_crcerr;
438 u64 rx_overrun;
439 u64 rx_bsy;
440 u64 rx_babr;
441 u64 rx_trunc;
442 u64 eberr;
443 u64 tx_babt;
444 u64 tx_underrun;
445 u64 rx_skbmissing;
446 u64 tx_timeout;
447 };
449 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
450 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
452 /* Number of stats in the stats structure (ignore car and cam regs)*/
453 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
455 #define GFAR_INFOSTR_LEN 32
457 struct gfar_stats {
458 u64 extra[GFAR_EXTRA_STATS_LEN];
459 u64 rmon[GFAR_RMON_LEN];
460 };
463 struct gfar {
464 u32 tsec_id; /* 0x.000 - Controller ID register */
465 u8 res1[12];
466 u32 ievent; /* 0x.010 - Interrupt Event Register */
467 u32 imask; /* 0x.014 - Interrupt Mask Register */
468 u32 edis; /* 0x.018 - Error Disabled Register */
469 u8 res2[4];
470 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
471 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
472 u32 ptv; /* 0x.028 - Pause Time Value Register */
473 u32 dmactrl; /* 0x.02c - DMA Control Register */
474 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
475 u8 res3[88];
476 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
477 u8 res4[8];
478 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
479 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
480 u8 res5[4];
481 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
482 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
483 u8 res6[84];
484 u32 tctrl; /* 0x.100 - Transmit Control Register */
485 u32 tstat; /* 0x.104 - Transmit Status Register */
486 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
487 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
488 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
489 u32 tqueue; /* 0x.114 - Transmit queue control register */
490 u8 res7[40];
491 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
492 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
493 u8 res8[52];
494 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
495 u8 res9a[4];
496 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
497 u8 res9b[4];
498 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
499 u8 res9c[4];
500 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
501 u8 res9d[4];
502 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
503 u8 res9e[4];
504 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
505 u8 res9f[4];
506 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
507 u8 res9g[4];
508 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
509 u8 res9h[4];
510 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
511 u8 res9[64];
512 u32 tbaseh; /* 0x.200 - TxBD base address high */
513 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
514 u8 res10a[4];
515 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
516 u8 res10b[4];
517 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
518 u8 res10c[4];
519 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
520 u8 res10d[4];
521 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
522 u8 res10e[4];
523 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
524 u8 res10f[4];
525 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
526 u8 res10g[4];
527 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
528 u8 res10[192];
529 u32 rctrl; /* 0x.300 - Receive Control Register */
530 u32 rstat; /* 0x.304 - Receive Status Register */
531 u8 res12[8];
532 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
533 u32 rqueue; /* 0x.314 - Receive queue control register */
534 u8 res13[24];
535 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
536 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
537 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
538 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
539 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
540 u8 res14[56];
541 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
542 u8 res15a[4];
543 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
544 u8 res15b[4];
545 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
546 u8 res15c[4];
547 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
548 u8 res15d[4];
549 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
550 u8 res15e[4];
551 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
552 u8 res15f[4];
553 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
554 u8 res15g[4];
555 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
556 u8 res15h[4];
557 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
558 u8 res16[64];
559 u32 rbaseh; /* 0x.400 - RxBD base address high */
560 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
561 u8 res17a[4];
562 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
563 u8 res17b[4];
564 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
565 u8 res17c[4];
566 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
567 u8 res17d[4];
568 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
569 u8 res17e[4];
570 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
571 u8 res17f[4];
572 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
573 u8 res17g[4];
574 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
575 u8 res17[192];
576 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
577 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
578 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
579 u32 hafdup; /* 0x.50c - Half Duplex Register */
580 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
581 u8 res18[12];
582 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
583 u8 res19[4];
584 u32 ifstat; /* 0x.53c - Interface Status Register */
585 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
586 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
587 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
588 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
589 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
590 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
591 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
592 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
593 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
594 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
595 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
596 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
597 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
598 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
599 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
600 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
601 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
602 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
603 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
604 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
605 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
606 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
607 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
608 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
609 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
610 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
611 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
612 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
613 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
614 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
615 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
616 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
617 u8 res20[192];
618 struct rmon_mib rmon; /* 0x.680-0x.73c */
619 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
620 u8 res21[188];
621 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
622 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
623 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
624 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
625 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
626 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
627 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
628 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
629 u8 res22[96];
630 u32 gaddr0; /* 0x.880 - Group address register 0 */
631 u32 gaddr1; /* 0x.884 - Group address register 1 */
632 u32 gaddr2; /* 0x.888 - Group address register 2 */
633 u32 gaddr3; /* 0x.88c - Group address register 3 */
634 u32 gaddr4; /* 0x.890 - Group address register 4 */
635 u32 gaddr5; /* 0x.894 - Group address register 5 */
636 u32 gaddr6; /* 0x.898 - Group address register 6 */
637 u32 gaddr7; /* 0x.89c - Group address register 7 */
638 u8 res23a[352];
639 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
640 u8 res23b[252];
641 u8 res23c[248];
642 u32 attr; /* 0x.bf8 - Attributes Register */
643 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
644 u8 res24[1024];
646 };
648 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
649 * (Ok, that's not so true anymore, but there is a family resemblence)
650 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
651 * and tx_bd_base always point to the currently available buffer.
652 * The dirty_tx tracks the current buffer that is being sent by the
653 * controller. The cur_tx and dirty_tx are equal under both completely
654 * empty and completely full conditions. The empty/ready indicator in
655 * the buffer descriptor determines the actual condition.
656 */
657 struct gfar_private {
658 /* Fields controlled by TX lock */
659 spinlock_t txlock;
661 /* Pointer to the array of skbuffs */
662 struct sk_buff ** tx_skbuff;
664 /* next free skb in the array */
665 u16 skb_curtx;
667 /* First skb in line to be transmitted */
668 u16 skb_dirtytx;
670 /* Configuration info for the coalescing features */
671 unsigned char txcoalescing;
672 unsigned short txcount;
673 unsigned short txtime;
675 /* Buffer descriptor pointers */
676 struct txbd8 *tx_bd_base; /* First tx buffer descriptor */
677 struct txbd8 *cur_tx; /* Next free ring entry */
678 struct txbd8 *dirty_tx; /* First buffer in line
679 to be transmitted */
680 unsigned int tx_ring_size;
682 /* RX Locked fields */
683 spinlock_t rxlock;
685 /* skb array and index */
686 struct sk_buff ** rx_skbuff;
687 u16 skb_currx;
689 /* RX Coalescing values */
690 unsigned char rxcoalescing;
691 unsigned short rxcount;
692 unsigned short rxtime;
694 struct rxbd8 *rx_bd_base; /* First Rx buffers */
695 struct rxbd8 *cur_rx; /* Next free rx ring entry */
697 /* RX parameters */
698 unsigned int rx_ring_size;
699 unsigned int rx_buffer_size;
700 unsigned int rx_stash_size;
701 unsigned int rx_stash_index;
703 struct vlan_group *vlgrp;
705 /* Unprotected fields */
706 /* Pointer to the GFAR memory mapped Registers */
707 struct gfar __iomem *regs;
709 /* Hash registers and their width */
710 u32 __iomem *hash_regs[16];
711 int hash_width;
713 /* global parameters */
714 unsigned int fifo_threshold;
715 unsigned int fifo_starve;
716 unsigned int fifo_starve_off;
718 unsigned char vlan_enable:1,
719 rx_csum_enable:1,
720 extended_hash:1,
721 bd_stash_en:1;
722 unsigned short padding;
724 unsigned int interruptTransmit;
725 unsigned int interruptReceive;
726 unsigned int interruptError;
728 /* info structure initialized by platform code */
729 struct gianfar_platform_data *einfo;
731 /* PHY stuff */
732 struct phy_device *phydev;
733 struct mii_bus *mii_bus;
734 int oldspeed;
735 int oldduplex;
736 int oldlink;
738 uint32_t msg_enable;
740 /* Network Statistics */
741 struct net_device_stats stats;
742 struct gfar_extra_stats extra_stats;
743 };
745 static inline u32 gfar_read(volatile unsigned __iomem *addr)
746 {
747 u32 val;
748 val = in_be32(addr);
749 return val;
750 }
752 static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
753 {
754 out_be32(addr, val);
755 }
757 extern struct ethtool_ops *gfar_op_array[];
759 extern irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
760 extern int startup_gfar(struct net_device *dev);
761 extern void stop_gfar(struct net_device *dev);
762 extern void gfar_halt(struct net_device *dev);
763 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
764 int enable, u32 regnum, u32 read);
765 void gfar_init_sysfs(struct net_device *dev);
767 #endif /* __GIANFAR_H */