ia64/linux-2.6.18-xen.hg

view drivers/net/dl2k.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
13 #ifndef __DL2K_H__
14 #define __DL2K_H__
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/string.h>
19 #include <linux/timer.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/init.h>
29 #include <linux/crc32.h>
30 #include <linux/ethtool.h>
31 #include <linux/bitops.h>
32 #include <asm/processor.h> /* Processor type for cache alignment. */
33 #include <asm/io.h>
34 #include <asm/uaccess.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/time.h>
38 #define TX_RING_SIZE 256
39 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
40 #define RX_RING_SIZE 256
41 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
42 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
44 /* This driver was written to use PCI memory space, however x86-oriented
45 hardware often uses I/O space accesses. */
46 #ifndef MEM_MAPPING
47 #undef readb
48 #undef readw
49 #undef readl
50 #undef writeb
51 #undef writew
52 #undef writel
53 #define readb inb
54 #define readw inw
55 #define readl inl
56 #define writeb outb
57 #define writew outw
58 #define writel outl
59 #endif
61 /* Offsets to the device registers.
62 Unlike software-only systems, device drivers interact with complex hardware.
63 It's not useful to define symbolic names for every register bit in the
64 device. The name can only partially document the semantics and make
65 the driver longer and more difficult to read.
66 In general, only the important configuration values or bits changed
67 multiple times should be defined symbolically.
68 */
69 enum dl2x_offsets {
70 /* I/O register offsets */
71 DMACtrl = 0x00,
72 RxDMAStatus = 0x08,
73 TFDListPtr0 = 0x10,
74 TFDListPtr1 = 0x14,
75 TxDMABurstThresh = 0x18,
76 TxDMAUrgentThresh = 0x19,
77 TxDMAPollPeriod = 0x1a,
78 RFDListPtr0 = 0x1c,
79 RFDListPtr1 = 0x20,
80 RxDMABurstThresh = 0x24,
81 RxDMAUrgentThresh = 0x25,
82 RxDMAPollPeriod = 0x26,
83 RxDMAIntCtrl = 0x28,
84 DebugCtrl = 0x2c,
85 ASICCtrl = 0x30,
86 FifoCtrl = 0x38,
87 RxEarlyThresh = 0x3a,
88 FlowOffThresh = 0x3c,
89 FlowOnThresh = 0x3e,
90 TxStartThresh = 0x44,
91 EepromData = 0x48,
92 EepromCtrl = 0x4a,
93 ExpromAddr = 0x4c,
94 Exprodata = 0x50,
95 WakeEvent = 0x51,
96 CountDown = 0x54,
97 IntStatusAck = 0x5a,
98 IntEnable = 0x5c,
99 IntStatus = 0x5e,
100 TxStatus = 0x60,
101 MACCtrl = 0x6c,
102 VLANTag = 0x70,
103 PhyCtrl = 0x76,
104 StationAddr0 = 0x78,
105 StationAddr1 = 0x7a,
106 StationAddr2 = 0x7c,
107 VLANId = 0x80,
108 MaxFrameSize = 0x86,
109 ReceiveMode = 0x88,
110 HashTable0 = 0x8c,
111 HashTable1 = 0x90,
112 RmonStatMask = 0x98,
113 StatMask = 0x9c,
114 RxJumboFrames = 0xbc,
115 TCPCheckSumErrors = 0xc0,
116 IPCheckSumErrors = 0xc2,
117 UDPCheckSumErrors = 0xc4,
118 TxJumboFrames = 0xf4,
119 /* Ethernet MIB statistic register offsets */
120 OctetRcvOk = 0xa8,
121 McstOctetRcvOk = 0xac,
122 BcstOctetRcvOk = 0xb0,
123 FramesRcvOk = 0xb4,
124 McstFramesRcvdOk = 0xb8,
125 BcstFramesRcvdOk = 0xbe,
126 MacControlFramesRcvd = 0xc6,
127 FrameTooLongErrors = 0xc8,
128 InRangeLengthErrors = 0xca,
129 FramesCheckSeqErrors = 0xcc,
130 FramesLostRxErrors = 0xce,
131 OctetXmtOk = 0xd0,
132 McstOctetXmtOk = 0xd4,
133 BcstOctetXmtOk = 0xd8,
134 FramesXmtOk = 0xdc,
135 McstFramesXmtdOk = 0xe0,
136 FramesWDeferredXmt = 0xe4,
137 LateCollisions = 0xe8,
138 MultiColFrames = 0xec,
139 SingleColFrames = 0xf0,
140 BcstFramesXmtdOk = 0xf6,
141 CarrierSenseErrors = 0xf8,
142 MacControlFramesXmtd = 0xfa,
143 FramesAbortXSColls = 0xfc,
144 FramesWEXDeferal = 0xfe,
145 /* RMON statistic register offsets */
146 EtherStatsCollisions = 0x100,
147 EtherStatsOctetsTransmit = 0x104,
148 EtherStatsPktsTransmit = 0x108,
149 EtherStatsPkts64OctetTransmit = 0x10c,
150 EtherStats65to127OctetsTransmit = 0x110,
151 EtherStatsPkts128to255OctetsTransmit = 0x114,
152 EtherStatsPkts256to511OctetsTransmit = 0x118,
153 EtherStatsPkts512to1023OctetsTransmit = 0x11c,
154 EtherStatsPkts1024to1518OctetsTransmit = 0x120,
155 EtherStatsCRCAlignErrors = 0x124,
156 EtherStatsUndersizePkts = 0x128,
157 EtherStatsFragments = 0x12c,
158 EtherStatsJabbers = 0x130,
159 EtherStatsOctets = 0x134,
160 EtherStatsPkts = 0x138,
161 EtherStats64Octets = 0x13c,
162 EtherStatsPkts65to127Octets = 0x140,
163 EtherStatsPkts128to255Octets = 0x144,
164 EtherStatsPkts256to511Octets = 0x148,
165 EtherStatsPkts512to1023Octets = 0x14c,
166 EtherStatsPkts1024to1518Octets = 0x150,
167 };
169 /* Bits in the interrupt status/mask registers. */
170 enum IntStatus_bits {
171 InterruptStatus = 0x0001,
172 HostError = 0x0002,
173 MACCtrlFrame = 0x0008,
174 TxComplete = 0x0004,
175 RxComplete = 0x0010,
176 RxEarly = 0x0020,
177 IntRequested = 0x0040,
178 UpdateStats = 0x0080,
179 LinkEvent = 0x0100,
180 TxDMAComplete = 0x0200,
181 RxDMAComplete = 0x0400,
182 RFDListEnd = 0x0800,
183 RxDMAPriority = 0x1000,
184 };
186 /* Bits in the ReceiveMode register. */
187 enum ReceiveMode_bits {
188 ReceiveUnicast = 0x0001,
189 ReceiveMulticast = 0x0002,
190 ReceiveBroadcast = 0x0004,
191 ReceiveAllFrames = 0x0008,
192 ReceiveMulticastHash = 0x0010,
193 ReceiveIPMulticast = 0x0020,
194 ReceiveVLANMatch = 0x0100,
195 ReceiveVLANHash = 0x0200,
196 };
197 /* Bits in MACCtrl. */
198 enum MACCtrl_bits {
199 DuplexSelect = 0x20,
200 TxFlowControlEnable = 0x80,
201 RxFlowControlEnable = 0x0100,
202 RcvFCS = 0x200,
203 AutoVLANtagging = 0x1000,
204 AutoVLANuntagging = 0x2000,
205 StatsEnable = 0x00200000,
206 StatsDisable = 0x00400000,
207 StatsEnabled = 0x00800000,
208 TxEnable = 0x01000000,
209 TxDisable = 0x02000000,
210 TxEnabled = 0x04000000,
211 RxEnable = 0x08000000,
212 RxDisable = 0x10000000,
213 RxEnabled = 0x20000000,
214 };
216 enum ASICCtrl_LoWord_bits {
217 PhyMedia = 0x0080,
218 };
220 enum ASICCtrl_HiWord_bits {
221 GlobalReset = 0x0001,
222 RxReset = 0x0002,
223 TxReset = 0x0004,
224 DMAReset = 0x0008,
225 FIFOReset = 0x0010,
226 NetworkReset = 0x0020,
227 HostReset = 0x0040,
228 ResetBusy = 0x0400,
229 };
231 /* Transmit Frame Control bits */
232 enum TFC_bits {
233 DwordAlign = 0x00000000,
234 WordAlignDisable = 0x00030000,
235 WordAlign = 0x00020000,
236 TCPChecksumEnable = 0x00040000,
237 UDPChecksumEnable = 0x00080000,
238 IPChecksumEnable = 0x00100000,
239 FCSAppendDisable = 0x00200000,
240 TxIndicate = 0x00400000,
241 TxDMAIndicate = 0x00800000,
242 FragCountShift = 24,
243 VLANTagInsert = 0x0000000010000000,
244 TFDDone = 0x80000000,
245 VIDShift = 32,
246 UsePriorityShift = 48,
247 };
249 /* Receive Frames Status bits */
250 enum RFS_bits {
251 RxFIFOOverrun = 0x00010000,
252 RxRuntFrame = 0x00020000,
253 RxAlignmentError = 0x00040000,
254 RxFCSError = 0x00080000,
255 RxOverSizedFrame = 0x00100000,
256 RxLengthError = 0x00200000,
257 VLANDetected = 0x00400000,
258 TCPDetected = 0x00800000,
259 TCPError = 0x01000000,
260 UDPDetected = 0x02000000,
261 UDPError = 0x04000000,
262 IPDetected = 0x08000000,
263 IPError = 0x10000000,
264 FrameStart = 0x20000000,
265 FrameEnd = 0x40000000,
266 RFDDone = 0x80000000,
267 TCIShift = 32,
268 RFS_Errors = 0x003f0000,
269 };
271 #define MII_RESET_TIME_OUT 10000
272 /* MII register */
273 enum _mii_reg {
274 MII_BMCR = 0,
275 MII_BMSR = 1,
276 MII_PHY_ID1 = 2,
277 MII_PHY_ID2 = 3,
278 MII_ANAR = 4,
279 MII_ANLPAR = 5,
280 MII_ANER = 6,
281 MII_ANNPT = 7,
282 MII_ANLPRNP = 8,
283 MII_MSCR = 9,
284 MII_MSSR = 10,
285 MII_ESR = 15,
286 MII_PHY_SCR = 16,
287 };
288 /* PCS register */
289 enum _pcs_reg {
290 PCS_BMCR = 0,
291 PCS_BMSR = 1,
292 PCS_ANAR = 4,
293 PCS_ANLPAR = 5,
294 PCS_ANER = 6,
295 PCS_ANNPT = 7,
296 PCS_ANLPRNP = 8,
297 PCS_ESR = 15,
298 };
300 /* Basic Mode Control Register */
301 typedef union t_MII_BMCR {
302 u16 image;
303 struct {
304 u16 _bit_5_0:6; // bit 5:0
305 u16 speed1000:1; // bit 6
306 u16 col_test_enable:1; // bit 7
307 u16 duplex_mode:1; // bit 8
308 u16 restart_an:1; // bit 9
309 u16 isolate:1; // bit 10
310 u16 power_down:1; // bit 11
311 u16 an_enable:1; // bit 12
312 u16 speed100:1; // bit 13
313 u16 loopback:1; // bit 14
314 u16 reset:1; // bit 15
315 } bits;
316 } BMCR_t, *PBMCR_t;
318 enum _mii_bmcr {
319 MII_BMCR_RESET = 0x8000,
320 MII_BMCR_LOOP_BACK = 0x4000,
321 MII_BMCR_SPEED_LSB = 0x2000,
322 MII_BMCR_AN_ENABLE = 0x1000,
323 MII_BMCR_POWER_DOWN = 0x0800,
324 MII_BMCR_ISOLATE = 0x0400,
325 MII_BMCR_RESTART_AN = 0x0200,
326 MII_BMCR_DUPLEX_MODE = 0x0100,
327 MII_BMCR_COL_TEST = 0x0080,
328 MII_BMCR_SPEED_MSB = 0x0040,
329 MII_BMCR_SPEED_RESERVED = 0x003f,
330 MII_BMCR_SPEED_10 = 0,
331 MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
332 MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
333 };
335 /* Basic Mode Status Register */
336 typedef union t_MII_BMSR {
337 u16 image;
338 struct {
339 u16 ext_capability:1; // bit 0
340 u16 japper_detect:1; // bit 1
341 u16 link_status:1; // bit 2
342 u16 an_ability:1; // bit 3
343 u16 remote_fault:1; // bit 4
344 u16 an_complete:1; // bit 5
345 u16 preamble_supp:1; // bit 6
346 u16 _bit_7:1; // bit 7
347 u16 ext_status:1; // bit 8
348 u16 media_100BT2_HD:1; // bit 9
349 u16 media_100BT2_FD:1; // bit 10
350 u16 media_10BT_HD:1; // bit 11
351 u16 media_10BT_FD:1; // bit 12
352 u16 media_100BX_HD:1; // bit 13
353 u16 media_100BX_FD:1; // bit 14
354 u16 media_100BT4:1; // bit 15
355 } bits;
356 } BMSR_t, *PBMSR_t;
358 enum _mii_bmsr {
359 MII_BMSR_100BT4 = 0x8000,
360 MII_BMSR_100BX_FD = 0x4000,
361 MII_BMSR_100BX_HD = 0x2000,
362 MII_BMSR_10BT_FD = 0x1000,
363 MII_BMSR_10BT_HD = 0x0800,
364 MII_BMSR_100BT2_FD = 0x0400,
365 MII_BMSR_100BT2_HD = 0x0200,
366 MII_BMSR_EXT_STATUS = 0x0100,
367 MII_BMSR_PREAMBLE_SUPP = 0x0040,
368 MII_BMSR_AN_COMPLETE = 0x0020,
369 MII_BMSR_REMOTE_FAULT = 0x0010,
370 MII_BMSR_AN_ABILITY = 0x0008,
371 MII_BMSR_LINK_STATUS = 0x0004,
372 MII_BMSR_JABBER_DETECT = 0x0002,
373 MII_BMSR_EXT_CAP = 0x0001,
374 };
376 /* ANAR */
377 typedef union t_MII_ANAR {
378 u16 image;
379 struct {
380 u16 selector:5; // bit 4:0
381 u16 media_10BT_HD:1; // bit 5
382 u16 media_10BT_FD:1; // bit 6
383 u16 media_100BX_HD:1; // bit 7
384 u16 media_100BX_FD:1; // bit 8
385 u16 media_100BT4:1; // bit 9
386 u16 pause:1; // bit 10
387 u16 asymmetric:1; // bit 11
388 u16 _bit12:1; // bit 12
389 u16 remote_fault:1; // bit 13
390 u16 _bit14:1; // bit 14
391 u16 next_page:1; // bit 15
392 } bits;
393 } ANAR_t, *PANAR_t;
395 enum _mii_anar {
396 MII_ANAR_NEXT_PAGE = 0x8000,
397 MII_ANAR_REMOTE_FAULT = 0x4000,
398 MII_ANAR_ASYMMETRIC = 0x0800,
399 MII_ANAR_PAUSE = 0x0400,
400 MII_ANAR_100BT4 = 0x0200,
401 MII_ANAR_100BX_FD = 0x0100,
402 MII_ANAR_100BX_HD = 0x0080,
403 MII_ANAR_10BT_FD = 0x0020,
404 MII_ANAR_10BT_HD = 0x0010,
405 MII_ANAR_SELECTOR = 0x001f,
406 MII_IEEE8023_CSMACD = 0x0001,
407 };
409 /* ANLPAR */
410 typedef union t_MII_ANLPAR {
411 u16 image;
412 struct {
413 u16 selector:5; // bit 4:0
414 u16 media_10BT_HD:1; // bit 5
415 u16 media_10BT_FD:1; // bit 6
416 u16 media_100BX_HD:1; // bit 7
417 u16 media_100BX_FD:1; // bit 8
418 u16 media_100BT4:1; // bit 9
419 u16 pause:1; // bit 10
420 u16 asymmetric:1; // bit 11
421 u16 _bit12:1; // bit 12
422 u16 remote_fault:1; // bit 13
423 u16 _bit14:1; // bit 14
424 u16 next_page:1; // bit 15
425 } bits;
426 } ANLPAR_t, *PANLPAR_t;
428 enum _mii_anlpar {
429 MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
430 MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
431 MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
432 MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
433 MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
434 MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
435 MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
436 MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
437 MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
438 MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
439 };
441 /* Auto-Negotiation Expansion Register */
442 typedef union t_MII_ANER {
443 u16 image;
444 struct {
445 u16 lp_negotiable:1; // bit 0
446 u16 page_received:1; // bit 1
447 u16 nextpagable:1; // bit 2
448 u16 lp_nextpagable:1; // bit 3
449 u16 pdetect_fault:1; // bit 4
450 u16 _bit15_5:11; // bit 15:5
451 } bits;
452 } ANER_t, *PANER_t;
454 enum _mii_aner {
455 MII_ANER_PAR_DETECT_FAULT = 0x0010,
456 MII_ANER_LP_NEXTPAGABLE = 0x0008,
457 MII_ANER_NETXTPAGABLE = 0x0004,
458 MII_ANER_PAGE_RECEIVED = 0x0002,
459 MII_ANER_LP_NEGOTIABLE = 0x0001,
460 };
462 /* MASTER-SLAVE Control Register */
463 typedef union t_MII_MSCR {
464 u16 image;
465 struct {
466 u16 _bit_7_0:8; // bit 7:0
467 u16 media_1000BT_HD:1; // bit 8
468 u16 media_1000BT_FD:1; // bit 9
469 u16 port_type:1; // bit 10
470 u16 cfg_value:1; // bit 11
471 u16 cfg_enable:1; // bit 12
472 u16 test_mode:3; // bit 15:13
473 } bits;
474 } MSCR_t, *PMSCR_t;
476 enum _mii_mscr {
477 MII_MSCR_TEST_MODE = 0xe000,
478 MII_MSCR_CFG_ENABLE = 0x1000,
479 MII_MSCR_CFG_VALUE = 0x0800,
480 MII_MSCR_PORT_VALUE = 0x0400,
481 MII_MSCR_1000BT_FD = 0x0200,
482 MII_MSCR_1000BT_HD = 0X0100,
483 };
485 /* MASTER-SLAVE Status Register */
486 typedef union t_MII_MSSR {
487 u16 image;
488 struct {
489 u16 idle_err_count:8; // bit 7:0
490 u16 _bit_9_8:2; // bit 9:8
491 u16 lp_1000BT_HD:1; // bit 10
492 u16 lp_1000BT_FD:1; // bit 11
493 u16 remote_rcv_status:1; // bit 12
494 u16 local_rcv_status:1; // bit 13
495 u16 cfg_resolution:1; // bit 14
496 u16 cfg_fault:1; // bit 15
497 } bits;
498 } MSSR_t, *PMSSR_t;
500 enum _mii_mssr {
501 MII_MSSR_CFG_FAULT = 0x8000,
502 MII_MSSR_CFG_RES = 0x4000,
503 MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
504 MII_MSSR_REMOTE_RCVR = 0x1000,
505 MII_MSSR_LP_1000BT_HD = 0x0800,
506 MII_MSSR_LP_1000BT_FD = 0x0400,
507 MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
508 };
510 /* IEEE Extened Status Register */
511 typedef union t_MII_ESR {
512 u16 image;
513 struct {
514 u16 _bit_11_0:12; // bit 11:0
515 u16 media_1000BT_HD:2; // bit 12
516 u16 media_1000BT_FD:1; // bit 13
517 u16 media_1000BX_HD:1; // bit 14
518 u16 media_1000BX_FD:1; // bit 15
519 } bits;
520 } ESR_t, *PESR_t;
522 enum _mii_esr {
523 MII_ESR_1000BX_FD = 0x8000,
524 MII_ESR_1000BX_HD = 0x4000,
525 MII_ESR_1000BT_FD = 0x2000,
526 MII_ESR_1000BT_HD = 0x1000,
527 };
528 /* PHY Specific Control Register */
529 typedef union t_MII_PHY_SCR {
530 u16 image;
531 struct {
532 u16 disable_jabber:1; // bit 0
533 u16 polarity_reversal:1; // bit 1
534 u16 SEQ_test:1; // bit 2
535 u16 _bit_3:1; // bit 3
536 u16 disable_CLK125:1; // bit 4
537 u16 mdi_crossover_mode:2; // bit 6:5
538 u16 enable_ext_dist:1; // bit 7
539 u16 _bit_8_9:2; // bit 9:8
540 u16 force_link:1; // bit 10
541 u16 assert_CRS:1; // bit 11
542 u16 rcv_fifo_depth:2; // bit 13:12
543 u16 xmit_fifo_depth:2; // bit 15:14
544 } bits;
545 } PHY_SCR_t, *PPHY_SCR_t;
547 typedef enum t_MII_ADMIN_STATUS {
548 adm_reset,
549 adm_operational,
550 adm_loopback,
551 adm_power_down,
552 adm_isolate
553 } MII_ADMIN_t, *PMII_ADMIN_t;
555 /* Physical Coding Sublayer Management (PCS) */
556 /* PCS control and status registers bitmap as the same as MII */
557 /* PCS Extended Status register bitmap as the same as MII */
558 /* PCS ANAR */
559 typedef union t_PCS_ANAR {
560 u16 image;
561 struct {
562 u16 _bit_4_0:5; // bit 4:0
563 u16 full_duplex:1; // bit 5
564 u16 half_duplex:1; // bit 6
565 u16 asymmetric:1; // bit 7
566 u16 pause:1; // bit 8
567 u16 _bit_11_9:3; // bit 11:9
568 u16 remote_fault:2; // bit 13:12
569 u16 _bit_14:1; // bit 14
570 u16 next_page:1; // bit 15
571 } bits;
572 } ANAR_PCS_t, *PANAR_PCS_t;
574 enum _pcs_anar {
575 PCS_ANAR_NEXT_PAGE = 0x8000,
576 PCS_ANAR_REMOTE_FAULT = 0x3000,
577 PCS_ANAR_ASYMMETRIC = 0x0100,
578 PCS_ANAR_PAUSE = 0x0080,
579 PCS_ANAR_HALF_DUPLEX = 0x0040,
580 PCS_ANAR_FULL_DUPLEX = 0x0020,
581 };
582 /* PCS ANLPAR */
583 typedef union t_PCS_ANLPAR {
584 u16 image;
585 struct {
586 u16 _bit_4_0:5; // bit 4:0
587 u16 full_duplex:1; // bit 5
588 u16 half_duplex:1; // bit 6
589 u16 asymmetric:1; // bit 7
590 u16 pause:1; // bit 8
591 u16 _bit_11_9:3; // bit 11:9
592 u16 remote_fault:2; // bit 13:12
593 u16 _bit_14:1; // bit 14
594 u16 next_page:1; // bit 15
595 } bits;
596 } ANLPAR_PCS_t, *PANLPAR_PCS_t;
598 enum _pcs_anlpar {
599 PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
600 PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
601 PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
602 PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
603 PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
604 PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
605 };
607 typedef struct t_SROM {
608 u16 config_param; /* 0x00 */
609 u16 asic_ctrl; /* 0x02 */
610 u16 sub_vendor_id; /* 0x04 */
611 u16 sub_system_id; /* 0x06 */
612 u16 reserved1[12]; /* 0x08-0x1f */
613 u8 mac_addr[6]; /* 0x20-0x25 */
614 u8 reserved2[10]; /* 0x26-0x2f */
615 u8 sib[204]; /* 0x30-0xfb */
616 u32 crc; /* 0xfc-0xff */
617 } SROM_t, *PSROM_t;
619 /* Ioctl custom data */
620 struct ioctl_data {
621 char signature[10];
622 int cmd;
623 int len;
624 char *data;
625 };
627 struct mii_data {
628 __u16 reserved;
629 __u16 reg_num;
630 __u16 in_value;
631 __u16 out_value;
632 };
634 /* The Rx and Tx buffer descriptors. */
635 struct netdev_desc {
636 u64 next_desc;
637 u64 status;
638 u64 fraginfo;
639 };
641 #define PRIV_ALIGN 15 /* Required alignment mask */
642 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
643 within the structure. */
644 struct netdev_private {
645 /* Descriptor rings first for alignment. */
646 struct netdev_desc *rx_ring;
647 struct netdev_desc *tx_ring;
648 struct sk_buff *rx_skbuff[RX_RING_SIZE];
649 struct sk_buff *tx_skbuff[TX_RING_SIZE];
650 dma_addr_t tx_ring_dma;
651 dma_addr_t rx_ring_dma;
652 struct pci_dev *pdev;
653 spinlock_t tx_lock;
654 spinlock_t rx_lock;
655 struct net_device_stats stats;
656 unsigned int rx_buf_sz; /* Based on MTU+slack. */
657 unsigned int speed; /* Operating speed */
658 unsigned int vlan; /* VLAN Id */
659 unsigned int chip_id; /* PCI table chip id */
660 unsigned int rx_coalesce; /* Maximum frames each RxDMAComplete intr */
661 unsigned int rx_timeout; /* Wait time between RxDMAComplete intr */
662 unsigned int tx_coalesce; /* Maximum frames each tx interrupt */
663 unsigned int full_duplex:1; /* Full-duplex operation requested. */
664 unsigned int an_enable:2; /* Auto-Negotiated Enable */
665 unsigned int jumbo:1; /* Jumbo frame enable */
666 unsigned int coalesce:1; /* Rx coalescing enable */
667 unsigned int tx_flow:1; /* Tx flow control enable */
668 unsigned int rx_flow:1; /* Rx flow control enable */
669 unsigned int phy_media:1; /* 1: fiber, 0: copper */
670 unsigned int link_status:1; /* Current link status */
671 unsigned char pci_rev_id; /* PCI revision ID */
672 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
673 unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
674 unsigned long cur_tx, old_tx;
675 struct timer_list timer;
676 int wake_polarity;
677 char name[256]; /* net device description */
678 u8 duplex_polarity;
679 u16 mcast_filter[4];
680 u16 advertising; /* NWay media advertisement */
681 u16 negotiate; /* Negotiated media */
682 int phy_addr; /* PHY addresses. */
683 };
685 /* The station address location in the EEPROM. */
686 /* The struct pci_device_id consist of:
687 vendor, device Vendor and device ID to match (or PCI_ANY_ID)
688 subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID)
689 class Device class to match. The class_mask tells which bits
690 class_mask of the class are honored during the comparison.
691 driver_data Data private to the driver.
692 */
694 static const struct pci_device_id rio_pci_tbl[] = {
695 {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
696 { }
697 };
698 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
699 #define TX_TIMEOUT (4*HZ)
700 #define PACKET_SIZE 1536
701 #define MAX_JUMBO 8000
702 #define RIO_IO_SIZE 340
703 #define DEFAULT_RXC 5
704 #define DEFAULT_RXT 750
705 #define DEFAULT_TXC 1
706 #define MAX_TXC 8
707 #endif /* __DL2K_H__ */