ia64/linux-2.6.18-xen.hg

view drivers/net/dgrs_es4h.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /************************************************************************/
2 /* */
3 /* es4h.h: Hardware definition of the ES/4h Ethernet Switch, from */
4 /* both the host and the 3051's point of view. */
5 /* NOTE: this name is a misnomer now that there is a PCI */
6 /* board. Everything that says "es4h" should really be */
7 /* "se4". But we'll keep the old name for now. */
8 /* */
9 /* $Id: es4h.h,v 1.10 1996/08/22 17:16:53 rick Exp $ */
10 /* */
11 /************************************************************************/
13 /************************************************************************/
14 /* */
15 /* EISA I/O Registers. These are located at 0x1000 * slot-number */
16 /* plus the indicated address. I.E. 0x4000-0x4009 for slot 4. */
17 /* */
18 /************************************************************************/
20 #define ES4H_MANUFmsb 0x00 /* Read-only */
21 #define ES4H_MANUFlsb 0x01 /* Read-only */
22 # define ES4H_MANUF_CODE 0x1049 /* = "DBI" */
24 #define ES4H_PRODUCT 0x02 /* Read-only */
25 # define ES4H_PRODUCT_CODE 0x0A
26 # define EPC_PRODUCT_CODE 0x03
28 #define ES4H_REVISION 0x03 /* Read-only */
29 # define ES4H_REVISION_CODE 0x01
31 #define ES4H_EC 0x04 /* EISA Control */
32 # define ES4H_EC_RESET 0x04 /* WO, EISA reset */
33 # define ES4H_EC_ENABLE 0x01 /* RW, EISA enable - set to */
34 /* 1 before memory enable */
35 #define ES4H_PC 0x05 /* Processor Control */
36 # define ES4H_PC_RESET 0x04 /* RW, 3051 reset */
37 # define ES4H_PC_INT 0x08 /* WO, assert 3051 intr. 3 */
39 #define ES4H_MW 0x06 /* Memory Window select and enable */
40 # define ES4H_MW_ENABLE 0x80 /* WO, enable memory */
41 # define ES4H_MW_SELECT_MASK 0x1f /* WO, 32k window selected */
43 #define ES4H_IS 0x07 /* Interrupt, addr select */
44 # define ES4H_IS_INTMASK 0x07 /* WO, interrupt select */
45 # define ES4H_IS_INTOFF 0x00 /* No IRQ */
46 # define ES4H_IS_INT3 0x03 /* IRQ 3 */
47 # define ES4H_IS_INT5 0x02 /* IRQ 5 */
48 # define ES4H_IS_INT7 0x01 /* IRQ 7 */
49 # define ES4H_IS_INT10 0x04 /* IRQ 10 */
50 # define ES4H_IS_INT11 0x05 /* IRQ 11 */
51 # define ES4H_IS_INT12 0x06 /* IRQ 12 */
52 # define ES4H_IS_INT15 0x07 /* IRQ 15 */
53 # define ES4H_IS_INTACK 0x10 /* WO, interrupt ack */
54 # define ES4H_IS_INTPEND 0x10 /* RO, interrupt pending */
55 # define ES4H_IS_LINEAR 0x40 /* WO, no memory windowing */
56 # define ES4H_IS_AS15 0x80 /* RW, address select bit 15 */
58 #define ES4H_AS_23_16 0x08 /* Address select bits 23-16 */
59 #define ES4H_AS_31_24 0x09 /* Address select bits 31-24 */
61 #define ES4H_IO_MAX 0x09 /* Size of I/O space */
63 /*
64 * PCI
65 */
66 #define SE6_RESET PLX_USEROUT
68 /************************************************************************/
69 /* */
70 /* 3051 Memory Map */
71 /* */
72 /* Note: 3051 has 4K I-cache, 2K D-cache. 1 cycle is 50 nsec. */
73 /* */
74 /************************************************************************/
75 #define SE4_NPORTS 4 /* # of ethernet ports */
76 #define SE6_NPORTS 6 /* # of ethernet ports */
77 #define SE_NPORTS 6 /* Max # of ethernet ports */
79 #define ES4H_RAM_BASE 0x83000000 /* Base address of RAM */
80 #define ES4H_RAM_SIZE 0x00200000 /* Size of RAM (2MB) */
81 #define ES4H_RAM_INTBASE 0x83800000 /* Base of int-on-write RAM */
82 /* a.k.a. PKT RAM */
84 /* Ethernet controllers */
85 /* See: i82596.h */
86 #define ES4H_ETHER0_PORT 0xA2000000
87 #define ES4H_ETHER0_CMD 0xA2000100
88 #define ES4H_ETHER1_PORT 0xA2000200
89 #define ES4H_ETHER1_CMD 0xA2000300
90 #define ES4H_ETHER2_PORT 0xA2000400
91 #define ES4H_ETHER2_CMD 0xA2000500
92 #define ES4H_ETHER3_PORT 0xA2000600
93 #define ES4H_ETHER3_CMD 0xA2000700
94 #define ES4H_ETHER4_PORT 0xA2000800 /* RS SE-6 only */
95 #define ES4H_ETHER4_CMD 0xA2000900 /* RS SE-6 only */
96 #define ES4H_ETHER5_PORT 0xA2000A00 /* RS SE-6 only */
97 #define ES4H_ETHER5_CMD 0xA2000B00 /* RS SE-6 only */
99 #define ES4H_I8254 0xA2040000 /* 82C54 timers */
100 /* See: i8254.h */
102 #define SE4_I8254_HZ (23000000/4) /* EISA clock input freq. */
103 #define SE4_IDT_HZ (46000000) /* EISA CPU freq. */
104 #define SE6_I8254_HZ (20000000/4) /* PCI clock input freq. */
105 #define SE6_IDT_HZ (50000000) /* PCI CPU freq. */
106 #define ES4H_I8254_HZ (23000000/4) /* EISA clock input freq. */
108 #define ES4H_GPP 0xA2050000 /* General purpose port */
109 /*
110 * SE-4 (EISA) GPP bits
111 */
112 # define ES4H_GPP_C0_100 0x0001 /* WO, Chan 0: 100 ohm TP */
113 # define ES4H_GPP_C0_SQE 0x0002 /* WO, Chan 0: normal squelch */
114 # define ES4H_GPP_C1_100 0x0004 /* WO, Chan 1: 100 ohm TP */
115 # define ES4H_GPP_C1_SQE 0x0008 /* WO, Chan 1: normal squelch */
116 # define ES4H_GPP_C2_100 0x0010 /* WO, Chan 2: 100 ohm TP */
117 # define ES4H_GPP_C2_SQE 0x0020 /* WO, Chan 2: normal squelch */
118 # define ES4H_GPP_C3_100 0x0040 /* WO, Chan 3: 100 ohm TP */
119 # define ES4H_GPP_C3_SQE 0x0080 /* WO, Chan 3: normal squelch */
120 # define ES4H_GPP_SQE 0x00AA /* WO, All: normal squelch */
121 # define ES4H_GPP_100 0x0055 /* WO, All: 100 ohm TP */
122 # define ES4H_GPP_HOSTINT 0x0100 /* RO, cause intr. to host */
123 /* Hold high > 250 nsec */
124 # define SE4_GPP_EED 0x0200 /* RW, EEPROM data bit */
125 # define SE4_GPP_EECS 0x0400 /* RW, EEPROM chip select */
126 # define SE4_GPP_EECK 0x0800 /* RW, EEPROM clock */
128 /*
129 * SE-6 (PCI) GPP bits
130 */
131 # define SE6_GPP_EED 0x0001 /* RW, EEPROM data bit */
132 # define SE6_GPP_EECS 0x0002 /* RW, EEPROM chip select */
133 # define SE6_GPP_EECK 0x0004 /* RW, EEPROM clock */
134 # define SE6_GPP_LINK 0x00fc /* R, Link status LEDs */
136 #define ES4H_INTVEC 0xA2060000 /* RO: Interrupt Vector */
137 # define ES4H_IV_DMA0 0x01 /* Chan 0 DMA interrupt */
138 # define ES4H_IV_PKT0 0x02 /* Chan 0 PKT interrupt */
139 # define ES4H_IV_DMA1 0x04 /* Chan 1 DMA interrupt */
140 # define ES4H_IV_PKT1 0x08 /* Chan 1 PKT interrupt */
141 # define ES4H_IV_DMA2 0x10 /* Chan 2 DMA interrupt */
142 # define ES4H_IV_PKT2 0x20 /* Chan 2 PKT interrupt */
143 # define ES4H_IV_DMA3 0x40 /* Chan 3 DMA interrupt */
144 # define ES4H_IV_PKT3 0x80 /* Chan 3 PKT interrupt */
146 #define ES4H_INTACK 0xA2060000 /* WO: Interrupt Ack */
147 # define ES4H_INTACK_8254 0x01 /* Real Time Clock (int 0) */
148 # define ES4H_INTACK_HOST 0x02 /* Host (int 1) */
149 # define ES4H_INTACK_PKT0 0x04 /* Chan 0 Pkt (int 2) */
150 # define ES4H_INTACK_PKT1 0x08 /* Chan 1 Pkt (int 3) */
151 # define ES4H_INTACK_PKT2 0x10 /* Chan 2 Pkt (int 4) */
152 # define ES4H_INTACK_PKT3 0x20 /* Chan 3 Pkt (int 5) */
154 #define SE6_PLX 0xA2070000 /* PLX 9060, SE-6 (PCI) only */
155 /* see plx9060.h */
157 #define SE6_PCI_VENDOR_ID 0x114F /* Digi PCI vendor ID */
158 #define SE6_PCI_DEVICE_ID 0x0003 /* RS SE-6 device ID */
159 #define SE6_PCI_ID ((SE6_PCI_DEVICE_ID<<16) | SE6_PCI_VENDOR_ID)
161 /*
162 * IDT Interrupts
163 */
164 #define ES4H_INT_8254 IDT_INT0
165 #define ES4H_INT_HOST IDT_INT1
166 #define ES4H_INT_ETHER0 IDT_INT2
167 #define ES4H_INT_ETHER1 IDT_INT3
168 #define ES4H_INT_ETHER2 IDT_INT4
169 #define ES4H_INT_ETHER3 IDT_INT5
171 /*
172 * Because there are differences between the SE-4 and the SE-6,
173 * we assume that the following globals will be set up at init
174 * time in main.c to containt the appropriate constants from above
175 */
176 extern ushort Gpp; /* Softcopy of GPP register */
177 extern ushort EEck; /* Clock bit */
178 extern ushort EEcs; /* CS bit */
179 extern ushort EEd; /* Data bit */
180 extern ulong I8254_Hz; /* i8254 input frequency */
181 extern ulong IDT_Hz; /* IDT CPU frequency */
182 extern int Nports; /* Number of ethernet controllers */
183 extern int Nchan; /* Nports+1 */