ia64/linux-2.6.18-xen.hg

view drivers/net/declance.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Lance ethernet driver for the MIPS processor based
3 * DECstation family
4 *
5 *
6 * adopted from sunlance.c by Richard van den Berg
7 *
8 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
9 *
10 * additional sources:
11 * - PMAD-AA TURBOchannel Ethernet Module Functional Specification,
12 * Revision 1.2
13 *
14 * History:
15 *
16 * v0.001: The kernel accepts the code and it shows the hardware address.
17 *
18 * v0.002: Removed most sparc stuff, left only some module and dma stuff.
19 *
20 * v0.003: Enhanced base address calculation from proposals by
21 * Harald Koerfgen and Thomas Riemer.
22 *
23 * v0.004: lance-regs is pointing at the right addresses, added prom
24 * check. First start of address mapping and DMA.
25 *
26 * v0.005: started to play around with LANCE-DMA. This driver will not
27 * work for non IOASIC lances. HK
28 *
29 * v0.006: added pointer arrays to lance_private and setup routine for
30 * them in dec_lance_init. HK
31 *
32 * v0.007: Big shit. The LANCE seems to use a different DMA mechanism to
33 * access the init block. This looks like one (short) word at a
34 * time, but the smallest amount the IOASIC can transfer is a
35 * (long) word. So we have a 2-2 padding here. Changed
36 * lance_init_block accordingly. The 16-16 padding for the buffers
37 * seems to be correct. HK
38 *
39 * v0.008: mods to make PMAX_LANCE work. 01/09/1999 triemer
40 *
41 * v0.009: Module support fixes, multiple interfaces support, various
42 * bits. macro
43 */
45 #include <linux/crc32.h>
46 #include <linux/delay.h>
47 #include <linux/errno.h>
48 #include <linux/if_ether.h>
49 #include <linux/init.h>
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/spinlock.h>
55 #include <linux/stddef.h>
56 #include <linux/string.h>
58 #include <asm/addrspace.h>
59 #include <asm/system.h>
61 #include <asm/dec/interrupts.h>
62 #include <asm/dec/ioasic.h>
63 #include <asm/dec/ioasic_addrs.h>
64 #include <asm/dec/kn01.h>
65 #include <asm/dec/machtype.h>
66 #include <asm/dec/system.h>
67 #include <asm/dec/tc.h>
69 static char version[] __devinitdata =
70 "declance.c: v0.009 by Linux MIPS DECstation task force\n";
72 MODULE_AUTHOR("Linux MIPS DECstation task force");
73 MODULE_DESCRIPTION("DEC LANCE (DECstation onboard, PMAD-xx) driver");
74 MODULE_LICENSE("GPL");
76 /*
77 * card types
78 */
79 #define ASIC_LANCE 1
80 #define PMAD_LANCE 2
81 #define PMAX_LANCE 3
84 #define LE_CSR0 0
85 #define LE_CSR1 1
86 #define LE_CSR2 2
87 #define LE_CSR3 3
89 #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
91 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
92 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
93 #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
94 #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
95 #define LE_C0_MERR 0x0800 /* ME: Memory error */
96 #define LE_C0_RINT 0x0400 /* Received interrupt */
97 #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
98 #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
99 #define LE_C0_INTR 0x0080 /* Interrupt or error */
100 #define LE_C0_INEA 0x0040 /* Interrupt enable */
101 #define LE_C0_RXON 0x0020 /* Receiver on */
102 #define LE_C0_TXON 0x0010 /* Transmitter on */
103 #define LE_C0_TDMD 0x0008 /* Transmitter demand */
104 #define LE_C0_STOP 0x0004 /* Stop the card */
105 #define LE_C0_STRT 0x0002 /* Start the card */
106 #define LE_C0_INIT 0x0001 /* Init the card */
108 #define LE_C3_BSWP 0x4 /* SWAP */
109 #define LE_C3_ACON 0x2 /* ALE Control */
110 #define LE_C3_BCON 0x1 /* Byte control */
112 /* Receive message descriptor 1 */
113 #define LE_R1_OWN 0x80 /* Who owns the entry */
114 #define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
115 #define LE_R1_FRA 0x20 /* FRA: Frame error */
116 #define LE_R1_OFL 0x10 /* OFL: Frame overflow */
117 #define LE_R1_CRC 0x08 /* CRC error */
118 #define LE_R1_BUF 0x04 /* BUF: Buffer error */
119 #define LE_R1_SOP 0x02 /* Start of packet */
120 #define LE_R1_EOP 0x01 /* End of packet */
121 #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
123 #define LE_T1_OWN 0x80 /* Lance owns the packet */
124 #define LE_T1_ERR 0x40 /* Error summary */
125 #define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
126 #define LE_T1_EONE 0x08 /* Error: one retry needed */
127 #define LE_T1_EDEF 0x04 /* Error: deferred */
128 #define LE_T1_SOP 0x02 /* Start of packet */
129 #define LE_T1_EOP 0x01 /* End of packet */
130 #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
132 #define LE_T3_BUF 0x8000 /* Buffer error */
133 #define LE_T3_UFL 0x4000 /* Error underflow */
134 #define LE_T3_LCOL 0x1000 /* Error late collision */
135 #define LE_T3_CLOS 0x0800 /* Error carrier loss */
136 #define LE_T3_RTY 0x0400 /* Error retry */
137 #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
139 /* Define: 2^4 Tx buffers and 2^4 Rx buffers */
141 #ifndef LANCE_LOG_TX_BUFFERS
142 #define LANCE_LOG_TX_BUFFERS 4
143 #define LANCE_LOG_RX_BUFFERS 4
144 #endif
146 #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
147 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
149 #define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
150 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
152 #define PKT_BUF_SZ 1536
153 #define RX_BUFF_SIZE PKT_BUF_SZ
154 #define TX_BUFF_SIZE PKT_BUF_SZ
156 #undef TEST_HITS
157 #define ZERO 0
159 /* The DS2000/3000 have a linear 64 KB buffer.
161 * The PMAD-AA has 128 kb buffer on-board.
162 *
163 * The IOASIC LANCE devices use a shared memory region. This region as seen
164 * from the CPU is (max) 128 KB long and has to be on an 128 KB boundary.
165 * The LANCE sees this as a 64 KB long continuous memory region.
166 *
167 * The LANCE's DMA address is used as an index in this buffer and DMA takes
168 * place in bursts of eight 16-Bit words which are packed into four 32-Bit words
169 * by the IOASIC. This leads to a strange padding: 16 bytes of valid data followed
170 * by a 16 byte gap :-(.
171 */
173 struct lance_rx_desc {
174 unsigned short rmd0; /* low address of packet */
175 short gap0;
176 unsigned char rmd1_hadr; /* high address of packet */
177 unsigned char rmd1_bits; /* descriptor bits */
178 short gap1;
179 short length; /* 2s complement (negative!)
180 of buffer length */
181 short gap2;
182 unsigned short mblength; /* actual number of bytes received */
183 short gap3;
184 };
186 struct lance_tx_desc {
187 unsigned short tmd0; /* low address of packet */
188 short gap0;
189 unsigned char tmd1_hadr; /* high address of packet */
190 unsigned char tmd1_bits; /* descriptor bits */
191 short gap1;
192 short length; /* 2s complement (negative!)
193 of buffer length */
194 short gap2;
195 unsigned short misc;
196 short gap3;
197 };
200 /* First part of the LANCE initialization block, described in databook. */
201 struct lance_init_block {
202 unsigned short mode; /* pre-set mode (reg. 15) */
203 short gap0;
205 unsigned char phys_addr[12]; /* physical ethernet address
206 only 0, 1, 4, 5, 8, 9 are valid
207 2, 3, 6, 7, 10, 11 are gaps */
208 unsigned short filter[8]; /* multicast filter
209 only 0, 2, 4, 6 are valid
210 1, 3, 5, 7 are gaps */
212 /* Receive and transmit ring base, along with extra bits. */
213 unsigned short rx_ptr; /* receive descriptor addr */
214 short gap1;
215 unsigned short rx_len; /* receive len and high addr */
216 short gap2;
217 unsigned short tx_ptr; /* transmit descriptor addr */
218 short gap3;
219 unsigned short tx_len; /* transmit len and high addr */
220 short gap4;
221 short gap5[8];
223 /* The buffer descriptors */
224 struct lance_rx_desc brx_ring[RX_RING_SIZE];
225 struct lance_tx_desc btx_ring[TX_RING_SIZE];
226 };
228 #define BUF_OFFSET_CPU sizeof(struct lance_init_block)
229 #define BUF_OFFSET_LNC (sizeof(struct lance_init_block)>>1)
231 #define libdesc_offset(rt, elem) \
232 ((__u32)(((unsigned long)(&(((struct lance_init_block *)0)->rt[elem])))))
234 /*
235 * This works *only* for the ring descriptors
236 */
237 #define LANCE_ADDR(x) (CPHYSADDR(x) >> 1)
239 struct lance_private {
240 struct net_device *next;
241 int type;
242 int slot;
243 int dma_irq;
244 volatile struct lance_regs *ll;
245 volatile struct lance_init_block *init_block;
247 spinlock_t lock;
249 int rx_new, tx_new;
250 int rx_old, tx_old;
252 struct net_device_stats stats;
254 unsigned short busmaster_regval;
256 struct timer_list multicast_timer;
258 /* Pointers to the ring buffers as seen from the CPU */
259 char *rx_buf_ptr_cpu[RX_RING_SIZE];
260 char *tx_buf_ptr_cpu[TX_RING_SIZE];
262 /* Pointers to the ring buffers as seen from the LANCE */
263 char *rx_buf_ptr_lnc[RX_RING_SIZE];
264 char *tx_buf_ptr_lnc[TX_RING_SIZE];
265 };
267 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
268 lp->tx_old+TX_RING_MOD_MASK-lp->tx_new:\
269 lp->tx_old - lp->tx_new-1)
271 /* The lance control ports are at an absolute address, machine and tc-slot
272 * dependent.
273 * DECstations do only 32-bit access and the LANCE uses 16 bit addresses,
274 * so we have to give the structure an extra member making rap pointing
275 * at the right address
276 */
277 struct lance_regs {
278 volatile unsigned short rdp; /* register data port */
279 unsigned short pad;
280 volatile unsigned short rap; /* register address port */
281 };
283 int dec_lance_debug = 2;
285 static struct net_device *root_lance_dev;
287 static inline void writereg(volatile unsigned short *regptr, short value)
288 {
289 *regptr = value;
290 iob();
291 }
293 /* Load the CSR registers */
294 static void load_csrs(struct lance_private *lp)
295 {
296 volatile struct lance_regs *ll = lp->ll;
297 int leptr;
299 /* The address space as seen from the LANCE
300 * begins at address 0. HK
301 */
302 leptr = 0;
304 writereg(&ll->rap, LE_CSR1);
305 writereg(&ll->rdp, (leptr & 0xFFFF));
306 writereg(&ll->rap, LE_CSR2);
307 writereg(&ll->rdp, leptr >> 16);
308 writereg(&ll->rap, LE_CSR3);
309 writereg(&ll->rdp, lp->busmaster_regval);
311 /* Point back to csr0 */
312 writereg(&ll->rap, LE_CSR0);
313 }
315 /*
316 * Our specialized copy routines
317 *
318 */
319 void cp_to_buf(const int type, void *to, const void *from, int len)
320 {
321 unsigned short *tp, *fp, clen;
322 unsigned char *rtp, *rfp;
324 if (type == PMAX_LANCE) {
325 clen = len >> 1;
326 tp = (unsigned short *) to;
327 fp = (unsigned short *) from;
329 while (clen--) {
330 *tp++ = *fp++;
331 tp++;
332 }
334 clen = len & 1;
335 rtp = (unsigned char *) tp;
336 rfp = (unsigned char *) fp;
337 while (clen--) {
338 *rtp++ = *rfp++;
339 }
340 } else {
341 /*
342 * copy 16 Byte chunks
343 */
344 clen = len >> 4;
345 tp = (unsigned short *) to;
346 fp = (unsigned short *) from;
347 while (clen--) {
348 *tp++ = *fp++;
349 *tp++ = *fp++;
350 *tp++ = *fp++;
351 *tp++ = *fp++;
352 *tp++ = *fp++;
353 *tp++ = *fp++;
354 *tp++ = *fp++;
355 *tp++ = *fp++;
356 tp += 8;
357 }
359 /*
360 * do the rest, if any.
361 */
362 clen = len & 15;
363 rtp = (unsigned char *) tp;
364 rfp = (unsigned char *) fp;
365 while (clen--) {
366 *rtp++ = *rfp++;
367 }
368 }
370 iob();
371 }
373 void cp_from_buf(const int type, void *to, const void *from, int len)
374 {
375 unsigned short *tp, *fp, clen;
376 unsigned char *rtp, *rfp;
378 if (type == PMAX_LANCE) {
379 clen = len >> 1;
380 tp = (unsigned short *) to;
381 fp = (unsigned short *) from;
382 while (clen--) {
383 *tp++ = *fp++;
384 fp++;
385 }
387 clen = len & 1;
389 rtp = (unsigned char *) tp;
390 rfp = (unsigned char *) fp;
392 while (clen--) {
393 *rtp++ = *rfp++;
394 }
395 } else {
397 /*
398 * copy 16 Byte chunks
399 */
400 clen = len >> 4;
401 tp = (unsigned short *) to;
402 fp = (unsigned short *) from;
403 while (clen--) {
404 *tp++ = *fp++;
405 *tp++ = *fp++;
406 *tp++ = *fp++;
407 *tp++ = *fp++;
408 *tp++ = *fp++;
409 *tp++ = *fp++;
410 *tp++ = *fp++;
411 *tp++ = *fp++;
412 fp += 8;
413 }
415 /*
416 * do the rest, if any.
417 */
418 clen = len & 15;
419 rtp = (unsigned char *) tp;
420 rfp = (unsigned char *) fp;
421 while (clen--) {
422 *rtp++ = *rfp++;
423 }
426 }
428 }
430 /* Setup the Lance Rx and Tx rings */
431 static void lance_init_ring(struct net_device *dev)
432 {
433 struct lance_private *lp = netdev_priv(dev);
434 volatile struct lance_init_block *ib;
435 int leptr;
436 int i;
438 ib = (struct lance_init_block *) (dev->mem_start);
440 /* Lock out other processes while setting up hardware */
441 netif_stop_queue(dev);
442 lp->rx_new = lp->tx_new = 0;
443 lp->rx_old = lp->tx_old = 0;
445 /* Copy the ethernet address to the lance init block.
446 * XXX bit 0 of the physical address registers has to be zero
447 */
448 ib->phys_addr[0] = dev->dev_addr[0];
449 ib->phys_addr[1] = dev->dev_addr[1];
450 ib->phys_addr[4] = dev->dev_addr[2];
451 ib->phys_addr[5] = dev->dev_addr[3];
452 ib->phys_addr[8] = dev->dev_addr[4];
453 ib->phys_addr[9] = dev->dev_addr[5];
454 /* Setup the initialization block */
456 /* Setup rx descriptor pointer */
457 leptr = LANCE_ADDR(libdesc_offset(brx_ring, 0));
458 ib->rx_len = (LANCE_LOG_RX_BUFFERS << 13) | (leptr >> 16);
459 ib->rx_ptr = leptr;
460 if (ZERO)
461 printk("RX ptr: %8.8x(%8.8x)\n", leptr, libdesc_offset(brx_ring, 0));
463 /* Setup tx descriptor pointer */
464 leptr = LANCE_ADDR(libdesc_offset(btx_ring, 0));
465 ib->tx_len = (LANCE_LOG_TX_BUFFERS << 13) | (leptr >> 16);
466 ib->tx_ptr = leptr;
467 if (ZERO)
468 printk("TX ptr: %8.8x(%8.8x)\n", leptr, libdesc_offset(btx_ring, 0));
470 if (ZERO)
471 printk("TX rings:\n");
473 /* Setup the Tx ring entries */
474 for (i = 0; i < TX_RING_SIZE; i++) {
475 leptr = (int) lp->tx_buf_ptr_lnc[i];
476 ib->btx_ring[i].tmd0 = leptr;
477 ib->btx_ring[i].tmd1_hadr = leptr >> 16;
478 ib->btx_ring[i].tmd1_bits = 0;
479 ib->btx_ring[i].length = 0xf000; /* The ones required by tmd2 */
480 ib->btx_ring[i].misc = 0;
481 if (i < 3 && ZERO)
482 printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->tx_buf_ptr_cpu[i]);
483 }
485 /* Setup the Rx ring entries */
486 if (ZERO)
487 printk("RX rings:\n");
488 for (i = 0; i < RX_RING_SIZE; i++) {
489 leptr = (int) lp->rx_buf_ptr_lnc[i];
490 ib->brx_ring[i].rmd0 = leptr;
491 ib->brx_ring[i].rmd1_hadr = leptr >> 16;
492 ib->brx_ring[i].rmd1_bits = LE_R1_OWN;
493 ib->brx_ring[i].length = -RX_BUFF_SIZE | 0xf000;
494 ib->brx_ring[i].mblength = 0;
495 if (i < 3 && ZERO)
496 printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->rx_buf_ptr_cpu[i]);
497 }
498 iob();
499 }
501 static int init_restart_lance(struct lance_private *lp)
502 {
503 volatile struct lance_regs *ll = lp->ll;
504 int i;
506 writereg(&ll->rap, LE_CSR0);
507 writereg(&ll->rdp, LE_C0_INIT);
509 /* Wait for the lance to complete initialization */
510 for (i = 0; (i < 100) && !(ll->rdp & LE_C0_IDON); i++) {
511 udelay(10);
512 }
513 if ((i == 100) || (ll->rdp & LE_C0_ERR)) {
514 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, ll->rdp);
515 return -1;
516 }
517 if ((ll->rdp & LE_C0_ERR)) {
518 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, ll->rdp);
519 return -1;
520 }
521 writereg(&ll->rdp, LE_C0_IDON);
522 writereg(&ll->rdp, LE_C0_STRT);
523 writereg(&ll->rdp, LE_C0_INEA);
525 return 0;
526 }
528 static int lance_rx(struct net_device *dev)
529 {
530 struct lance_private *lp = netdev_priv(dev);
531 volatile struct lance_init_block *ib;
532 volatile struct lance_rx_desc *rd = 0;
533 unsigned char bits;
534 int len = 0;
535 struct sk_buff *skb = 0;
536 ib = (struct lance_init_block *) (dev->mem_start);
538 #ifdef TEST_HITS
539 {
540 int i;
542 printk("[");
543 for (i = 0; i < RX_RING_SIZE; i++) {
544 if (i == lp->rx_new)
545 printk("%s", ib->brx_ring[i].rmd1_bits &
546 LE_R1_OWN ? "_" : "X");
547 else
548 printk("%s", ib->brx_ring[i].rmd1_bits &
549 LE_R1_OWN ? "." : "1");
550 }
551 printk("]");
552 }
553 #endif
555 for (rd = &ib->brx_ring[lp->rx_new];
556 !((bits = rd->rmd1_bits) & LE_R1_OWN);
557 rd = &ib->brx_ring[lp->rx_new]) {
559 /* We got an incomplete frame? */
560 if ((bits & LE_R1_POK) != LE_R1_POK) {
561 lp->stats.rx_over_errors++;
562 lp->stats.rx_errors++;
563 } else if (bits & LE_R1_ERR) {
564 /* Count only the end frame as a rx error,
565 * not the beginning
566 */
567 if (bits & LE_R1_BUF)
568 lp->stats.rx_fifo_errors++;
569 if (bits & LE_R1_CRC)
570 lp->stats.rx_crc_errors++;
571 if (bits & LE_R1_OFL)
572 lp->stats.rx_over_errors++;
573 if (bits & LE_R1_FRA)
574 lp->stats.rx_frame_errors++;
575 if (bits & LE_R1_EOP)
576 lp->stats.rx_errors++;
577 } else {
578 len = (rd->mblength & 0xfff) - 4;
579 skb = dev_alloc_skb(len + 2);
581 if (skb == 0) {
582 printk("%s: Memory squeeze, deferring packet.\n",
583 dev->name);
584 lp->stats.rx_dropped++;
585 rd->mblength = 0;
586 rd->rmd1_bits = LE_R1_OWN;
587 lp->rx_new = (lp->rx_new + 1) & RX_RING_MOD_MASK;
588 return 0;
589 }
590 lp->stats.rx_bytes += len;
592 skb->dev = dev;
593 skb_reserve(skb, 2); /* 16 byte align */
594 skb_put(skb, len); /* make room */
596 cp_from_buf(lp->type, skb->data,
597 (char *)lp->rx_buf_ptr_cpu[lp->rx_new],
598 len);
600 skb->protocol = eth_type_trans(skb, dev);
601 netif_rx(skb);
602 dev->last_rx = jiffies;
603 lp->stats.rx_packets++;
604 }
606 /* Return the packet to the pool */
607 rd->mblength = 0;
608 rd->length = -RX_BUFF_SIZE | 0xf000;
609 rd->rmd1_bits = LE_R1_OWN;
610 lp->rx_new = (lp->rx_new + 1) & RX_RING_MOD_MASK;
611 }
612 return 0;
613 }
615 static void lance_tx(struct net_device *dev)
616 {
617 struct lance_private *lp = netdev_priv(dev);
618 volatile struct lance_init_block *ib;
619 volatile struct lance_regs *ll = lp->ll;
620 volatile struct lance_tx_desc *td;
621 int i, j;
622 int status;
623 ib = (struct lance_init_block *) (dev->mem_start);
624 j = lp->tx_old;
626 spin_lock(&lp->lock);
628 for (i = j; i != lp->tx_new; i = j) {
629 td = &ib->btx_ring[i];
630 /* If we hit a packet not owned by us, stop */
631 if (td->tmd1_bits & LE_T1_OWN)
632 break;
634 if (td->tmd1_bits & LE_T1_ERR) {
635 status = td->misc;
637 lp->stats.tx_errors++;
638 if (status & LE_T3_RTY)
639 lp->stats.tx_aborted_errors++;
640 if (status & LE_T3_LCOL)
641 lp->stats.tx_window_errors++;
643 if (status & LE_T3_CLOS) {
644 lp->stats.tx_carrier_errors++;
645 printk("%s: Carrier Lost\n", dev->name);
646 /* Stop the lance */
647 writereg(&ll->rap, LE_CSR0);
648 writereg(&ll->rdp, LE_C0_STOP);
649 lance_init_ring(dev);
650 load_csrs(lp);
651 init_restart_lance(lp);
652 goto out;
653 }
654 /* Buffer errors and underflows turn off the
655 * transmitter, restart the adapter.
656 */
657 if (status & (LE_T3_BUF | LE_T3_UFL)) {
658 lp->stats.tx_fifo_errors++;
660 printk("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
661 dev->name);
662 /* Stop the lance */
663 writereg(&ll->rap, LE_CSR0);
664 writereg(&ll->rdp, LE_C0_STOP);
665 lance_init_ring(dev);
666 load_csrs(lp);
667 init_restart_lance(lp);
668 goto out;
669 }
670 } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
671 /*
672 * So we don't count the packet more than once.
673 */
674 td->tmd1_bits &= ~(LE_T1_POK);
676 /* One collision before packet was sent. */
677 if (td->tmd1_bits & LE_T1_EONE)
678 lp->stats.collisions++;
680 /* More than one collision, be optimistic. */
681 if (td->tmd1_bits & LE_T1_EMORE)
682 lp->stats.collisions += 2;
684 lp->stats.tx_packets++;
685 }
686 j = (j + 1) & TX_RING_MOD_MASK;
687 }
688 lp->tx_old = j;
689 out:
690 if (netif_queue_stopped(dev) &&
691 TX_BUFFS_AVAIL > 0)
692 netif_wake_queue(dev);
694 spin_unlock(&lp->lock);
695 }
697 static irqreturn_t lance_dma_merr_int(const int irq, void *dev_id,
698 struct pt_regs *regs)
699 {
700 struct net_device *dev = (struct net_device *) dev_id;
702 printk("%s: DMA error\n", dev->name);
703 return IRQ_HANDLED;
704 }
706 static irqreturn_t lance_interrupt(const int irq, void *dev_id,
707 struct pt_regs *regs)
708 {
709 struct net_device *dev = (struct net_device *) dev_id;
710 struct lance_private *lp = netdev_priv(dev);
711 volatile struct lance_regs *ll = lp->ll;
712 int csr0;
714 writereg(&ll->rap, LE_CSR0);
715 csr0 = ll->rdp;
717 /* Acknowledge all the interrupt sources ASAP */
718 writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT));
720 if ((csr0 & LE_C0_ERR)) {
721 /* Clear the error condition */
722 writereg(&ll->rdp, LE_C0_BABL | LE_C0_ERR | LE_C0_MISS |
723 LE_C0_CERR | LE_C0_MERR);
724 }
725 if (csr0 & LE_C0_RINT)
726 lance_rx(dev);
728 if (csr0 & LE_C0_TINT)
729 lance_tx(dev);
731 if (csr0 & LE_C0_BABL)
732 lp->stats.tx_errors++;
734 if (csr0 & LE_C0_MISS)
735 lp->stats.rx_errors++;
737 if (csr0 & LE_C0_MERR) {
738 printk("%s: Memory error, status %04x\n", dev->name, csr0);
740 writereg(&ll->rdp, LE_C0_STOP);
742 lance_init_ring(dev);
743 load_csrs(lp);
744 init_restart_lance(lp);
745 netif_wake_queue(dev);
746 }
748 writereg(&ll->rdp, LE_C0_INEA);
749 writereg(&ll->rdp, LE_C0_INEA);
750 return IRQ_HANDLED;
751 }
753 struct net_device *last_dev = 0;
755 static int lance_open(struct net_device *dev)
756 {
757 volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
758 struct lance_private *lp = netdev_priv(dev);
759 volatile struct lance_regs *ll = lp->ll;
760 int status = 0;
762 last_dev = dev;
764 /* Stop the Lance */
765 writereg(&ll->rap, LE_CSR0);
766 writereg(&ll->rdp, LE_C0_STOP);
768 /* Set mode and clear multicast filter only at device open,
769 * so that lance_init_ring() called at any error will not
770 * forget multicast filters.
771 *
772 * BTW it is common bug in all lance drivers! --ANK
773 */
774 ib->mode = 0;
775 ib->filter [0] = 0;
776 ib->filter [2] = 0;
777 ib->filter [4] = 0;
778 ib->filter [6] = 0;
780 lance_init_ring(dev);
781 load_csrs(lp);
783 netif_start_queue(dev);
785 /* Associate IRQ with lance_interrupt */
786 if (request_irq(dev->irq, &lance_interrupt, 0, "lance", dev)) {
787 printk("%s: Can't get IRQ %d\n", dev->name, dev->irq);
788 return -EAGAIN;
789 }
790 if (lp->dma_irq >= 0) {
791 unsigned long flags;
793 if (request_irq(lp->dma_irq, &lance_dma_merr_int, 0,
794 "lance error", dev)) {
795 free_irq(dev->irq, dev);
796 printk("%s: Can't get DMA IRQ %d\n", dev->name,
797 lp->dma_irq);
798 return -EAGAIN;
799 }
801 spin_lock_irqsave(&ioasic_ssr_lock, flags);
803 fast_mb();
804 /* Enable I/O ASIC LANCE DMA. */
805 ioasic_write(IO_REG_SSR,
806 ioasic_read(IO_REG_SSR) | IO_SSR_LANCE_DMA_EN);
808 fast_mb();
809 spin_unlock_irqrestore(&ioasic_ssr_lock, flags);
810 }
812 status = init_restart_lance(lp);
813 return status;
814 }
816 static int lance_close(struct net_device *dev)
817 {
818 struct lance_private *lp = netdev_priv(dev);
819 volatile struct lance_regs *ll = lp->ll;
821 netif_stop_queue(dev);
822 del_timer_sync(&lp->multicast_timer);
824 /* Stop the card */
825 writereg(&ll->rap, LE_CSR0);
826 writereg(&ll->rdp, LE_C0_STOP);
828 if (lp->dma_irq >= 0) {
829 unsigned long flags;
831 spin_lock_irqsave(&ioasic_ssr_lock, flags);
833 fast_mb();
834 /* Disable I/O ASIC LANCE DMA. */
835 ioasic_write(IO_REG_SSR,
836 ioasic_read(IO_REG_SSR) & ~IO_SSR_LANCE_DMA_EN);
838 fast_iob();
839 spin_unlock_irqrestore(&ioasic_ssr_lock, flags);
841 free_irq(lp->dma_irq, dev);
842 }
843 free_irq(dev->irq, dev);
844 return 0;
845 }
847 static inline int lance_reset(struct net_device *dev)
848 {
849 struct lance_private *lp = netdev_priv(dev);
850 volatile struct lance_regs *ll = lp->ll;
851 int status;
853 /* Stop the lance */
854 writereg(&ll->rap, LE_CSR0);
855 writereg(&ll->rdp, LE_C0_STOP);
857 lance_init_ring(dev);
858 load_csrs(lp);
859 dev->trans_start = jiffies;
860 status = init_restart_lance(lp);
861 return status;
862 }
864 static void lance_tx_timeout(struct net_device *dev)
865 {
866 struct lance_private *lp = netdev_priv(dev);
867 volatile struct lance_regs *ll = lp->ll;
869 printk(KERN_ERR "%s: transmit timed out, status %04x, reset\n",
870 dev->name, ll->rdp);
871 lance_reset(dev);
872 netif_wake_queue(dev);
873 }
875 static int lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
876 {
877 struct lance_private *lp = netdev_priv(dev);
878 volatile struct lance_regs *ll = lp->ll;
879 volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
880 int entry, skblen, len;
882 skblen = skb->len;
884 len = skblen;
886 if (len < ETH_ZLEN) {
887 if (skb_padto(skb, ETH_ZLEN))
888 return 0;
889 len = ETH_ZLEN;
890 }
892 lp->stats.tx_bytes += len;
894 entry = lp->tx_new & TX_RING_MOD_MASK;
895 ib->btx_ring[entry].length = (-len);
896 ib->btx_ring[entry].misc = 0;
898 cp_to_buf(lp->type, (char *)lp->tx_buf_ptr_cpu[entry], skb->data,
899 skblen);
901 /* Clear the slack of the packet, do I need this? */
902 /* For a firewall it's a good idea - AC */
903 /*
904 if (len != skblen)
905 memset ((char *) &ib->tx_buf [entry][skblen], 0, (len - skblen) << 1);
906 */
908 /* Now, give the packet to the lance */
909 ib->btx_ring[entry].tmd1_bits = (LE_T1_POK | LE_T1_OWN);
910 lp->tx_new = (lp->tx_new + 1) & TX_RING_MOD_MASK;
912 if (TX_BUFFS_AVAIL <= 0)
913 netif_stop_queue(dev);
915 /* Kick the lance: transmit now */
916 writereg(&ll->rdp, LE_C0_INEA | LE_C0_TDMD);
918 spin_unlock_irq(&lp->lock);
920 dev->trans_start = jiffies;
921 dev_kfree_skb(skb);
923 return 0;
924 }
926 static struct net_device_stats *lance_get_stats(struct net_device *dev)
927 {
928 struct lance_private *lp = netdev_priv(dev);
930 return &lp->stats;
931 }
933 static void lance_load_multicast(struct net_device *dev)
934 {
935 volatile struct lance_init_block *ib = (struct lance_init_block *) (dev->mem_start);
936 volatile u16 *mcast_table = (u16 *) & ib->filter;
937 struct dev_mc_list *dmi = dev->mc_list;
938 char *addrs;
939 int i;
940 u32 crc;
942 /* set all multicast bits */
943 if (dev->flags & IFF_ALLMULTI) {
944 ib->filter[0] = 0xffff;
945 ib->filter[2] = 0xffff;
946 ib->filter[4] = 0xffff;
947 ib->filter[6] = 0xffff;
948 return;
949 }
950 /* clear the multicast filter */
951 ib->filter[0] = 0;
952 ib->filter[2] = 0;
953 ib->filter[4] = 0;
954 ib->filter[6] = 0;
956 /* Add addresses */
957 for (i = 0; i < dev->mc_count; i++) {
958 addrs = dmi->dmi_addr;
959 dmi = dmi->next;
961 /* multicast address? */
962 if (!(*addrs & 1))
963 continue;
965 crc = ether_crc_le(ETH_ALEN, addrs);
966 crc = crc >> 26;
967 mcast_table[2 * (crc >> 4)] |= 1 << (crc & 0xf);
968 }
969 return;
970 }
972 static void lance_set_multicast(struct net_device *dev)
973 {
974 struct lance_private *lp = netdev_priv(dev);
975 volatile struct lance_init_block *ib;
976 volatile struct lance_regs *ll = lp->ll;
978 ib = (struct lance_init_block *) (dev->mem_start);
980 if (!netif_running(dev))
981 return;
983 if (lp->tx_old != lp->tx_new) {
984 mod_timer(&lp->multicast_timer, jiffies + 4 * HZ/100);
985 netif_wake_queue(dev);
986 return;
987 }
989 netif_stop_queue(dev);
991 writereg(&ll->rap, LE_CSR0);
992 writereg(&ll->rdp, LE_C0_STOP);
994 lance_init_ring(dev);
996 if (dev->flags & IFF_PROMISC) {
997 ib->mode |= LE_MO_PROM;
998 } else {
999 ib->mode &= ~LE_MO_PROM;
1000 lance_load_multicast(dev);
1002 load_csrs(lp);
1003 init_restart_lance(lp);
1004 netif_wake_queue(dev);
1007 static void lance_set_multicast_retry(unsigned long _opaque)
1009 struct net_device *dev = (struct net_device *) _opaque;
1011 lance_set_multicast(dev);
1014 static int __init dec_lance_init(const int type, const int slot)
1016 static unsigned version_printed;
1017 static const char fmt[] = "declance%d";
1018 char name[10];
1019 struct net_device *dev;
1020 struct lance_private *lp;
1021 volatile struct lance_regs *ll;
1022 int i, ret;
1023 unsigned long esar_base;
1024 unsigned char *esar;
1026 if (dec_lance_debug && version_printed++ == 0)
1027 printk(version);
1029 i = 0;
1030 dev = root_lance_dev;
1031 while (dev) {
1032 i++;
1033 lp = (struct lance_private *)dev->priv;
1034 dev = lp->next;
1036 snprintf(name, sizeof(name), fmt, i);
1038 dev = alloc_etherdev(sizeof(struct lance_private));
1039 if (!dev) {
1040 printk(KERN_ERR "%s: Unable to allocate etherdev, aborting.\n",
1041 name);
1042 ret = -ENOMEM;
1043 goto err_out;
1046 /*
1047 * alloc_etherdev ensures the data structures used by the LANCE
1048 * are aligned.
1049 */
1050 lp = netdev_priv(dev);
1051 spin_lock_init(&lp->lock);
1053 lp->type = type;
1054 lp->slot = slot;
1055 switch (type) {
1056 #ifdef CONFIG_TC
1057 case ASIC_LANCE:
1058 dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE);
1060 /* buffer space for the on-board LANCE shared memory */
1061 /*
1062 * FIXME: ugly hack!
1063 */
1064 dev->mem_start = CKSEG1ADDR(0x00020000);
1065 dev->mem_end = dev->mem_start + 0x00020000;
1066 dev->irq = dec_interrupt[DEC_IRQ_LANCE];
1067 esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR);
1069 /* Workaround crash with booting KN04 2.1k from Disk */
1070 memset((void *)dev->mem_start, 0,
1071 dev->mem_end - dev->mem_start);
1073 /*
1074 * setup the pointer arrays, this sucks [tm] :-(
1075 */
1076 for (i = 0; i < RX_RING_SIZE; i++) {
1077 lp->rx_buf_ptr_cpu[i] =
1078 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1079 2 * i * RX_BUFF_SIZE);
1080 lp->rx_buf_ptr_lnc[i] =
1081 (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
1083 for (i = 0; i < TX_RING_SIZE; i++) {
1084 lp->tx_buf_ptr_cpu[i] =
1085 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1086 2 * RX_RING_SIZE * RX_BUFF_SIZE +
1087 2 * i * TX_BUFF_SIZE);
1088 lp->tx_buf_ptr_lnc[i] =
1089 (char *)(BUF_OFFSET_LNC +
1090 RX_RING_SIZE * RX_BUFF_SIZE +
1091 i * TX_BUFF_SIZE);
1094 /* Setup I/O ASIC LANCE DMA. */
1095 lp->dma_irq = dec_interrupt[DEC_IRQ_LANCE_MERR];
1096 ioasic_write(IO_REG_LANCE_DMA_P,
1097 CPHYSADDR(dev->mem_start) << 3);
1099 break;
1101 case PMAD_LANCE:
1102 claim_tc_card(slot);
1104 dev->mem_start = CKSEG1ADDR(get_tc_base_addr(slot));
1105 dev->base_addr = dev->mem_start + 0x100000;
1106 dev->irq = get_tc_irq_nr(slot);
1107 esar_base = dev->mem_start + 0x1c0002;
1108 lp->dma_irq = -1;
1110 for (i = 0; i < RX_RING_SIZE; i++) {
1111 lp->rx_buf_ptr_cpu[i] =
1112 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1113 i * RX_BUFF_SIZE);
1114 lp->rx_buf_ptr_lnc[i] =
1115 (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
1117 for (i = 0; i < TX_RING_SIZE; i++) {
1118 lp->tx_buf_ptr_cpu[i] =
1119 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1120 RX_RING_SIZE * RX_BUFF_SIZE +
1121 i * TX_BUFF_SIZE);
1122 lp->tx_buf_ptr_lnc[i] =
1123 (char *)(BUF_OFFSET_LNC +
1124 RX_RING_SIZE * RX_BUFF_SIZE +
1125 i * TX_BUFF_SIZE);
1128 break;
1129 #endif
1131 case PMAX_LANCE:
1132 dev->irq = dec_interrupt[DEC_IRQ_LANCE];
1133 dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE);
1134 dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM);
1135 esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);
1136 lp->dma_irq = -1;
1138 /*
1139 * setup the pointer arrays, this sucks [tm] :-(
1140 */
1141 for (i = 0; i < RX_RING_SIZE; i++) {
1142 lp->rx_buf_ptr_cpu[i] =
1143 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1144 2 * i * RX_BUFF_SIZE);
1145 lp->rx_buf_ptr_lnc[i] =
1146 (char *)(BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
1148 for (i = 0; i < TX_RING_SIZE; i++) {
1149 lp->tx_buf_ptr_cpu[i] =
1150 (char *)(dev->mem_start + BUF_OFFSET_CPU +
1151 2 * RX_RING_SIZE * RX_BUFF_SIZE +
1152 2 * i * TX_BUFF_SIZE);
1153 lp->tx_buf_ptr_lnc[i] =
1154 (char *)(BUF_OFFSET_LNC +
1155 RX_RING_SIZE * RX_BUFF_SIZE +
1156 i * TX_BUFF_SIZE);
1159 break;
1161 default:
1162 printk(KERN_ERR "%s: declance_init called with unknown type\n",
1163 name);
1164 ret = -ENODEV;
1165 goto err_out_free_dev;
1168 ll = (struct lance_regs *) dev->base_addr;
1169 esar = (unsigned char *) esar_base;
1171 /* prom checks */
1172 /* First, check for test pattern */
1173 if (esar[0x60] != 0xff && esar[0x64] != 0x00 &&
1174 esar[0x68] != 0x55 && esar[0x6c] != 0xaa) {
1175 printk(KERN_ERR
1176 "%s: Ethernet station address prom not found!\n",
1177 name);
1178 ret = -ENODEV;
1179 goto err_out_free_dev;
1181 /* Check the prom contents */
1182 for (i = 0; i < 8; i++) {
1183 if (esar[i * 4] != esar[0x3c - i * 4] &&
1184 esar[i * 4] != esar[0x40 + i * 4] &&
1185 esar[0x3c - i * 4] != esar[0x40 + i * 4]) {
1186 printk(KERN_ERR "%s: Something is wrong with the "
1187 "ethernet station address prom!\n", name);
1188 ret = -ENODEV;
1189 goto err_out_free_dev;
1193 /* Copy the ethernet address to the device structure, later to the
1194 * lance initialization block so the lance gets it every time it's
1195 * (re)initialized.
1196 */
1197 switch (type) {
1198 case ASIC_LANCE:
1199 printk("%s: IOASIC onboard LANCE, addr = ", name);
1200 break;
1201 case PMAD_LANCE:
1202 printk("%s: PMAD-AA, addr = ", name);
1203 break;
1204 case PMAX_LANCE:
1205 printk("%s: PMAX onboard LANCE, addr = ", name);
1206 break;
1208 for (i = 0; i < 6; i++) {
1209 dev->dev_addr[i] = esar[i * 4];
1210 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ',' : ':');
1213 printk(" irq = %d\n", dev->irq);
1215 dev->open = &lance_open;
1216 dev->stop = &lance_close;
1217 dev->hard_start_xmit = &lance_start_xmit;
1218 dev->tx_timeout = &lance_tx_timeout;
1219 dev->watchdog_timeo = 5*HZ;
1220 dev->get_stats = &lance_get_stats;
1221 dev->set_multicast_list = &lance_set_multicast;
1223 /* lp->ll is the location of the registers for lance card */
1224 lp->ll = ll;
1226 /* busmaster_regval (CSR3) should be zero according to the PMAD-AA
1227 * specification.
1228 */
1229 lp->busmaster_regval = 0;
1231 dev->dma = 0;
1233 /* We cannot sleep if the chip is busy during a
1234 * multicast list update event, because such events
1235 * can occur from interrupts (ex. IPv6). So we
1236 * use a timer to try again later when necessary. -DaveM
1237 */
1238 init_timer(&lp->multicast_timer);
1239 lp->multicast_timer.data = (unsigned long) dev;
1240 lp->multicast_timer.function = &lance_set_multicast_retry;
1242 ret = register_netdev(dev);
1243 if (ret) {
1244 printk(KERN_ERR
1245 "%s: Unable to register netdev, aborting.\n", name);
1246 goto err_out_free_dev;
1249 lp->next = root_lance_dev;
1250 root_lance_dev = dev;
1252 printk("%s: registered as %s.\n", name, dev->name);
1253 return 0;
1255 err_out_free_dev:
1256 free_netdev(dev);
1258 err_out:
1259 return ret;
1263 /* Find all the lance cards on the system and initialize them */
1264 static int __init dec_lance_probe(void)
1266 int count = 0;
1268 /* Scan slots for PMAD-AA cards first. */
1269 #ifdef CONFIG_TC
1270 if (TURBOCHANNEL) {
1271 int slot;
1273 while ((slot = search_tc_card("PMAD-AA")) >= 0) {
1274 if (dec_lance_init(PMAD_LANCE, slot) < 0)
1275 break;
1276 count++;
1279 #endif
1281 /* Then handle onboard devices. */
1282 if (dec_interrupt[DEC_IRQ_LANCE] >= 0) {
1283 if (dec_interrupt[DEC_IRQ_LANCE_MERR] >= 0) {
1284 #ifdef CONFIG_TC
1285 if (dec_lance_init(ASIC_LANCE, -1) >= 0)
1286 count++;
1287 #endif
1288 } else if (!TURBOCHANNEL) {
1289 if (dec_lance_init(PMAX_LANCE, -1) >= 0)
1290 count++;
1294 return (count > 0) ? 0 : -ENODEV;
1297 static void __exit dec_lance_cleanup(void)
1299 while (root_lance_dev) {
1300 struct net_device *dev = root_lance_dev;
1301 struct lance_private *lp = netdev_priv(dev);
1303 unregister_netdev(dev);
1304 #ifdef CONFIG_TC
1305 if (lp->slot >= 0)
1306 release_tc_card(lp->slot);
1307 #endif
1308 root_lance_dev = lp->next;
1309 free_netdev(dev);
1313 module_init(dec_lance_probe);
1314 module_exit(dec_lance_cleanup);