ia64/linux-2.6.18-xen.hg

view drivers/net/chelsio/regs.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*****************************************************************************
2 * *
3 * File: regs.h *
4 * $Revision: 1.8 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
39 #ifndef _CXGB_REGS_H_
40 #define _CXGB_REGS_H_
42 /* SGE registers */
43 #define A_SG_CONTROL 0x0
45 #define S_CMDQ0_ENABLE 0
46 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
47 #define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
49 #define S_CMDQ1_ENABLE 1
50 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
51 #define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
53 #define S_FL0_ENABLE 2
54 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
55 #define F_FL0_ENABLE V_FL0_ENABLE(1U)
57 #define S_FL1_ENABLE 3
58 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
59 #define F_FL1_ENABLE V_FL1_ENABLE(1U)
61 #define S_CPL_ENABLE 4
62 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
63 #define F_CPL_ENABLE V_CPL_ENABLE(1U)
65 #define S_RESPONSE_QUEUE_ENABLE 5
66 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
67 #define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
69 #define S_CMDQ_PRIORITY 6
70 #define M_CMDQ_PRIORITY 0x3
71 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
72 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
74 #define S_DISABLE_CMDQ1_GTS 9
75 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
76 #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
78 #define S_DISABLE_FL0_GTS 10
79 #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
80 #define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)
82 #define S_DISABLE_FL1_GTS 11
83 #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
84 #define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)
86 #define S_ENABLE_BIG_ENDIAN 12
87 #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
88 #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
90 #define S_ISCSI_COALESCE 14
91 #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
92 #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
94 #define S_RX_PKT_OFFSET 15
95 #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
97 #define S_VLAN_XTRACT 18
98 #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
99 #define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
101 #define A_SG_DOORBELL 0x4
102 #define A_SG_CMD0BASELWR 0x8
103 #define A_SG_CMD0BASEUPR 0xc
104 #define A_SG_CMD1BASELWR 0x10
105 #define A_SG_CMD1BASEUPR 0x14
106 #define A_SG_FL0BASELWR 0x18
107 #define A_SG_FL0BASEUPR 0x1c
108 #define A_SG_FL1BASELWR 0x20
109 #define A_SG_FL1BASEUPR 0x24
110 #define A_SG_CMD0SIZE 0x28
111 #define A_SG_FL0SIZE 0x2c
112 #define A_SG_RSPSIZE 0x30
113 #define A_SG_RSPBASELWR 0x34
114 #define A_SG_RSPBASEUPR 0x38
115 #define A_SG_FLTHRESHOLD 0x3c
116 #define A_SG_RSPQUEUECREDIT 0x40
117 #define A_SG_SLEEPING 0x48
118 #define A_SG_INTRTIMER 0x4c
119 #define A_SG_CMD1SIZE 0xb0
120 #define A_SG_FL1SIZE 0xb4
121 #define A_SG_INT_ENABLE 0xb8
123 #define S_RESPQ_EXHAUSTED 0
124 #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
125 #define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
127 #define S_RESPQ_OVERFLOW 1
128 #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
129 #define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
131 #define S_FL_EXHAUSTED 2
132 #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
133 #define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
135 #define S_PACKET_TOO_BIG 3
136 #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
137 #define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
139 #define S_PACKET_MISMATCH 4
140 #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
141 #define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
143 #define A_SG_INT_CAUSE 0xbc
144 #define A_SG_RESPACCUTIMER 0xc0
146 /* MC3 registers */
148 #define S_READY 1
149 #define V_READY(x) ((x) << S_READY)
150 #define F_READY V_READY(1U)
152 /* MC4 registers */
154 #define A_MC4_CFG 0x180
155 #define S_MC4_SLOW 25
156 #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
157 #define F_MC4_SLOW V_MC4_SLOW(1U)
159 /* TPI registers */
161 #define A_TPI_ADDR 0x280
162 #define A_TPI_WR_DATA 0x284
163 #define A_TPI_RD_DATA 0x288
164 #define A_TPI_CSR 0x28c
166 #define S_TPIWR 0
167 #define V_TPIWR(x) ((x) << S_TPIWR)
168 #define F_TPIWR V_TPIWR(1U)
170 #define S_TPIRDY 1
171 #define V_TPIRDY(x) ((x) << S_TPIRDY)
172 #define F_TPIRDY V_TPIRDY(1U)
174 #define A_TPI_PAR 0x29c
176 #define S_TPIPAR 0
177 #define M_TPIPAR 0x7f
178 #define V_TPIPAR(x) ((x) << S_TPIPAR)
179 #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
181 /* TP registers */
183 #define A_TP_IN_CONFIG 0x300
185 #define S_TP_IN_CSPI_CPL 3
186 #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
187 #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
189 #define S_TP_IN_CSPI_CHECK_IP_CSUM 5
190 #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
191 #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
193 #define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
194 #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
195 #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
197 #define S_TP_IN_ESPI_ETHERNET 8
198 #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
199 #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
201 #define S_TP_IN_ESPI_CHECK_IP_CSUM 12
202 #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
203 #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
205 #define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
206 #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
207 #define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
209 #define S_OFFLOAD_DISABLE 14
210 #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
211 #define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
213 #define A_TP_OUT_CONFIG 0x304
215 #define S_TP_OUT_CSPI_CPL 2
216 #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
217 #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
219 #define S_TP_OUT_ESPI_ETHERNET 6
220 #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
221 #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
223 #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
224 #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
225 #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
227 #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
228 #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
229 #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
231 #define A_TP_GLOBAL_CONFIG 0x308
233 #define S_IP_TTL 0
234 #define M_IP_TTL 0xff
235 #define V_IP_TTL(x) ((x) << S_IP_TTL)
237 #define S_TCP_CSUM 11
238 #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
239 #define F_TCP_CSUM V_TCP_CSUM(1U)
241 #define S_UDP_CSUM 12
242 #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
243 #define F_UDP_CSUM V_UDP_CSUM(1U)
245 #define S_IP_CSUM 13
246 #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
247 #define F_IP_CSUM V_IP_CSUM(1U)
249 #define S_PATH_MTU 15
250 #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
251 #define F_PATH_MTU V_PATH_MTU(1U)
253 #define S_5TUPLE_LOOKUP 17
254 #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
256 #define S_SYN_COOKIE_PARAMETER 26
257 #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
259 #define A_TP_PC_CONFIG 0x348
260 #define S_DIS_TX_FILL_WIN_PUSH 12
261 #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
262 #define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
264 #define S_TP_PC_REV 30
265 #define M_TP_PC_REV 0x3
266 #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
267 #define A_TP_RESET 0x44c
268 #define S_TP_RESET 0
269 #define V_TP_RESET(x) ((x) << S_TP_RESET)
270 #define F_TP_RESET V_TP_RESET(1U)
272 #define A_TP_INT_ENABLE 0x470
273 #define A_TP_INT_CAUSE 0x474
274 #define A_TP_TX_DROP_CONFIG 0x4b8
276 #define S_ENABLE_TX_DROP 31
277 #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
278 #define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
280 #define S_ENABLE_TX_ERROR 30
281 #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
282 #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
284 #define S_DROP_TICKS_CNT 4
285 #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
287 #define S_NUM_PKTS_DROPPED 0
288 #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
290 /* CSPI registers */
292 #define S_DIP4ERR 0
293 #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
294 #define F_DIP4ERR V_DIP4ERR(1U)
296 #define S_RXDROP 1
297 #define V_RXDROP(x) ((x) << S_RXDROP)
298 #define F_RXDROP V_RXDROP(1U)
300 #define S_TXDROP 2
301 #define V_TXDROP(x) ((x) << S_TXDROP)
302 #define F_TXDROP V_TXDROP(1U)
304 #define S_RXOVERFLOW 3
305 #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
306 #define F_RXOVERFLOW V_RXOVERFLOW(1U)
308 #define S_RAMPARITYERR 4
309 #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
310 #define F_RAMPARITYERR V_RAMPARITYERR(1U)
312 /* ESPI registers */
314 #define A_ESPI_SCH_TOKEN0 0x880
315 #define A_ESPI_SCH_TOKEN1 0x884
316 #define A_ESPI_SCH_TOKEN2 0x888
317 #define A_ESPI_SCH_TOKEN3 0x88c
318 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
319 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
320 #define A_ESPI_CALENDAR_LENGTH 0x898
321 #define A_PORT_CONFIG 0x89c
323 #define S_RX_NPORTS 0
324 #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
326 #define S_TX_NPORTS 8
327 #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
329 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
331 #define S_RXSTATUSENABLE 0
332 #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
333 #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
335 #define S_INTEL1010MODE 4
336 #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
337 #define F_INTEL1010MODE V_INTEL1010MODE(1U)
339 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
340 #define A_ESPI_TRAIN 0x8ac
341 #define A_ESPI_INTR_STATUS 0x8c8
343 #define S_DIP2PARITYERR 5
344 #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
345 #define F_DIP2PARITYERR V_DIP2PARITYERR(1U)
347 #define A_ESPI_INTR_ENABLE 0x8cc
348 #define A_RX_DROP_THRESHOLD 0x8d0
349 #define A_ESPI_RX_RESET 0x8ec
350 #define A_ESPI_MISC_CONTROL 0x8f0
352 #define S_OUT_OF_SYNC_COUNT 0
353 #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
355 #define S_DIP2_PARITY_ERR_THRES 5
356 #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
358 #define S_DIP4_THRES 9
359 #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
361 #define S_MONITORED_PORT_NUM 25
362 #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
364 #define S_MONITORED_DIRECTION 27
365 #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
366 #define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U)
368 #define S_MONITORED_INTERFACE 28
369 #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
370 #define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
372 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
373 #define A_ESPI_CMD_ADDR 0x8f8
375 #define S_WRITE_DATA 0
376 #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
378 #define S_REGISTER_OFFSET 8
379 #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
381 #define S_CHANNEL_ADDR 12
382 #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
384 #define S_MODULE_ADDR 16
385 #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
387 #define S_BUNDLE_ADDR 20
388 #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
390 #define S_SPI4_COMMAND 24
391 #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
393 #define A_ESPI_GOSTAT 0x8fc
394 #define S_ESPI_CMD_BUSY 8
395 #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
396 #define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
398 /* PL registers */
400 #define A_PL_ENABLE 0xa00
402 #define S_PL_INTR_SGE_ERR 0
403 #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
404 #define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U)
406 #define S_PL_INTR_SGE_DATA 1
407 #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
408 #define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
410 #define S_PL_INTR_TP 6
411 #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
412 #define F_PL_INTR_TP V_PL_INTR_TP(1U)
414 #define S_PL_INTR_ESPI 8
415 #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
416 #define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
418 #define S_PL_INTR_PCIX 10
419 #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
420 #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
422 #define S_PL_INTR_EXT 11
423 #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
424 #define F_PL_INTR_EXT V_PL_INTR_EXT(1U)
426 #define A_PL_CAUSE 0xa04
428 /* MC5 registers */
430 #define A_MC5_CONFIG 0xc04
432 #define S_TCAM_RESET 1
433 #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
434 #define F_TCAM_RESET V_TCAM_RESET(1U)
436 #define S_M_BUS_ENABLE 5
437 #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
438 #define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
440 /* PCICFG registers */
442 #define A_PCICFG_PM_CSR 0x44
443 #define A_PCICFG_VPD_ADDR 0x4a
445 #define S_VPD_OP_FLAG 15
446 #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
447 #define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
449 #define A_PCICFG_VPD_DATA 0x4c
451 #define A_PCICFG_INTR_ENABLE 0xf4
452 #define A_PCICFG_INTR_CAUSE 0xf8
454 #define A_PCICFG_MODE 0xfc
456 #define S_PCI_MODE_64BIT 0
457 #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
458 #define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
460 #define S_PCI_MODE_PCIX 5
461 #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
462 #define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
464 #define S_PCI_MODE_CLK 6
465 #define M_PCI_MODE_CLK 0x3
466 #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
468 #endif /* _CXGB_REGS_H_ */