ia64/linux-2.6.18-xen.hg

view drivers/net/chelsio/elmer0.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*****************************************************************************
2 * *
3 * File: elmer0.h *
4 * $Revision: 1.6 $ *
5 * $Date: 2005/06/21 22:49:43 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
39 #ifndef _CXGB_ELMER0_H_
40 #define _CXGB_ELMER0_H_
42 /* ELMER0 registers */
43 #define A_ELMER0_VERSION 0x100000
44 #define A_ELMER0_PHY_CFG 0x100004
45 #define A_ELMER0_INT_ENABLE 0x100008
46 #define A_ELMER0_INT_CAUSE 0x10000c
47 #define A_ELMER0_GPI_CFG 0x100010
48 #define A_ELMER0_GPI_STAT 0x100014
49 #define A_ELMER0_GPO 0x100018
50 #define A_ELMER0_PORT0_MI1_CFG 0x400000
52 #define S_MI1_MDI_ENABLE 0
53 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
54 #define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)
56 #define S_MI1_MDI_INVERT 1
57 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
58 #define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)
60 #define S_MI1_PREAMBLE_ENABLE 2
61 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
62 #define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)
64 #define S_MI1_SOF 3
65 #define M_MI1_SOF 0x3
66 #define V_MI1_SOF(x) ((x) << S_MI1_SOF)
67 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
69 #define S_MI1_CLK_DIV 5
70 #define M_MI1_CLK_DIV 0xff
71 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
72 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
74 #define A_ELMER0_PORT0_MI1_ADDR 0x400004
76 #define S_MI1_REG_ADDR 0
77 #define M_MI1_REG_ADDR 0x1f
78 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
79 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
81 #define S_MI1_PHY_ADDR 5
82 #define M_MI1_PHY_ADDR 0x1f
83 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
84 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
86 #define A_ELMER0_PORT0_MI1_DATA 0x400008
88 #define S_MI1_DATA 0
89 #define M_MI1_DATA 0xffff
90 #define V_MI1_DATA(x) ((x) << S_MI1_DATA)
91 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
93 #define A_ELMER0_PORT0_MI1_OP 0x40000c
95 #define S_MI1_OP 0
96 #define M_MI1_OP 0x3
97 #define V_MI1_OP(x) ((x) << S_MI1_OP)
98 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
100 #define S_MI1_ADDR_AUTOINC 2
101 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
102 #define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)
104 #define S_MI1_OP_BUSY 31
105 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
106 #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)
108 #define A_ELMER0_PORT1_MI1_CFG 0x500000
109 #define A_ELMER0_PORT1_MI1_ADDR 0x500004
110 #define A_ELMER0_PORT1_MI1_DATA 0x500008
111 #define A_ELMER0_PORT1_MI1_OP 0x50000c
112 #define A_ELMER0_PORT2_MI1_CFG 0x600000
113 #define A_ELMER0_PORT2_MI1_ADDR 0x600004
114 #define A_ELMER0_PORT2_MI1_DATA 0x600008
115 #define A_ELMER0_PORT2_MI1_OP 0x60000c
116 #define A_ELMER0_PORT3_MI1_CFG 0x700000
117 #define A_ELMER0_PORT3_MI1_ADDR 0x700004
118 #define A_ELMER0_PORT3_MI1_DATA 0x700008
119 #define A_ELMER0_PORT3_MI1_OP 0x70000c
121 /* Simple bit definition for GPI and GP0 registers. */
122 #define ELMER0_GP_BIT0 0x0001
123 #define ELMER0_GP_BIT1 0x0002
124 #define ELMER0_GP_BIT2 0x0004
125 #define ELMER0_GP_BIT3 0x0008
126 #define ELMER0_GP_BIT4 0x0010
127 #define ELMER0_GP_BIT5 0x0020
128 #define ELMER0_GP_BIT6 0x0040
129 #define ELMER0_GP_BIT7 0x0080
130 #define ELMER0_GP_BIT8 0x0100
131 #define ELMER0_GP_BIT9 0x0200
132 #define ELMER0_GP_BIT10 0x0400
133 #define ELMER0_GP_BIT11 0x0800
134 #define ELMER0_GP_BIT12 0x1000
135 #define ELMER0_GP_BIT13 0x2000
136 #define ELMER0_GP_BIT14 0x4000
137 #define ELMER0_GP_BIT15 0x8000
138 #define ELMER0_GP_BIT16 0x10000
139 #define ELMER0_GP_BIT17 0x20000
140 #define ELMER0_GP_BIT18 0x40000
141 #define ELMER0_GP_BIT19 0x80000
143 #define MI1_OP_DIRECT_WRITE 1
144 #define MI1_OP_DIRECT_READ 2
146 #define MI1_OP_INDIRECT_ADDRESS 0
147 #define MI1_OP_INDIRECT_WRITE 1
148 #define MI1_OP_INDIRECT_READ_INC 2
149 #define MI1_OP_INDIRECT_READ 3
151 #endif /* _CXGB_ELMER0_H_ */