ia64/linux-2.6.18-xen.hg

view drivers/net/bmac.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1998 Randy Gobbel.
6 *
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/proc_fs.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/crc32.h>
21 #include <asm/prom.h>
22 #include <asm/dbdma.h>
23 #include <asm/io.h>
24 #include <asm/page.h>
25 #include <asm/pgtable.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
28 #include <asm/macio.h>
29 #include <asm/irq.h>
31 #include "bmac.h"
33 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
34 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
36 /*
37 * CRC polynomial - used in working out multicast filter bits.
38 */
39 #define ENET_CRCPOLY 0x04c11db7
41 /* switch to use multicast code lifted from sunhme driver */
42 #define SUNHME_MULTICAST
44 #define N_RX_RING 64
45 #define N_TX_RING 32
46 #define MAX_TX_ACTIVE 1
47 #define ETHERCRC 4
48 #define ETHERMINPACKET 64
49 #define ETHERMTU 1500
50 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
51 #define TX_TIMEOUT HZ /* 1 second */
53 /* Bits in transmit DMA status */
54 #define TX_DMA_ERR 0x80
56 #define XXDEBUG(args)
58 struct bmac_data {
59 /* volatile struct bmac *bmac; */
60 struct sk_buff_head *queue;
61 volatile struct dbdma_regs __iomem *tx_dma;
62 int tx_dma_intr;
63 volatile struct dbdma_regs __iomem *rx_dma;
64 int rx_dma_intr;
65 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
66 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
67 struct macio_dev *mdev;
68 int is_bmac_plus;
69 struct sk_buff *rx_bufs[N_RX_RING];
70 int rx_fill;
71 int rx_empty;
72 struct sk_buff *tx_bufs[N_TX_RING];
73 int tx_fill;
74 int tx_empty;
75 unsigned char tx_fullup;
76 struct net_device_stats stats;
77 struct timer_list tx_timeout;
78 int timeout_active;
79 int sleeping;
80 int opened;
81 unsigned short hash_use_count[64];
82 unsigned short hash_table_mask[4];
83 spinlock_t lock;
84 };
86 #if 0 /* Move that to ethtool */
88 typedef struct bmac_reg_entry {
89 char *name;
90 unsigned short reg_offset;
91 } bmac_reg_entry_t;
93 #define N_REG_ENTRIES 31
95 static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
96 {"MEMADD", MEMADD},
97 {"MEMDATAHI", MEMDATAHI},
98 {"MEMDATALO", MEMDATALO},
99 {"TXPNTR", TXPNTR},
100 {"RXPNTR", RXPNTR},
101 {"IPG1", IPG1},
102 {"IPG2", IPG2},
103 {"ALIMIT", ALIMIT},
104 {"SLOT", SLOT},
105 {"PALEN", PALEN},
106 {"PAPAT", PAPAT},
107 {"TXSFD", TXSFD},
108 {"JAM", JAM},
109 {"TXCFG", TXCFG},
110 {"TXMAX", TXMAX},
111 {"TXMIN", TXMIN},
112 {"PAREG", PAREG},
113 {"DCNT", DCNT},
114 {"NCCNT", NCCNT},
115 {"NTCNT", NTCNT},
116 {"EXCNT", EXCNT},
117 {"LTCNT", LTCNT},
118 {"TXSM", TXSM},
119 {"RXCFG", RXCFG},
120 {"RXMAX", RXMAX},
121 {"RXMIN", RXMIN},
122 {"FRCNT", FRCNT},
123 {"AECNT", AECNT},
124 {"FECNT", FECNT},
125 {"RXSM", RXSM},
126 {"RXCV", RXCV}
127 };
129 #endif
131 static unsigned char *bmac_emergency_rxbuf;
133 /*
134 * Number of bytes of private data per BMAC: allow enough for
135 * the rx and tx dma commands plus a branch dma command each,
136 * and another 16 bytes to allow us to align the dma command
137 * buffers on a 16 byte boundary.
138 */
139 #define PRIV_BYTES (sizeof(struct bmac_data) \
140 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
141 + sizeof(struct sk_buff_head))
143 static unsigned char bitrev(unsigned char b);
144 static int bmac_open(struct net_device *dev);
145 static int bmac_close(struct net_device *dev);
146 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
147 static struct net_device_stats *bmac_stats(struct net_device *dev);
148 static void bmac_set_multicast(struct net_device *dev);
149 static void bmac_reset_and_enable(struct net_device *dev);
150 static void bmac_start_chip(struct net_device *dev);
151 static void bmac_init_chip(struct net_device *dev);
152 static void bmac_init_registers(struct net_device *dev);
153 static void bmac_enable_and_reset_chip(struct net_device *dev);
154 static int bmac_set_address(struct net_device *dev, void *addr);
155 static irqreturn_t bmac_misc_intr(int irq, void *dev_id, struct pt_regs *regs);
156 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
157 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);
158 static void bmac_set_timeout(struct net_device *dev);
159 static void bmac_tx_timeout(unsigned long data);
160 static int bmac_output(struct sk_buff *skb, struct net_device *dev);
161 static void bmac_start(struct net_device *dev);
163 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
164 #define DBDMA_CLEAR(x) ( (x) << 16)
166 static inline void
167 dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
168 {
169 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
170 return;
171 }
173 static inline unsigned long
174 dbdma_ld32(volatile __u32 __iomem *a)
175 {
176 __u32 swap;
177 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
178 return swap;
179 }
181 static void
182 dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
183 {
184 dbdma_st32(&dmap->control,
185 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
186 eieio();
187 }
189 static void
190 dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
191 {
192 dbdma_st32(&dmap->control,
193 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
194 eieio();
195 while (dbdma_ld32(&dmap->status) & RUN)
196 eieio();
197 }
199 static void
200 dbdma_setcmd(volatile struct dbdma_cmd *cp,
201 unsigned short cmd, unsigned count, unsigned long addr,
202 unsigned long cmd_dep)
203 {
204 out_le16(&cp->command, cmd);
205 out_le16(&cp->req_count, count);
206 out_le32(&cp->phy_addr, addr);
207 out_le32(&cp->cmd_dep, cmd_dep);
208 out_le16(&cp->xfer_status, 0);
209 out_le16(&cp->res_count, 0);
210 }
212 static inline
213 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
214 {
215 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
216 }
219 static inline
220 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
221 {
222 return in_le16((void __iomem *)dev->base_addr + reg_offset);
223 }
225 static void
226 bmac_enable_and_reset_chip(struct net_device *dev)
227 {
228 struct bmac_data *bp = netdev_priv(dev);
229 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
230 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
232 if (rd)
233 dbdma_reset(rd);
234 if (td)
235 dbdma_reset(td);
237 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
238 }
240 #define MIFDELAY udelay(10)
242 static unsigned int
243 bmac_mif_readbits(struct net_device *dev, int nb)
244 {
245 unsigned int val = 0;
247 while (--nb >= 0) {
248 bmwrite(dev, MIFCSR, 0);
249 MIFDELAY;
250 if (bmread(dev, MIFCSR) & 8)
251 val |= 1 << nb;
252 bmwrite(dev, MIFCSR, 1);
253 MIFDELAY;
254 }
255 bmwrite(dev, MIFCSR, 0);
256 MIFDELAY;
257 bmwrite(dev, MIFCSR, 1);
258 MIFDELAY;
259 return val;
260 }
262 static void
263 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
264 {
265 int b;
267 while (--nb >= 0) {
268 b = (val & (1 << nb))? 6: 4;
269 bmwrite(dev, MIFCSR, b);
270 MIFDELAY;
271 bmwrite(dev, MIFCSR, b|1);
272 MIFDELAY;
273 }
274 }
276 static unsigned int
277 bmac_mif_read(struct net_device *dev, unsigned int addr)
278 {
279 unsigned int val;
281 bmwrite(dev, MIFCSR, 4);
282 MIFDELAY;
283 bmac_mif_writebits(dev, ~0U, 32);
284 bmac_mif_writebits(dev, 6, 4);
285 bmac_mif_writebits(dev, addr, 10);
286 bmwrite(dev, MIFCSR, 2);
287 MIFDELAY;
288 bmwrite(dev, MIFCSR, 1);
289 MIFDELAY;
290 val = bmac_mif_readbits(dev, 17);
291 bmwrite(dev, MIFCSR, 4);
292 MIFDELAY;
293 return val;
294 }
296 static void
297 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
298 {
299 bmwrite(dev, MIFCSR, 4);
300 MIFDELAY;
301 bmac_mif_writebits(dev, ~0U, 32);
302 bmac_mif_writebits(dev, 5, 4);
303 bmac_mif_writebits(dev, addr, 10);
304 bmac_mif_writebits(dev, 2, 2);
305 bmac_mif_writebits(dev, val, 16);
306 bmac_mif_writebits(dev, 3, 2);
307 }
309 static void
310 bmac_init_registers(struct net_device *dev)
311 {
312 struct bmac_data *bp = netdev_priv(dev);
313 volatile unsigned short regValue;
314 unsigned short *pWord16;
315 int i;
317 /* XXDEBUG(("bmac: enter init_registers\n")); */
319 bmwrite(dev, RXRST, RxResetValue);
320 bmwrite(dev, TXRST, TxResetBit);
322 i = 100;
323 do {
324 --i;
325 udelay(10000);
326 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
327 } while ((regValue & TxResetBit) && i > 0);
329 if (!bp->is_bmac_plus) {
330 regValue = bmread(dev, XCVRIF);
331 regValue |= ClkBit | SerialMode | COLActiveLow;
332 bmwrite(dev, XCVRIF, regValue);
333 udelay(10000);
334 }
336 bmwrite(dev, RSEED, (unsigned short)0x1968);
338 regValue = bmread(dev, XIFC);
339 regValue |= TxOutputEnable;
340 bmwrite(dev, XIFC, regValue);
342 bmread(dev, PAREG);
344 /* set collision counters to 0 */
345 bmwrite(dev, NCCNT, 0);
346 bmwrite(dev, NTCNT, 0);
347 bmwrite(dev, EXCNT, 0);
348 bmwrite(dev, LTCNT, 0);
350 /* set rx counters to 0 */
351 bmwrite(dev, FRCNT, 0);
352 bmwrite(dev, LECNT, 0);
353 bmwrite(dev, AECNT, 0);
354 bmwrite(dev, FECNT, 0);
355 bmwrite(dev, RXCV, 0);
357 /* set tx fifo information */
358 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
360 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
361 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
363 /* set rx fifo information */
364 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
365 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
367 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
368 bmread(dev, STATUS); /* read it just to clear it */
370 /* zero out the chip Hash Filter registers */
371 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
372 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
373 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
374 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
375 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
377 pWord16 = (unsigned short *)dev->dev_addr;
378 bmwrite(dev, MADD0, *pWord16++);
379 bmwrite(dev, MADD1, *pWord16++);
380 bmwrite(dev, MADD2, *pWord16);
382 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
384 bmwrite(dev, INTDISABLE, EnableNormal);
386 return;
387 }
389 #if 0
390 static void
391 bmac_disable_interrupts(struct net_device *dev)
392 {
393 bmwrite(dev, INTDISABLE, DisableAll);
394 }
396 static void
397 bmac_enable_interrupts(struct net_device *dev)
398 {
399 bmwrite(dev, INTDISABLE, EnableNormal);
400 }
401 #endif
404 static void
405 bmac_start_chip(struct net_device *dev)
406 {
407 struct bmac_data *bp = netdev_priv(dev);
408 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
409 unsigned short oldConfig;
411 /* enable rx dma channel */
412 dbdma_continue(rd);
414 oldConfig = bmread(dev, TXCFG);
415 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
417 /* turn on rx plus any other bits already on (promiscuous possibly) */
418 oldConfig = bmread(dev, RXCFG);
419 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
420 udelay(20000);
421 }
423 static void
424 bmac_init_phy(struct net_device *dev)
425 {
426 unsigned int addr;
427 struct bmac_data *bp = netdev_priv(dev);
429 printk(KERN_DEBUG "phy registers:");
430 for (addr = 0; addr < 32; ++addr) {
431 if ((addr & 7) == 0)
432 printk("\n" KERN_DEBUG);
433 printk(" %.4x", bmac_mif_read(dev, addr));
434 }
435 printk("\n");
436 if (bp->is_bmac_plus) {
437 unsigned int capable, ctrl;
439 ctrl = bmac_mif_read(dev, 0);
440 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
441 if (bmac_mif_read(dev, 4) != capable
442 || (ctrl & 0x1000) == 0) {
443 bmac_mif_write(dev, 4, capable);
444 bmac_mif_write(dev, 0, 0x1200);
445 } else
446 bmac_mif_write(dev, 0, 0x1000);
447 }
448 }
450 static void bmac_init_chip(struct net_device *dev)
451 {
452 bmac_init_phy(dev);
453 bmac_init_registers(dev);
454 }
456 #ifdef CONFIG_PM
457 static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
458 {
459 struct net_device* dev = macio_get_drvdata(mdev);
460 struct bmac_data *bp = netdev_priv(dev);
461 unsigned long flags;
462 unsigned short config;
463 int i;
465 netif_device_detach(dev);
466 /* prolly should wait for dma to finish & turn off the chip */
467 spin_lock_irqsave(&bp->lock, flags);
468 if (bp->timeout_active) {
469 del_timer(&bp->tx_timeout);
470 bp->timeout_active = 0;
471 }
472 disable_irq(dev->irq);
473 disable_irq(bp->tx_dma_intr);
474 disable_irq(bp->rx_dma_intr);
475 bp->sleeping = 1;
476 spin_unlock_irqrestore(&bp->lock, flags);
477 if (bp->opened) {
478 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
479 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
481 config = bmread(dev, RXCFG);
482 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
483 config = bmread(dev, TXCFG);
484 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
485 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
486 /* disable rx and tx dma */
487 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
488 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
489 /* free some skb's */
490 for (i=0; i<N_RX_RING; i++) {
491 if (bp->rx_bufs[i] != NULL) {
492 dev_kfree_skb(bp->rx_bufs[i]);
493 bp->rx_bufs[i] = NULL;
494 }
495 }
496 for (i = 0; i<N_TX_RING; i++) {
497 if (bp->tx_bufs[i] != NULL) {
498 dev_kfree_skb(bp->tx_bufs[i]);
499 bp->tx_bufs[i] = NULL;
500 }
501 }
502 }
503 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
504 return 0;
505 }
507 static int bmac_resume(struct macio_dev *mdev)
508 {
509 struct net_device* dev = macio_get_drvdata(mdev);
510 struct bmac_data *bp = netdev_priv(dev);
512 /* see if this is enough */
513 if (bp->opened)
514 bmac_reset_and_enable(dev);
516 enable_irq(dev->irq);
517 enable_irq(bp->tx_dma_intr);
518 enable_irq(bp->rx_dma_intr);
519 netif_device_attach(dev);
521 return 0;
522 }
523 #endif /* CONFIG_PM */
525 static int bmac_set_address(struct net_device *dev, void *addr)
526 {
527 struct bmac_data *bp = netdev_priv(dev);
528 unsigned char *p = addr;
529 unsigned short *pWord16;
530 unsigned long flags;
531 int i;
533 XXDEBUG(("bmac: enter set_address\n"));
534 spin_lock_irqsave(&bp->lock, flags);
536 for (i = 0; i < 6; ++i) {
537 dev->dev_addr[i] = p[i];
538 }
539 /* load up the hardware address */
540 pWord16 = (unsigned short *)dev->dev_addr;
541 bmwrite(dev, MADD0, *pWord16++);
542 bmwrite(dev, MADD1, *pWord16++);
543 bmwrite(dev, MADD2, *pWord16);
545 spin_unlock_irqrestore(&bp->lock, flags);
546 XXDEBUG(("bmac: exit set_address\n"));
547 return 0;
548 }
550 static inline void bmac_set_timeout(struct net_device *dev)
551 {
552 struct bmac_data *bp = netdev_priv(dev);
553 unsigned long flags;
555 spin_lock_irqsave(&bp->lock, flags);
556 if (bp->timeout_active)
557 del_timer(&bp->tx_timeout);
558 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
559 bp->tx_timeout.function = bmac_tx_timeout;
560 bp->tx_timeout.data = (unsigned long) dev;
561 add_timer(&bp->tx_timeout);
562 bp->timeout_active = 1;
563 spin_unlock_irqrestore(&bp->lock, flags);
564 }
566 static void
567 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
568 {
569 void *vaddr;
570 unsigned long baddr;
571 unsigned long len;
573 len = skb->len;
574 vaddr = skb->data;
575 baddr = virt_to_bus(vaddr);
577 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
578 }
580 static void
581 bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
582 {
583 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
585 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
586 virt_to_bus(addr), 0);
587 }
589 /* Bit-reverse one byte of an ethernet hardware address. */
590 static unsigned char
591 bitrev(unsigned char b)
592 {
593 int d = 0, i;
595 for (i = 0; i < 8; ++i, b >>= 1)
596 d = (d << 1) | (b & 1);
597 return d;
598 }
601 static void
602 bmac_init_tx_ring(struct bmac_data *bp)
603 {
604 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
606 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
608 bp->tx_empty = 0;
609 bp->tx_fill = 0;
610 bp->tx_fullup = 0;
612 /* put a branch at the end of the tx command list */
613 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
614 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
616 /* reset tx dma */
617 dbdma_reset(td);
618 out_le32(&td->wait_sel, 0x00200020);
619 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
620 }
622 static int
623 bmac_init_rx_ring(struct bmac_data *bp)
624 {
625 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
626 int i;
627 struct sk_buff *skb;
629 /* initialize list of sk_buffs for receiving and set up recv dma */
630 memset((char *)bp->rx_cmds, 0,
631 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
632 for (i = 0; i < N_RX_RING; i++) {
633 if ((skb = bp->rx_bufs[i]) == NULL) {
634 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
635 if (skb != NULL)
636 skb_reserve(skb, 2);
637 }
638 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
639 }
641 bp->rx_empty = 0;
642 bp->rx_fill = i;
644 /* Put a branch back to the beginning of the receive command list */
645 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
646 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
648 /* start rx dma */
649 dbdma_reset(rd);
650 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
652 return 1;
653 }
656 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
657 {
658 struct bmac_data *bp = netdev_priv(dev);
659 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
660 int i;
662 /* see if there's a free slot in the tx ring */
663 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
664 /* bp->tx_empty, bp->tx_fill)); */
665 i = bp->tx_fill + 1;
666 if (i >= N_TX_RING)
667 i = 0;
668 if (i == bp->tx_empty) {
669 netif_stop_queue(dev);
670 bp->tx_fullup = 1;
671 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
672 return -1; /* can't take it at the moment */
673 }
675 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
677 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
679 bp->tx_bufs[bp->tx_fill] = skb;
680 bp->tx_fill = i;
682 bp->stats.tx_bytes += skb->len;
684 dbdma_continue(td);
686 return 0;
687 }
689 static int rxintcount;
691 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
692 {
693 struct net_device *dev = (struct net_device *) dev_id;
694 struct bmac_data *bp = netdev_priv(dev);
695 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
696 volatile struct dbdma_cmd *cp;
697 int i, nb, stat;
698 struct sk_buff *skb;
699 unsigned int residual;
700 int last;
701 unsigned long flags;
703 spin_lock_irqsave(&bp->lock, flags);
705 if (++rxintcount < 10) {
706 XXDEBUG(("bmac_rxdma_intr\n"));
707 }
709 last = -1;
710 i = bp->rx_empty;
712 while (1) {
713 cp = &bp->rx_cmds[i];
714 stat = ld_le16(&cp->xfer_status);
715 residual = ld_le16(&cp->res_count);
716 if ((stat & ACTIVE) == 0)
717 break;
718 nb = RX_BUFLEN - residual - 2;
719 if (nb < (ETHERMINPACKET - ETHERCRC)) {
720 skb = NULL;
721 bp->stats.rx_length_errors++;
722 bp->stats.rx_errors++;
723 } else {
724 skb = bp->rx_bufs[i];
725 bp->rx_bufs[i] = NULL;
726 }
727 if (skb != NULL) {
728 nb -= ETHERCRC;
729 skb_put(skb, nb);
730 skb->dev = dev;
731 skb->protocol = eth_type_trans(skb, dev);
732 netif_rx(skb);
733 dev->last_rx = jiffies;
734 ++bp->stats.rx_packets;
735 bp->stats.rx_bytes += nb;
736 } else {
737 ++bp->stats.rx_dropped;
738 }
739 dev->last_rx = jiffies;
740 if ((skb = bp->rx_bufs[i]) == NULL) {
741 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
742 if (skb != NULL)
743 skb_reserve(bp->rx_bufs[i], 2);
744 }
745 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
746 st_le16(&cp->res_count, 0);
747 st_le16(&cp->xfer_status, 0);
748 last = i;
749 if (++i >= N_RX_RING) i = 0;
750 }
752 if (last != -1) {
753 bp->rx_fill = last;
754 bp->rx_empty = i;
755 }
757 dbdma_continue(rd);
758 spin_unlock_irqrestore(&bp->lock, flags);
760 if (rxintcount < 10) {
761 XXDEBUG(("bmac_rxdma_intr done\n"));
762 }
763 return IRQ_HANDLED;
764 }
766 static int txintcount;
768 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id, struct pt_regs *regs)
769 {
770 struct net_device *dev = (struct net_device *) dev_id;
771 struct bmac_data *bp = netdev_priv(dev);
772 volatile struct dbdma_cmd *cp;
773 int stat;
774 unsigned long flags;
776 spin_lock_irqsave(&bp->lock, flags);
778 if (txintcount++ < 10) {
779 XXDEBUG(("bmac_txdma_intr\n"));
780 }
782 /* del_timer(&bp->tx_timeout); */
783 /* bp->timeout_active = 0; */
785 while (1) {
786 cp = &bp->tx_cmds[bp->tx_empty];
787 stat = ld_le16(&cp->xfer_status);
788 if (txintcount < 10) {
789 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
790 }
791 if (!(stat & ACTIVE)) {
792 /*
793 * status field might not have been filled by DBDMA
794 */
795 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
796 break;
797 }
799 if (bp->tx_bufs[bp->tx_empty]) {
800 ++bp->stats.tx_packets;
801 dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
802 }
803 bp->tx_bufs[bp->tx_empty] = NULL;
804 bp->tx_fullup = 0;
805 netif_wake_queue(dev);
806 if (++bp->tx_empty >= N_TX_RING)
807 bp->tx_empty = 0;
808 if (bp->tx_empty == bp->tx_fill)
809 break;
810 }
812 spin_unlock_irqrestore(&bp->lock, flags);
814 if (txintcount < 10) {
815 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
816 }
818 bmac_start(dev);
819 return IRQ_HANDLED;
820 }
822 static struct net_device_stats *bmac_stats(struct net_device *dev)
823 {
824 struct bmac_data *p = netdev_priv(dev);
826 return &p->stats;
827 }
829 #ifndef SUNHME_MULTICAST
830 /* Real fast bit-reversal algorithm, 6-bit values */
831 static int reverse6[64] = {
832 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
833 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
834 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
835 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
836 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
837 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
838 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
839 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
840 };
842 static unsigned int
843 crc416(unsigned int curval, unsigned short nxtval)
844 {
845 register unsigned int counter, cur = curval, next = nxtval;
846 register int high_crc_set, low_data_set;
848 /* Swap bytes */
849 next = ((next & 0x00FF) << 8) | (next >> 8);
851 /* Compute bit-by-bit */
852 for (counter = 0; counter < 16; ++counter) {
853 /* is high CRC bit set? */
854 if ((cur & 0x80000000) == 0) high_crc_set = 0;
855 else high_crc_set = 1;
857 cur = cur << 1;
859 if ((next & 0x0001) == 0) low_data_set = 0;
860 else low_data_set = 1;
862 next = next >> 1;
864 /* do the XOR */
865 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
866 }
867 return cur;
868 }
870 static unsigned int
871 bmac_crc(unsigned short *address)
872 {
873 unsigned int newcrc;
875 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
876 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
877 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
878 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
880 return(newcrc);
881 }
883 /*
884 * Add requested mcast addr to BMac's hash table filter.
885 *
886 */
888 static void
889 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
890 {
891 unsigned int crc;
892 unsigned short mask;
894 if (!(*addr)) return;
895 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
896 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
897 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
898 mask = crc % 16;
899 mask = (unsigned char)1 << mask;
900 bp->hash_use_count[crc/16] |= mask;
901 }
903 static void
904 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
905 {
906 unsigned int crc;
907 unsigned char mask;
909 /* Now, delete the address from the filter copy, as indicated */
910 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
911 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
912 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
913 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
914 mask = crc % 16;
915 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
916 bp->hash_table_mask[crc/16] &= mask;
917 }
919 /*
920 * Sync the adapter with the software copy of the multicast mask
921 * (logical address filter).
922 */
924 static void
925 bmac_rx_off(struct net_device *dev)
926 {
927 unsigned short rx_cfg;
929 rx_cfg = bmread(dev, RXCFG);
930 rx_cfg &= ~RxMACEnable;
931 bmwrite(dev, RXCFG, rx_cfg);
932 do {
933 rx_cfg = bmread(dev, RXCFG);
934 } while (rx_cfg & RxMACEnable);
935 }
937 unsigned short
938 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
939 {
940 unsigned short rx_cfg;
942 rx_cfg = bmread(dev, RXCFG);
943 rx_cfg |= RxMACEnable;
944 if (hash_enable) rx_cfg |= RxHashFilterEnable;
945 else rx_cfg &= ~RxHashFilterEnable;
946 if (promisc_enable) rx_cfg |= RxPromiscEnable;
947 else rx_cfg &= ~RxPromiscEnable;
948 bmwrite(dev, RXRST, RxResetValue);
949 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
950 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
951 bmwrite(dev, RXCFG, rx_cfg );
952 return rx_cfg;
953 }
955 static void
956 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
957 {
958 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
959 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
960 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
961 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
962 }
964 #if 0
965 static void
966 bmac_add_multi(struct net_device *dev,
967 struct bmac_data *bp, unsigned char *addr)
968 {
969 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
970 bmac_addhash(bp, addr);
971 bmac_rx_off(dev);
972 bmac_update_hash_table_mask(dev, bp);
973 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
974 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
975 }
977 static void
978 bmac_remove_multi(struct net_device *dev,
979 struct bmac_data *bp, unsigned char *addr)
980 {
981 bmac_removehash(bp, addr);
982 bmac_rx_off(dev);
983 bmac_update_hash_table_mask(dev, bp);
984 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
985 }
986 #endif
988 /* Set or clear the multicast filter for this adaptor.
989 num_addrs == -1 Promiscuous mode, receive all packets
990 num_addrs == 0 Normal mode, clear multicast list
991 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
992 best-effort filtering.
993 */
994 static void bmac_set_multicast(struct net_device *dev)
995 {
996 struct dev_mc_list *dmi;
997 struct bmac_data *bp = netdev_priv(dev);
998 int num_addrs = dev->mc_count;
999 unsigned short rx_cfg;
1000 int i;
1002 if (bp->sleeping)
1003 return;
1005 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
1007 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1008 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
1009 bmac_update_hash_table_mask(dev, bp);
1010 rx_cfg = bmac_rx_on(dev, 1, 0);
1011 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
1012 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
1013 rx_cfg = bmread(dev, RXCFG);
1014 rx_cfg |= RxPromiscEnable;
1015 bmwrite(dev, RXCFG, rx_cfg);
1016 rx_cfg = bmac_rx_on(dev, 0, 1);
1017 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
1018 } else {
1019 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
1020 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
1021 if (num_addrs == 0) {
1022 rx_cfg = bmac_rx_on(dev, 0, 0);
1023 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
1024 } else {
1025 for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
1026 bmac_addhash(bp, dmi->dmi_addr);
1027 bmac_update_hash_table_mask(dev, bp);
1028 rx_cfg = bmac_rx_on(dev, 1, 0);
1029 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
1032 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1034 #else /* ifdef SUNHME_MULTICAST */
1036 /* The version of set_multicast below was lifted from sunhme.c */
1038 static void bmac_set_multicast(struct net_device *dev)
1040 struct dev_mc_list *dmi = dev->mc_list;
1041 char *addrs;
1042 int i;
1043 unsigned short rx_cfg;
1044 u32 crc;
1046 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1047 bmwrite(dev, BHASH0, 0xffff);
1048 bmwrite(dev, BHASH1, 0xffff);
1049 bmwrite(dev, BHASH2, 0xffff);
1050 bmwrite(dev, BHASH3, 0xffff);
1051 } else if(dev->flags & IFF_PROMISC) {
1052 rx_cfg = bmread(dev, RXCFG);
1053 rx_cfg |= RxPromiscEnable;
1054 bmwrite(dev, RXCFG, rx_cfg);
1055 } else {
1056 u16 hash_table[4];
1058 rx_cfg = bmread(dev, RXCFG);
1059 rx_cfg &= ~RxPromiscEnable;
1060 bmwrite(dev, RXCFG, rx_cfg);
1062 for(i = 0; i < 4; i++) hash_table[i] = 0;
1064 for(i = 0; i < dev->mc_count; i++) {
1065 addrs = dmi->dmi_addr;
1066 dmi = dmi->next;
1068 if(!(*addrs & 1))
1069 continue;
1071 crc = ether_crc_le(6, addrs);
1072 crc >>= 26;
1073 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1075 bmwrite(dev, BHASH0, hash_table[0]);
1076 bmwrite(dev, BHASH1, hash_table[1]);
1077 bmwrite(dev, BHASH2, hash_table[2]);
1078 bmwrite(dev, BHASH3, hash_table[3]);
1081 #endif /* SUNHME_MULTICAST */
1083 static int miscintcount;
1085 static irqreturn_t bmac_misc_intr(int irq, void *dev_id, struct pt_regs *regs)
1087 struct net_device *dev = (struct net_device *) dev_id;
1088 struct bmac_data *bp = netdev_priv(dev);
1089 unsigned int status = bmread(dev, STATUS);
1090 if (miscintcount++ < 10) {
1091 XXDEBUG(("bmac_misc_intr\n"));
1093 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1094 /* bmac_txdma_intr_inner(irq, dev_id, regs); */
1095 /* if (status & FrameReceived) bp->stats.rx_dropped++; */
1096 if (status & RxErrorMask) bp->stats.rx_errors++;
1097 if (status & RxCRCCntExp) bp->stats.rx_crc_errors++;
1098 if (status & RxLenCntExp) bp->stats.rx_length_errors++;
1099 if (status & RxOverFlow) bp->stats.rx_over_errors++;
1100 if (status & RxAlignCntExp) bp->stats.rx_frame_errors++;
1102 /* if (status & FrameSent) bp->stats.tx_dropped++; */
1103 if (status & TxErrorMask) bp->stats.tx_errors++;
1104 if (status & TxUnderrun) bp->stats.tx_fifo_errors++;
1105 if (status & TxNormalCollExp) bp->stats.collisions++;
1106 return IRQ_HANDLED;
1109 /*
1110 * Procedure for reading EEPROM
1111 */
1112 #define SROMAddressLength 5
1113 #define DataInOn 0x0008
1114 #define DataInOff 0x0000
1115 #define Clk 0x0002
1116 #define ChipSelect 0x0001
1117 #define SDIShiftCount 3
1118 #define SD0ShiftCount 2
1119 #define DelayValue 1000 /* number of microseconds */
1120 #define SROMStartOffset 10 /* this is in words */
1121 #define SROMReadCount 3 /* number of words to read from SROM */
1122 #define SROMAddressBits 6
1123 #define EnetAddressOffset 20
1125 static unsigned char
1126 bmac_clock_out_bit(struct net_device *dev)
1128 unsigned short data;
1129 unsigned short val;
1131 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1132 udelay(DelayValue);
1134 data = bmread(dev, SROMCSR);
1135 udelay(DelayValue);
1136 val = (data >> SD0ShiftCount) & 1;
1138 bmwrite(dev, SROMCSR, ChipSelect);
1139 udelay(DelayValue);
1141 return val;
1144 static void
1145 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1147 unsigned short data;
1149 if (val != 0 && val != 1) return;
1151 data = (val << SDIShiftCount);
1152 bmwrite(dev, SROMCSR, data | ChipSelect );
1153 udelay(DelayValue);
1155 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1156 udelay(DelayValue);
1158 bmwrite(dev, SROMCSR, data | ChipSelect);
1159 udelay(DelayValue);
1162 static void
1163 reset_and_select_srom(struct net_device *dev)
1165 /* first reset */
1166 bmwrite(dev, SROMCSR, 0);
1167 udelay(DelayValue);
1169 /* send it the read command (110) */
1170 bmac_clock_in_bit(dev, 1);
1171 bmac_clock_in_bit(dev, 1);
1172 bmac_clock_in_bit(dev, 0);
1175 static unsigned short
1176 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1178 unsigned short data, val;
1179 int i;
1181 /* send out the address we want to read from */
1182 for (i = 0; i < addr_len; i++) {
1183 val = addr >> (addr_len-i-1);
1184 bmac_clock_in_bit(dev, val & 1);
1187 /* Now read in the 16-bit data */
1188 data = 0;
1189 for (i = 0; i < 16; i++) {
1190 val = bmac_clock_out_bit(dev);
1191 data <<= 1;
1192 data |= val;
1194 bmwrite(dev, SROMCSR, 0);
1196 return data;
1199 /*
1200 * It looks like Cogent and SMC use different methods for calculating
1201 * checksums. What a pain..
1202 */
1204 static int
1205 bmac_verify_checksum(struct net_device *dev)
1207 unsigned short data, storedCS;
1209 reset_and_select_srom(dev);
1210 data = read_srom(dev, 3, SROMAddressBits);
1211 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1213 return 0;
1217 static void
1218 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1220 int i;
1221 unsigned short data;
1223 for (i = 0; i < 6; i++)
1225 reset_and_select_srom(dev);
1226 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1227 ea[2*i] = bitrev(data & 0x0ff);
1228 ea[2*i+1] = bitrev((data >> 8) & 0x0ff);
1232 static void bmac_reset_and_enable(struct net_device *dev)
1234 struct bmac_data *bp = netdev_priv(dev);
1235 unsigned long flags;
1236 struct sk_buff *skb;
1237 unsigned char *data;
1239 spin_lock_irqsave(&bp->lock, flags);
1240 bmac_enable_and_reset_chip(dev);
1241 bmac_init_tx_ring(bp);
1242 bmac_init_rx_ring(bp);
1243 bmac_init_chip(dev);
1244 bmac_start_chip(dev);
1245 bmwrite(dev, INTDISABLE, EnableNormal);
1246 bp->sleeping = 0;
1248 /*
1249 * It seems that the bmac can't receive until it's transmitted
1250 * a packet. So we give it a dummy packet to transmit.
1251 */
1252 skb = dev_alloc_skb(ETHERMINPACKET);
1253 if (skb != NULL) {
1254 data = skb_put(skb, ETHERMINPACKET);
1255 memset(data, 0, ETHERMINPACKET);
1256 memcpy(data, dev->dev_addr, 6);
1257 memcpy(data+6, dev->dev_addr, 6);
1258 bmac_transmit_packet(skb, dev);
1260 spin_unlock_irqrestore(&bp->lock, flags);
1263 static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1265 int j, rev, ret;
1266 struct bmac_data *bp;
1267 unsigned char *addr;
1268 struct net_device *dev;
1269 int is_bmac_plus = ((int)match->data) != 0;
1271 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1272 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1273 return -ENODEV;
1275 addr = get_property(macio_get_of_node(mdev), "mac-address", NULL);
1276 if (addr == NULL) {
1277 addr = get_property(macio_get_of_node(mdev), "local-mac-address", NULL);
1278 if (addr == NULL) {
1279 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1280 return -ENODEV;
1284 dev = alloc_etherdev(PRIV_BYTES);
1285 if (!dev) {
1286 printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
1287 return -ENOMEM;
1290 bp = netdev_priv(dev);
1291 SET_MODULE_OWNER(dev);
1292 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1293 macio_set_drvdata(mdev, dev);
1295 bp->mdev = mdev;
1296 spin_lock_init(&bp->lock);
1298 if (macio_request_resources(mdev, "bmac")) {
1299 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1300 goto out_free;
1303 dev->base_addr = (unsigned long)
1304 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1305 if (dev->base_addr == 0)
1306 goto out_release;
1308 dev->irq = macio_irq(mdev, 0);
1310 bmac_enable_and_reset_chip(dev);
1311 bmwrite(dev, INTDISABLE, DisableAll);
1313 rev = addr[0] == 0 && addr[1] == 0xA0;
1314 for (j = 0; j < 6; ++j)
1315 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
1317 /* Enable chip without interrupts for now */
1318 bmac_enable_and_reset_chip(dev);
1319 bmwrite(dev, INTDISABLE, DisableAll);
1321 dev->open = bmac_open;
1322 dev->stop = bmac_close;
1323 dev->hard_start_xmit = bmac_output;
1324 dev->get_stats = bmac_stats;
1325 dev->set_multicast_list = bmac_set_multicast;
1326 dev->set_mac_address = bmac_set_address;
1328 bmac_get_station_address(dev, addr);
1329 if (bmac_verify_checksum(dev) != 0)
1330 goto err_out_iounmap;
1332 bp->is_bmac_plus = is_bmac_plus;
1333 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1334 if (!bp->tx_dma)
1335 goto err_out_iounmap;
1336 bp->tx_dma_intr = macio_irq(mdev, 1);
1337 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1338 if (!bp->rx_dma)
1339 goto err_out_iounmap_tx;
1340 bp->rx_dma_intr = macio_irq(mdev, 2);
1342 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1343 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1345 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1346 skb_queue_head_init(bp->queue);
1348 init_timer(&bp->tx_timeout);
1350 ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
1351 if (ret) {
1352 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1353 goto err_out_iounmap_rx;
1355 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1356 if (ret) {
1357 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1358 goto err_out_irq0;
1360 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1361 if (ret) {
1362 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1363 goto err_out_irq1;
1366 /* Mask chip interrupts and disable chip, will be
1367 * re-enabled on open()
1368 */
1369 disable_irq(dev->irq);
1370 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1372 if (register_netdev(dev) != 0) {
1373 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1374 goto err_out_irq2;
1377 printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
1378 for (j = 0; j < 6; ++j)
1379 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
1380 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1381 printk("\n");
1383 return 0;
1385 err_out_irq2:
1386 free_irq(bp->rx_dma_intr, dev);
1387 err_out_irq1:
1388 free_irq(bp->tx_dma_intr, dev);
1389 err_out_irq0:
1390 free_irq(dev->irq, dev);
1391 err_out_iounmap_rx:
1392 iounmap(bp->rx_dma);
1393 err_out_iounmap_tx:
1394 iounmap(bp->tx_dma);
1395 err_out_iounmap:
1396 iounmap((void __iomem *)dev->base_addr);
1397 out_release:
1398 macio_release_resources(mdev);
1399 out_free:
1400 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1401 free_netdev(dev);
1403 return -ENODEV;
1406 static int bmac_open(struct net_device *dev)
1408 struct bmac_data *bp = netdev_priv(dev);
1409 /* XXDEBUG(("bmac: enter open\n")); */
1410 /* reset the chip */
1411 bp->opened = 1;
1412 bmac_reset_and_enable(dev);
1413 enable_irq(dev->irq);
1414 return 0;
1417 static int bmac_close(struct net_device *dev)
1419 struct bmac_data *bp = netdev_priv(dev);
1420 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1421 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1422 unsigned short config;
1423 int i;
1425 bp->sleeping = 1;
1427 /* disable rx and tx */
1428 config = bmread(dev, RXCFG);
1429 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1431 config = bmread(dev, TXCFG);
1432 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1434 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1436 /* disable rx and tx dma */
1437 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1438 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1440 /* free some skb's */
1441 XXDEBUG(("bmac: free rx bufs\n"));
1442 for (i=0; i<N_RX_RING; i++) {
1443 if (bp->rx_bufs[i] != NULL) {
1444 dev_kfree_skb(bp->rx_bufs[i]);
1445 bp->rx_bufs[i] = NULL;
1448 XXDEBUG(("bmac: free tx bufs\n"));
1449 for (i = 0; i<N_TX_RING; i++) {
1450 if (bp->tx_bufs[i] != NULL) {
1451 dev_kfree_skb(bp->tx_bufs[i]);
1452 bp->tx_bufs[i] = NULL;
1455 XXDEBUG(("bmac: all bufs freed\n"));
1457 bp->opened = 0;
1458 disable_irq(dev->irq);
1459 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1461 return 0;
1464 static void
1465 bmac_start(struct net_device *dev)
1467 struct bmac_data *bp = netdev_priv(dev);
1468 int i;
1469 struct sk_buff *skb;
1470 unsigned long flags;
1472 if (bp->sleeping)
1473 return;
1475 spin_lock_irqsave(&bp->lock, flags);
1476 while (1) {
1477 i = bp->tx_fill + 1;
1478 if (i >= N_TX_RING)
1479 i = 0;
1480 if (i == bp->tx_empty)
1481 break;
1482 skb = skb_dequeue(bp->queue);
1483 if (skb == NULL)
1484 break;
1485 bmac_transmit_packet(skb, dev);
1487 spin_unlock_irqrestore(&bp->lock, flags);
1490 static int
1491 bmac_output(struct sk_buff *skb, struct net_device *dev)
1493 struct bmac_data *bp = netdev_priv(dev);
1494 skb_queue_tail(bp->queue, skb);
1495 bmac_start(dev);
1496 return 0;
1499 static void bmac_tx_timeout(unsigned long data)
1501 struct net_device *dev = (struct net_device *) data;
1502 struct bmac_data *bp = netdev_priv(dev);
1503 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1504 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1505 volatile struct dbdma_cmd *cp;
1506 unsigned long flags;
1507 unsigned short config, oldConfig;
1508 int i;
1510 XXDEBUG(("bmac: tx_timeout called\n"));
1511 spin_lock_irqsave(&bp->lock, flags);
1512 bp->timeout_active = 0;
1514 /* update various counters */
1515 /* bmac_handle_misc_intrs(bp, 0); */
1517 cp = &bp->tx_cmds[bp->tx_empty];
1518 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1519 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1520 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1522 /* turn off both tx and rx and reset the chip */
1523 config = bmread(dev, RXCFG);
1524 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1525 config = bmread(dev, TXCFG);
1526 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1527 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1528 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1529 bmac_enable_and_reset_chip(dev);
1531 /* restart rx dma */
1532 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1533 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1534 out_le16(&cp->xfer_status, 0);
1535 out_le32(&rd->cmdptr, virt_to_bus(cp));
1536 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1538 /* fix up the transmit side */
1539 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1540 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1541 i = bp->tx_empty;
1542 ++bp->stats.tx_errors;
1543 if (i != bp->tx_fill) {
1544 dev_kfree_skb(bp->tx_bufs[i]);
1545 bp->tx_bufs[i] = NULL;
1546 if (++i >= N_TX_RING) i = 0;
1547 bp->tx_empty = i;
1549 bp->tx_fullup = 0;
1550 netif_wake_queue(dev);
1551 if (i != bp->tx_fill) {
1552 cp = &bp->tx_cmds[i];
1553 out_le16(&cp->xfer_status, 0);
1554 out_le16(&cp->command, OUTPUT_LAST);
1555 out_le32(&td->cmdptr, virt_to_bus(cp));
1556 out_le32(&td->control, DBDMA_SET(RUN));
1557 /* bmac_set_timeout(dev); */
1558 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1561 /* turn it back on */
1562 oldConfig = bmread(dev, RXCFG);
1563 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1564 oldConfig = bmread(dev, TXCFG);
1565 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1567 spin_unlock_irqrestore(&bp->lock, flags);
1570 #if 0
1571 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1573 int i,*ip;
1575 for (i=0;i< count;i++) {
1576 ip = (int*)(cp+i);
1578 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1579 ld_le32(ip+0),
1580 ld_le32(ip+1),
1581 ld_le32(ip+2),
1582 ld_le32(ip+3));
1586 #endif
1588 #if 0
1589 static int
1590 bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1592 int len = 0;
1593 off_t pos = 0;
1594 off_t begin = 0;
1595 int i;
1597 if (bmac_devs == NULL)
1598 return (-ENOSYS);
1600 len += sprintf(buffer, "BMAC counters & registers\n");
1602 for (i = 0; i<N_REG_ENTRIES; i++) {
1603 len += sprintf(buffer + len, "%s: %#08x\n",
1604 reg_entries[i].name,
1605 bmread(bmac_devs, reg_entries[i].reg_offset));
1606 pos = begin + len;
1608 if (pos < offset) {
1609 len = 0;
1610 begin = pos;
1613 if (pos > offset+length) break;
1616 *start = buffer + (offset - begin);
1617 len -= (offset - begin);
1619 if (len > length) len = length;
1621 return len;
1623 #endif
1625 static int __devexit bmac_remove(struct macio_dev *mdev)
1627 struct net_device *dev = macio_get_drvdata(mdev);
1628 struct bmac_data *bp = netdev_priv(dev);
1630 unregister_netdev(dev);
1632 free_irq(dev->irq, dev);
1633 free_irq(bp->tx_dma_intr, dev);
1634 free_irq(bp->rx_dma_intr, dev);
1636 iounmap((void __iomem *)dev->base_addr);
1637 iounmap(bp->tx_dma);
1638 iounmap(bp->rx_dma);
1640 macio_release_resources(mdev);
1642 free_netdev(dev);
1644 return 0;
1647 static struct of_device_id bmac_match[] =
1650 .name = "bmac",
1651 .data = (void *)0,
1652 },
1654 .type = "network",
1655 .compatible = "bmac+",
1656 .data = (void *)1,
1657 },
1658 {},
1659 };
1660 MODULE_DEVICE_TABLE (of, bmac_match);
1662 static struct macio_driver bmac_driver =
1664 .name = "bmac",
1665 .match_table = bmac_match,
1666 .probe = bmac_probe,
1667 .remove = bmac_remove,
1668 #ifdef CONFIG_PM
1669 .suspend = bmac_suspend,
1670 .resume = bmac_resume,
1671 #endif
1672 };
1675 static int __init bmac_init(void)
1677 if (bmac_emergency_rxbuf == NULL) {
1678 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1679 if (bmac_emergency_rxbuf == NULL) {
1680 printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
1681 return -ENOMEM;
1685 return macio_register_driver(&bmac_driver);
1688 static void __exit bmac_exit(void)
1690 macio_unregister_driver(&bmac_driver);
1692 kfree(bmac_emergency_rxbuf);
1693 bmac_emergency_rxbuf = NULL;
1696 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1697 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1698 MODULE_LICENSE("GPL");
1700 module_init(bmac_init);
1701 module_exit(bmac_exit);