ia64/linux-2.6.18-xen.hg

view drivers/net/au1000_eth.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
35 *
36 */
38 #include <linux/module.h>
39 #include <linux/kernel.h>
40 #include <linux/sched.h>
41 #include <linux/string.h>
42 #include <linux/timer.h>
43 #include <linux/errno.h>
44 #include <linux/in.h>
45 #include <linux/ioport.h>
46 #include <linux/bitops.h>
47 #include <linux/slab.h>
48 #include <linux/interrupt.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/netdevice.h>
52 #include <linux/etherdevice.h>
53 #include <linux/ethtool.h>
54 #include <linux/mii.h>
55 #include <linux/skbuff.h>
56 #include <linux/delay.h>
57 #include <linux/crc32.h>
58 #include <linux/phy.h>
59 #include <asm/mipsregs.h>
60 #include <asm/irq.h>
61 #include <asm/io.h>
62 #include <asm/processor.h>
64 #include <asm/mach-au1x00/au1000.h>
65 #include <asm/cpu.h>
66 #include "au1000_eth.h"
68 #ifdef AU1000_ETH_DEBUG
69 static int au1000_debug = 5;
70 #else
71 static int au1000_debug = 3;
72 #endif
74 #define DRV_NAME "au1000_eth"
75 #define DRV_VERSION "1.5"
76 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
77 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
79 MODULE_AUTHOR(DRV_AUTHOR);
80 MODULE_DESCRIPTION(DRV_DESC);
81 MODULE_LICENSE("GPL");
83 // prototypes
84 static void hard_stop(struct net_device *);
85 static void enable_rx_tx(struct net_device *dev);
86 static struct net_device * au1000_probe(int port_num);
87 static int au1000_init(struct net_device *);
88 static int au1000_open(struct net_device *);
89 static int au1000_close(struct net_device *);
90 static int au1000_tx(struct sk_buff *, struct net_device *);
91 static int au1000_rx(struct net_device *);
92 static irqreturn_t au1000_interrupt(int, void *, struct pt_regs *);
93 static void au1000_tx_timeout(struct net_device *);
94 static void set_rx_mode(struct net_device *);
95 static struct net_device_stats *au1000_get_stats(struct net_device *);
96 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
97 static int mdio_read(struct net_device *, int, int);
98 static void mdio_write(struct net_device *, int, int, u16);
99 static void au1000_adjust_link(struct net_device *);
100 static void enable_mac(struct net_device *, int);
102 // externs
103 extern int get_ethernet_addr(char *ethernet_addr);
104 extern void str2eaddr(unsigned char *ea, unsigned char *str);
105 extern char * __init prom_getcmdline(void);
107 /*
108 * Theory of operation
109 *
110 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
111 * There are four receive and four transmit descriptors. These
112 * descriptors are not in memory; rather, they are just a set of
113 * hardware registers.
114 *
115 * Since the Au1000 has a coherent data cache, the receive and
116 * transmit buffers are allocated from the KSEG0 segment. The
117 * hardware registers, however, are still mapped at KSEG1 to
118 * make sure there's no out-of-order writes, and that all writes
119 * complete immediately.
120 */
122 /* These addresses are only used if yamon doesn't tell us what
123 * the mac address is, and the mac address is not passed on the
124 * command line.
125 */
126 static unsigned char au1000_mac_addr[6] __devinitdata = {
127 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
128 };
130 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
132 /*
133 * board-specific configurations
134 *
135 * PHY detection algorithm
136 *
137 * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is
138 * autodetected:
139 *
140 * mii_probe() first searches the current MAC's MII bus for a PHY,
141 * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is
142 * defined) PHY address not already claimed by another netdev.
143 *
144 * If nothing was found that way when searching for the 2nd ethernet
145 * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then
146 * the first MII bus is searched as well for an unclaimed PHY; this is
147 * needed in case of a dual-PHY accessible only through the MAC0's MII
148 * bus.
149 *
150 * Finally, if no PHY is found, then the corresponding ethernet
151 * controller is not registered to the network subsystem.
152 */
154 /* autodetection defaults */
155 #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR
156 #define AU1XXX_PHY1_SEARCH_ON_MAC0
158 /* static PHY setup
159 *
160 * most boards PHY setup should be detectable properly with the
161 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
162 * you have a switch attached, or want to use the PHY's interrupt
163 * notification capabilities) you can provide a static PHY
164 * configuration here
165 *
166 * IRQs may only be set, if a PHY address was configured
167 * If a PHY address is given, also a bus id is required to be set
168 *
169 * ps: make sure the used irqs are configured properly in the board
170 * specific irq-map
171 */
173 #if defined(CONFIG_MIPS_BOSPORUS)
174 /*
175 * Micrel/Kendin 5 port switch attached to MAC0,
176 * MAC0 is associated with PHY address 5 (== WAN port)
177 * MAC1 is not associated with any PHY, since it's connected directly
178 * to the switch.
179 * no interrupts are used
180 */
181 # define AU1XXX_PHY_STATIC_CONFIG
183 # define AU1XXX_PHY0_ADDR 5
184 # define AU1XXX_PHY0_BUSID 0
185 # undef AU1XXX_PHY0_IRQ
187 # undef AU1XXX_PHY1_ADDR
188 # undef AU1XXX_PHY1_BUSID
189 # undef AU1XXX_PHY1_IRQ
190 #endif
192 #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
193 # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
194 #endif
196 /*
197 * MII operations
198 */
199 static int mdio_read(struct net_device *dev, int phy_addr, int reg)
200 {
201 struct au1000_private *aup = (struct au1000_private *) dev->priv;
202 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
203 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
204 u32 timedout = 20;
205 u32 mii_control;
207 while (*mii_control_reg & MAC_MII_BUSY) {
208 mdelay(1);
209 if (--timedout == 0) {
210 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
211 dev->name);
212 return -1;
213 }
214 }
216 mii_control = MAC_SET_MII_SELECT_REG(reg) |
217 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
219 *mii_control_reg = mii_control;
221 timedout = 20;
222 while (*mii_control_reg & MAC_MII_BUSY) {
223 mdelay(1);
224 if (--timedout == 0) {
225 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
226 dev->name);
227 return -1;
228 }
229 }
230 return (int)*mii_data_reg;
231 }
233 static void mdio_write(struct net_device *dev, int phy_addr, int reg, u16 value)
234 {
235 struct au1000_private *aup = (struct au1000_private *) dev->priv;
236 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
237 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
238 u32 timedout = 20;
239 u32 mii_control;
241 while (*mii_control_reg & MAC_MII_BUSY) {
242 mdelay(1);
243 if (--timedout == 0) {
244 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
245 dev->name);
246 return;
247 }
248 }
250 mii_control = MAC_SET_MII_SELECT_REG(reg) |
251 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
253 *mii_data_reg = value;
254 *mii_control_reg = mii_control;
255 }
257 static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
258 {
259 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
260 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
261 struct net_device *const dev = bus->priv;
263 enable_mac(dev, 0); /* make sure the MAC associated with this
264 * mii_bus is enabled */
265 return mdio_read(dev, phy_addr, regnum);
266 }
268 static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
269 u16 value)
270 {
271 struct net_device *const dev = bus->priv;
273 enable_mac(dev, 0); /* make sure the MAC associated with this
274 * mii_bus is enabled */
275 mdio_write(dev, phy_addr, regnum, value);
276 return 0;
277 }
279 static int mdiobus_reset(struct mii_bus *bus)
280 {
281 struct net_device *const dev = bus->priv;
283 enable_mac(dev, 0); /* make sure the MAC associated with this
284 * mii_bus is enabled */
285 return 0;
286 }
288 static int mii_probe (struct net_device *dev)
289 {
290 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
291 struct phy_device *phydev = NULL;
293 #if defined(AU1XXX_PHY_STATIC_CONFIG)
294 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
296 if(aup->mac_id == 0) { /* get PHY0 */
297 # if defined(AU1XXX_PHY0_ADDR)
298 phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus.phy_map[AU1XXX_PHY0_ADDR];
299 # else
300 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
301 dev->name);
302 return 0;
303 # endif /* defined(AU1XXX_PHY0_ADDR) */
304 } else if (aup->mac_id == 1) { /* get PHY1 */
305 # if defined(AU1XXX_PHY1_ADDR)
306 phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus.phy_map[AU1XXX_PHY1_ADDR];
307 # else
308 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
309 dev->name);
310 return 0;
311 # endif /* defined(AU1XXX_PHY1_ADDR) */
312 }
314 #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */
315 int phy_addr;
317 /* find the first (lowest address) PHY on the current MAC's MII bus */
318 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
319 if (aup->mii_bus.phy_map[phy_addr]) {
320 phydev = aup->mii_bus.phy_map[phy_addr];
321 # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR)
322 break; /* break out with first one found */
323 # endif
324 }
326 # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0)
327 /* try harder to find a PHY */
328 if (!phydev && (aup->mac_id == 1)) {
329 /* no PHY found, maybe we have a dual PHY? */
330 printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
331 "let's see if it's attached to MAC0...\n");
333 BUG_ON(!au_macs[0]);
335 /* find the first (lowest address) non-attached PHY on
336 * the MAC0 MII bus */
337 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
338 struct phy_device *const tmp_phydev =
339 au_macs[0]->mii_bus.phy_map[phy_addr];
341 if (!tmp_phydev)
342 continue; /* no PHY here... */
344 if (tmp_phydev->attached_dev)
345 continue; /* already claimed by MAC0 */
347 phydev = tmp_phydev;
348 break; /* found it */
349 }
350 }
351 # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */
353 #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */
354 if (!phydev) {
355 printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
356 return -1;
357 }
359 /* now we are supposed to have a proper phydev, to attach to... */
360 BUG_ON(!phydev);
361 BUG_ON(phydev->attached_dev);
363 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0);
365 if (IS_ERR(phydev)) {
366 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
367 return PTR_ERR(phydev);
368 }
370 /* mask with MAC supported features */
371 phydev->supported &= (SUPPORTED_10baseT_Half
372 | SUPPORTED_10baseT_Full
373 | SUPPORTED_100baseT_Half
374 | SUPPORTED_100baseT_Full
375 | SUPPORTED_Autoneg
376 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
377 | SUPPORTED_MII
378 | SUPPORTED_TP);
380 phydev->advertising = phydev->supported;
382 aup->old_link = 0;
383 aup->old_speed = 0;
384 aup->old_duplex = -1;
385 aup->phy_dev = phydev;
387 printk(KERN_INFO "%s: attached PHY driver [%s] "
388 "(mii_bus:phy_addr=%s, irq=%d)\n",
389 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
391 return 0;
392 }
395 /*
396 * Buffer allocation/deallocation routines. The buffer descriptor returned
397 * has the virtual and dma address of a buffer suitable for
398 * both, receive and transmit operations.
399 */
400 static db_dest_t *GetFreeDB(struct au1000_private *aup)
401 {
402 db_dest_t *pDB;
403 pDB = aup->pDBfree;
405 if (pDB) {
406 aup->pDBfree = pDB->pnext;
407 }
408 return pDB;
409 }
411 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
412 {
413 db_dest_t *pDBfree = aup->pDBfree;
414 if (pDBfree)
415 pDBfree->pnext = pDB;
416 aup->pDBfree = pDB;
417 }
419 static void enable_rx_tx(struct net_device *dev)
420 {
421 struct au1000_private *aup = (struct au1000_private *) dev->priv;
423 if (au1000_debug > 4)
424 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
426 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
427 au_sync_delay(10);
428 }
430 static void hard_stop(struct net_device *dev)
431 {
432 struct au1000_private *aup = (struct au1000_private *) dev->priv;
434 if (au1000_debug > 4)
435 printk(KERN_INFO "%s: hard stop\n", dev->name);
437 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
438 au_sync_delay(10);
439 }
441 static void enable_mac(struct net_device *dev, int force_reset)
442 {
443 unsigned long flags;
444 struct au1000_private *aup = (struct au1000_private *) dev->priv;
446 spin_lock_irqsave(&aup->lock, flags);
448 if(force_reset || (!aup->mac_enabled)) {
449 *aup->enable = MAC_EN_CLOCK_ENABLE;
450 au_sync_delay(2);
451 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
452 | MAC_EN_CLOCK_ENABLE);
453 au_sync_delay(2);
455 aup->mac_enabled = 1;
456 }
458 spin_unlock_irqrestore(&aup->lock, flags);
459 }
461 static void reset_mac_unlocked(struct net_device *dev)
462 {
463 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
464 int i;
466 hard_stop(dev);
468 *aup->enable = MAC_EN_CLOCK_ENABLE;
469 au_sync_delay(2);
470 *aup->enable = 0;
471 au_sync_delay(2);
473 aup->tx_full = 0;
474 for (i = 0; i < NUM_RX_DMA; i++) {
475 /* reset control bits */
476 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
477 }
478 for (i = 0; i < NUM_TX_DMA; i++) {
479 /* reset control bits */
480 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
481 }
483 aup->mac_enabled = 0;
485 }
487 static void reset_mac(struct net_device *dev)
488 {
489 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
490 unsigned long flags;
492 if (au1000_debug > 4)
493 printk(KERN_INFO "%s: reset mac, aup %x\n",
494 dev->name, (unsigned)aup);
496 spin_lock_irqsave(&aup->lock, flags);
498 reset_mac_unlocked (dev);
500 spin_unlock_irqrestore(&aup->lock, flags);
501 }
503 /*
504 * Setup the receive and transmit "rings". These pointers are the addresses
505 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
506 * these are not descriptors sitting in memory.
507 */
508 static void
509 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
510 {
511 int i;
513 for (i = 0; i < NUM_RX_DMA; i++) {
514 aup->rx_dma_ring[i] =
515 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
516 }
517 for (i = 0; i < NUM_TX_DMA; i++) {
518 aup->tx_dma_ring[i] =
519 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
520 }
521 }
523 static struct {
524 u32 base_addr;
525 u32 macen_addr;
526 int irq;
527 struct net_device *dev;
528 } iflist[2] = {
529 #ifdef CONFIG_SOC_AU1000
530 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
531 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
532 #endif
533 #ifdef CONFIG_SOC_AU1100
534 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
535 #endif
536 #ifdef CONFIG_SOC_AU1500
537 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
538 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
539 #endif
540 #ifdef CONFIG_SOC_AU1550
541 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
542 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
543 #endif
544 };
546 static int num_ifs;
548 /*
549 * Setup the base address and interupt of the Au1xxx ethernet macs
550 * based on cpu type and whether the interface is enabled in sys_pinfunc
551 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
552 */
553 static int __init au1000_init_module(void)
554 {
555 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
556 struct net_device *dev;
557 int i, found_one = 0;
559 num_ifs = NUM_ETH_INTERFACES - ni;
561 for(i = 0; i < num_ifs; i++) {
562 dev = au1000_probe(i);
563 iflist[i].dev = dev;
564 if (dev)
565 found_one++;
566 }
567 if (!found_one)
568 return -ENODEV;
569 return 0;
570 }
572 /*
573 * ethtool operations
574 */
576 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
577 {
578 struct au1000_private *aup = (struct au1000_private *)dev->priv;
580 if (aup->phy_dev)
581 return phy_ethtool_gset(aup->phy_dev, cmd);
583 return -EINVAL;
584 }
586 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
587 {
588 struct au1000_private *aup = (struct au1000_private *)dev->priv;
590 if (!capable(CAP_NET_ADMIN))
591 return -EPERM;
593 if (aup->phy_dev)
594 return phy_ethtool_sset(aup->phy_dev, cmd);
596 return -EINVAL;
597 }
599 static void
600 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
601 {
602 struct au1000_private *aup = (struct au1000_private *)dev->priv;
604 strcpy(info->driver, DRV_NAME);
605 strcpy(info->version, DRV_VERSION);
606 info->fw_version[0] = '\0';
607 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
608 info->regdump_len = 0;
609 }
611 static struct ethtool_ops au1000_ethtool_ops = {
612 .get_settings = au1000_get_settings,
613 .set_settings = au1000_set_settings,
614 .get_drvinfo = au1000_get_drvinfo,
615 .get_link = ethtool_op_get_link,
616 };
618 static struct net_device * au1000_probe(int port_num)
619 {
620 static unsigned version_printed = 0;
621 struct au1000_private *aup = NULL;
622 struct net_device *dev = NULL;
623 db_dest_t *pDB, *pDBfree;
624 char *pmac, *argptr;
625 char ethaddr[6];
626 int irq, i, err;
627 u32 base, macen;
629 if (port_num >= NUM_ETH_INTERFACES)
630 return NULL;
632 base = CPHYSADDR(iflist[port_num].base_addr );
633 macen = CPHYSADDR(iflist[port_num].macen_addr);
634 irq = iflist[port_num].irq;
636 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
637 !request_mem_region(macen, 4, "Au1x00 ENET"))
638 return NULL;
640 if (version_printed++ == 0)
641 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
643 dev = alloc_etherdev(sizeof(struct au1000_private));
644 if (!dev) {
645 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
646 return NULL;
647 }
649 if ((err = register_netdev(dev)) != 0) {
650 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
651 DRV_NAME, err);
652 free_netdev(dev);
653 return NULL;
654 }
656 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
657 dev->name, base, irq);
659 aup = dev->priv;
661 /* Allocate the data buffers */
662 /* Snooping works fine with eth on all au1xxx */
663 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
664 (NUM_TX_BUFFS + NUM_RX_BUFFS),
665 &aup->dma_addr, 0);
666 if (!aup->vaddr) {
667 free_netdev(dev);
668 release_mem_region( base, MAC_IOSIZE);
669 release_mem_region(macen, 4);
670 return NULL;
671 }
673 /* aup->mac is the base address of the MAC's registers */
674 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
676 /* Setup some variables for quick register address access */
677 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
678 aup->mac_id = port_num;
679 au_macs[port_num] = aup;
681 if (port_num == 0) {
682 /* Check the environment variables first */
683 if (get_ethernet_addr(ethaddr) == 0)
684 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
685 else {
686 /* Check command line */
687 argptr = prom_getcmdline();
688 if ((pmac = strstr(argptr, "ethaddr=")) == NULL)
689 printk(KERN_INFO "%s: No MAC address found\n",
690 dev->name);
691 /* Use the hard coded MAC addresses */
692 else {
693 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
694 memcpy(au1000_mac_addr, ethaddr,
695 sizeof(au1000_mac_addr));
696 }
697 }
699 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
700 } else if (port_num == 1)
701 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
703 /*
704 * Assign to the Ethernet ports two consecutive MAC addresses
705 * to match those that are printed on their stickers
706 */
707 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
708 dev->dev_addr[5] += port_num;
710 *aup->enable = 0;
711 aup->mac_enabled = 0;
713 aup->mii_bus.priv = dev;
714 aup->mii_bus.read = mdiobus_read;
715 aup->mii_bus.write = mdiobus_write;
716 aup->mii_bus.reset = mdiobus_reset;
717 aup->mii_bus.name = "au1000_eth_mii";
718 aup->mii_bus.id = aup->mac_id;
719 aup->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
720 for(i = 0; i < PHY_MAX_ADDR; ++i)
721 aup->mii_bus.irq[i] = PHY_POLL;
723 /* if known, set corresponding PHY IRQs */
724 #if defined(AU1XXX_PHY_STATIC_CONFIG)
725 # if defined(AU1XXX_PHY0_IRQ)
726 if (AU1XXX_PHY0_BUSID == aup->mii_bus.id)
727 aup->mii_bus.irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
728 # endif
729 # if defined(AU1XXX_PHY1_IRQ)
730 if (AU1XXX_PHY1_BUSID == aup->mii_bus.id)
731 aup->mii_bus.irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
732 # endif
733 #endif
734 mdiobus_register(&aup->mii_bus);
736 if (mii_probe(dev) != 0) {
737 goto err_out;
738 }
740 pDBfree = NULL;
741 /* setup the data buffer descriptors and attach a buffer to each one */
742 pDB = aup->db;
743 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
744 pDB->pnext = pDBfree;
745 pDBfree = pDB;
746 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
747 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
748 pDB++;
749 }
750 aup->pDBfree = pDBfree;
752 for (i = 0; i < NUM_RX_DMA; i++) {
753 pDB = GetFreeDB(aup);
754 if (!pDB) {
755 goto err_out;
756 }
757 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
758 aup->rx_db_inuse[i] = pDB;
759 }
760 for (i = 0; i < NUM_TX_DMA; i++) {
761 pDB = GetFreeDB(aup);
762 if (!pDB) {
763 goto err_out;
764 }
765 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
766 aup->tx_dma_ring[i]->len = 0;
767 aup->tx_db_inuse[i] = pDB;
768 }
770 spin_lock_init(&aup->lock);
771 dev->base_addr = base;
772 dev->irq = irq;
773 dev->open = au1000_open;
774 dev->hard_start_xmit = au1000_tx;
775 dev->stop = au1000_close;
776 dev->get_stats = au1000_get_stats;
777 dev->set_multicast_list = &set_rx_mode;
778 dev->do_ioctl = &au1000_ioctl;
779 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
780 dev->tx_timeout = au1000_tx_timeout;
781 dev->watchdog_timeo = ETH_TX_TIMEOUT;
783 /*
784 * The boot code uses the ethernet controller, so reset it to start
785 * fresh. au1000_init() expects that the device is in reset state.
786 */
787 reset_mac(dev);
789 return dev;
791 err_out:
792 /* here we should have a valid dev plus aup-> register addresses
793 * so we can reset the mac properly.*/
794 reset_mac(dev);
796 for (i = 0; i < NUM_RX_DMA; i++) {
797 if (aup->rx_db_inuse[i])
798 ReleaseDB(aup, aup->rx_db_inuse[i]);
799 }
800 for (i = 0; i < NUM_TX_DMA; i++) {
801 if (aup->tx_db_inuse[i])
802 ReleaseDB(aup, aup->tx_db_inuse[i]);
803 }
804 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
805 (void *)aup->vaddr, aup->dma_addr);
806 unregister_netdev(dev);
807 free_netdev(dev);
808 release_mem_region( base, MAC_IOSIZE);
809 release_mem_region(macen, 4);
810 return NULL;
811 }
813 /*
814 * Initialize the interface.
815 *
816 * When the device powers up, the clocks are disabled and the
817 * mac is in reset state. When the interface is closed, we
818 * do the same -- reset the device and disable the clocks to
819 * conserve power. Thus, whenever au1000_init() is called,
820 * the device should already be in reset state.
821 */
822 static int au1000_init(struct net_device *dev)
823 {
824 struct au1000_private *aup = (struct au1000_private *) dev->priv;
825 u32 flags;
826 int i;
827 u32 control;
829 if (au1000_debug > 4)
830 printk("%s: au1000_init\n", dev->name);
832 /* bring the device out of reset */
833 enable_mac(dev, 1);
835 spin_lock_irqsave(&aup->lock, flags);
837 aup->mac->control = 0;
838 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
839 aup->tx_tail = aup->tx_head;
840 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
842 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
843 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
844 dev->dev_addr[1]<<8 | dev->dev_addr[0];
846 for (i = 0; i < NUM_RX_DMA; i++) {
847 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
848 }
849 au_sync();
851 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
852 #ifndef CONFIG_CPU_LITTLE_ENDIAN
853 control |= MAC_BIG_ENDIAN;
854 #endif
855 if (aup->phy_dev) {
856 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
857 control |= MAC_FULL_DUPLEX;
858 else
859 control |= MAC_DISABLE_RX_OWN;
860 } else { /* PHY-less op, assume full-duplex */
861 control |= MAC_FULL_DUPLEX;
862 }
864 aup->mac->control = control;
865 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
866 au_sync();
868 spin_unlock_irqrestore(&aup->lock, flags);
869 return 0;
870 }
872 static void
873 au1000_adjust_link(struct net_device *dev)
874 {
875 struct au1000_private *aup = (struct au1000_private *) dev->priv;
876 struct phy_device *phydev = aup->phy_dev;
877 unsigned long flags;
879 int status_change = 0;
881 BUG_ON(!aup->phy_dev);
883 spin_lock_irqsave(&aup->lock, flags);
885 if (phydev->link && (aup->old_speed != phydev->speed)) {
886 // speed changed
888 switch(phydev->speed) {
889 case SPEED_10:
890 case SPEED_100:
891 break;
892 default:
893 printk(KERN_WARNING
894 "%s: Speed (%d) is not 10/100 ???\n",
895 dev->name, phydev->speed);
896 break;
897 }
899 aup->old_speed = phydev->speed;
901 status_change = 1;
902 }
904 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
905 // duplex mode changed
907 /* switching duplex mode requires to disable rx and tx! */
908 hard_stop(dev);
910 if (DUPLEX_FULL == phydev->duplex)
911 aup->mac->control = ((aup->mac->control
912 | MAC_FULL_DUPLEX)
913 & ~MAC_DISABLE_RX_OWN);
914 else
915 aup->mac->control = ((aup->mac->control
916 & ~MAC_FULL_DUPLEX)
917 | MAC_DISABLE_RX_OWN);
918 au_sync_delay(1);
920 enable_rx_tx(dev);
921 aup->old_duplex = phydev->duplex;
923 status_change = 1;
924 }
926 if(phydev->link != aup->old_link) {
927 // link state changed
929 if (phydev->link) // link went up
930 netif_schedule(dev);
931 else { // link went down
932 aup->old_speed = 0;
933 aup->old_duplex = -1;
934 }
936 aup->old_link = phydev->link;
937 status_change = 1;
938 }
940 spin_unlock_irqrestore(&aup->lock, flags);
942 if (status_change) {
943 if (phydev->link)
944 printk(KERN_INFO "%s: link up (%d/%s)\n",
945 dev->name, phydev->speed,
946 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
947 else
948 printk(KERN_INFO "%s: link down\n", dev->name);
949 }
950 }
952 static int au1000_open(struct net_device *dev)
953 {
954 int retval;
955 struct au1000_private *aup = (struct au1000_private *) dev->priv;
957 if (au1000_debug > 4)
958 printk("%s: open: dev=%p\n", dev->name, dev);
960 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
961 dev->name, dev))) {
962 printk(KERN_ERR "%s: unable to get IRQ %d\n",
963 dev->name, dev->irq);
964 return retval;
965 }
967 if ((retval = au1000_init(dev))) {
968 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
969 free_irq(dev->irq, dev);
970 return retval;
971 }
973 if (aup->phy_dev) {
974 /* cause the PHY state machine to schedule a link state check */
975 aup->phy_dev->state = PHY_CHANGELINK;
976 phy_start(aup->phy_dev);
977 }
979 netif_start_queue(dev);
981 if (au1000_debug > 4)
982 printk("%s: open: Initialization done.\n", dev->name);
984 return 0;
985 }
987 static int au1000_close(struct net_device *dev)
988 {
989 unsigned long flags;
990 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
992 if (au1000_debug > 4)
993 printk("%s: close: dev=%p\n", dev->name, dev);
995 if (aup->phy_dev)
996 phy_stop(aup->phy_dev);
998 spin_lock_irqsave(&aup->lock, flags);
1000 reset_mac_unlocked (dev);
1002 /* stop the device */
1003 netif_stop_queue(dev);
1005 /* disable the interrupt */
1006 free_irq(dev->irq, dev);
1007 spin_unlock_irqrestore(&aup->lock, flags);
1009 return 0;
1012 static void __exit au1000_cleanup_module(void)
1014 int i, j;
1015 struct net_device *dev;
1016 struct au1000_private *aup;
1018 for (i = 0; i < num_ifs; i++) {
1019 dev = iflist[i].dev;
1020 if (dev) {
1021 aup = (struct au1000_private *) dev->priv;
1022 unregister_netdev(dev);
1023 for (j = 0; j < NUM_RX_DMA; j++)
1024 if (aup->rx_db_inuse[j])
1025 ReleaseDB(aup, aup->rx_db_inuse[j]);
1026 for (j = 0; j < NUM_TX_DMA; j++)
1027 if (aup->tx_db_inuse[j])
1028 ReleaseDB(aup, aup->tx_db_inuse[j]);
1029 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1030 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1031 (void *)aup->vaddr, aup->dma_addr);
1032 release_mem_region(dev->base_addr, MAC_IOSIZE);
1033 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1034 free_netdev(dev);
1039 static void update_tx_stats(struct net_device *dev, u32 status)
1041 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1042 struct net_device_stats *ps = &aup->stats;
1044 if (status & TX_FRAME_ABORTED) {
1045 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
1046 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1047 /* any other tx errors are only valid
1048 * in half duplex mode */
1049 ps->tx_errors++;
1050 ps->tx_aborted_errors++;
1053 else {
1054 ps->tx_errors++;
1055 ps->tx_aborted_errors++;
1056 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1057 ps->tx_carrier_errors++;
1063 /*
1064 * Called from the interrupt service routine to acknowledge
1065 * the TX DONE bits. This is a must if the irq is setup as
1066 * edge triggered.
1067 */
1068 static void au1000_tx_ack(struct net_device *dev)
1070 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1071 volatile tx_dma_t *ptxd;
1073 ptxd = aup->tx_dma_ring[aup->tx_tail];
1075 while (ptxd->buff_stat & TX_T_DONE) {
1076 update_tx_stats(dev, ptxd->status);
1077 ptxd->buff_stat &= ~TX_T_DONE;
1078 ptxd->len = 0;
1079 au_sync();
1081 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1082 ptxd = aup->tx_dma_ring[aup->tx_tail];
1084 if (aup->tx_full) {
1085 aup->tx_full = 0;
1086 netif_wake_queue(dev);
1092 /*
1093 * Au1000 transmit routine.
1094 */
1095 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1097 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1098 struct net_device_stats *ps = &aup->stats;
1099 volatile tx_dma_t *ptxd;
1100 u32 buff_stat;
1101 db_dest_t *pDB;
1102 int i;
1104 if (au1000_debug > 5)
1105 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1106 dev->name, (unsigned)aup, skb->len,
1107 skb->data, aup->tx_head);
1109 ptxd = aup->tx_dma_ring[aup->tx_head];
1110 buff_stat = ptxd->buff_stat;
1111 if (buff_stat & TX_DMA_ENABLE) {
1112 /* We've wrapped around and the transmitter is still busy */
1113 netif_stop_queue(dev);
1114 aup->tx_full = 1;
1115 return 1;
1117 else if (buff_stat & TX_T_DONE) {
1118 update_tx_stats(dev, ptxd->status);
1119 ptxd->len = 0;
1122 if (aup->tx_full) {
1123 aup->tx_full = 0;
1124 netif_wake_queue(dev);
1127 pDB = aup->tx_db_inuse[aup->tx_head];
1128 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1129 if (skb->len < ETH_ZLEN) {
1130 for (i=skb->len; i<ETH_ZLEN; i++) {
1131 ((char *)pDB->vaddr)[i] = 0;
1133 ptxd->len = ETH_ZLEN;
1135 else
1136 ptxd->len = skb->len;
1138 ps->tx_packets++;
1139 ps->tx_bytes += ptxd->len;
1141 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1142 au_sync();
1143 dev_kfree_skb(skb);
1144 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1145 dev->trans_start = jiffies;
1146 return 0;
1149 static inline void update_rx_stats(struct net_device *dev, u32 status)
1151 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1152 struct net_device_stats *ps = &aup->stats;
1154 ps->rx_packets++;
1155 if (status & RX_MCAST_FRAME)
1156 ps->multicast++;
1158 if (status & RX_ERROR) {
1159 ps->rx_errors++;
1160 if (status & RX_MISSED_FRAME)
1161 ps->rx_missed_errors++;
1162 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1163 ps->rx_length_errors++;
1164 if (status & RX_CRC_ERROR)
1165 ps->rx_crc_errors++;
1166 if (status & RX_COLL)
1167 ps->collisions++;
1169 else
1170 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1174 /*
1175 * Au1000 receive routine.
1176 */
1177 static int au1000_rx(struct net_device *dev)
1179 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1180 struct sk_buff *skb;
1181 volatile rx_dma_t *prxd;
1182 u32 buff_stat, status;
1183 db_dest_t *pDB;
1184 u32 frmlen;
1186 if (au1000_debug > 5)
1187 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1189 prxd = aup->rx_dma_ring[aup->rx_head];
1190 buff_stat = prxd->buff_stat;
1191 while (buff_stat & RX_T_DONE) {
1192 status = prxd->status;
1193 pDB = aup->rx_db_inuse[aup->rx_head];
1194 update_rx_stats(dev, status);
1195 if (!(status & RX_ERROR)) {
1197 /* good frame */
1198 frmlen = (status & RX_FRAME_LEN_MASK);
1199 frmlen -= 4; /* Remove FCS */
1200 skb = dev_alloc_skb(frmlen + 2);
1201 if (skb == NULL) {
1202 printk(KERN_ERR
1203 "%s: Memory squeeze, dropping packet.\n",
1204 dev->name);
1205 aup->stats.rx_dropped++;
1206 continue;
1208 skb->dev = dev;
1209 skb_reserve(skb, 2); /* 16 byte IP header align */
1210 eth_copy_and_sum(skb,
1211 (unsigned char *)pDB->vaddr, frmlen, 0);
1212 skb_put(skb, frmlen);
1213 skb->protocol = eth_type_trans(skb, dev);
1214 netif_rx(skb); /* pass the packet to upper layers */
1216 else {
1217 if (au1000_debug > 4) {
1218 if (status & RX_MISSED_FRAME)
1219 printk("rx miss\n");
1220 if (status & RX_WDOG_TIMER)
1221 printk("rx wdog\n");
1222 if (status & RX_RUNT)
1223 printk("rx runt\n");
1224 if (status & RX_OVERLEN)
1225 printk("rx overlen\n");
1226 if (status & RX_COLL)
1227 printk("rx coll\n");
1228 if (status & RX_MII_ERROR)
1229 printk("rx mii error\n");
1230 if (status & RX_CRC_ERROR)
1231 printk("rx crc error\n");
1232 if (status & RX_LEN_ERROR)
1233 printk("rx len error\n");
1234 if (status & RX_U_CNTRL_FRAME)
1235 printk("rx u control frame\n");
1236 if (status & RX_MISSED_FRAME)
1237 printk("rx miss\n");
1240 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1241 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1242 au_sync();
1244 /* next descriptor */
1245 prxd = aup->rx_dma_ring[aup->rx_head];
1246 buff_stat = prxd->buff_stat;
1247 dev->last_rx = jiffies;
1249 return 0;
1253 /*
1254 * Au1000 interrupt service routine.
1255 */
1256 static irqreturn_t au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1258 struct net_device *dev = (struct net_device *) dev_id;
1260 if (dev == NULL) {
1261 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1262 return IRQ_RETVAL(1);
1265 /* Handle RX interrupts first to minimize chance of overrun */
1267 au1000_rx(dev);
1268 au1000_tx_ack(dev);
1269 return IRQ_RETVAL(1);
1273 /*
1274 * The Tx ring has been full longer than the watchdog timeout
1275 * value. The transmitter must be hung?
1276 */
1277 static void au1000_tx_timeout(struct net_device *dev)
1279 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1280 reset_mac(dev);
1281 au1000_init(dev);
1282 dev->trans_start = jiffies;
1283 netif_wake_queue(dev);
1286 static void set_rx_mode(struct net_device *dev)
1288 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1290 if (au1000_debug > 4)
1291 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1293 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1294 aup->mac->control |= MAC_PROMISCUOUS;
1295 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1296 } else if ((dev->flags & IFF_ALLMULTI) ||
1297 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1298 aup->mac->control |= MAC_PASS_ALL_MULTI;
1299 aup->mac->control &= ~MAC_PROMISCUOUS;
1300 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1301 } else {
1302 int i;
1303 struct dev_mc_list *mclist;
1304 u32 mc_filter[2]; /* Multicast hash filter */
1306 mc_filter[1] = mc_filter[0] = 0;
1307 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1308 i++, mclist = mclist->next) {
1309 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
1310 (long *)mc_filter);
1312 aup->mac->multi_hash_high = mc_filter[1];
1313 aup->mac->multi_hash_low = mc_filter[0];
1314 aup->mac->control &= ~MAC_PROMISCUOUS;
1315 aup->mac->control |= MAC_HASH_MODE;
1319 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1321 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1323 if (!netif_running(dev)) return -EINVAL;
1325 if (!aup->phy_dev) return -EINVAL; // PHY not controllable
1327 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1330 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
1332 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1334 if (au1000_debug > 4)
1335 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
1337 if (netif_device_present(dev)) {
1338 return &aup->stats;
1340 return 0;
1343 module_init(au1000_init_module);
1344 module_exit(au1000_cleanup_module);