ia64/linux-2.6.18-xen.hg

view drivers/net/8139cp.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
21 Contributors:
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
48 */
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
69 #include <linux/in.h>
70 #include <linux/ip.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/uaccess.h>
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #else
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
87 #endif
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_VERSION(DRV_VERSION);
96 MODULE_LICENSE("GPL");
98 static int debug = -1;
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104 static int multicast_filter_limit = 32;
105 module_param(multicast_filter_limit, int, 0);
106 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108 #define PFX DRV_NAME ": "
110 #ifndef TRUE
111 #define FALSE 0
112 #define TRUE (!FALSE)
113 #endif
115 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
116 NETIF_MSG_PROBE | \
117 NETIF_MSG_LINK)
118 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120 #define CP_REGS_SIZE (0xff + 1)
121 #define CP_REGS_VER 1 /* version 1 */
122 #define CP_RX_RING_SIZE 64
123 #define CP_TX_RING_SIZE 64
124 #define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
127 CP_STATS_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130 #define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
135 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
136 #define RX_OFFSET 2
137 #define CP_INTERNAL_PHY 32
139 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (6*HZ)
148 /* hardware minimum and maximum for a single frame's data payload */
149 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150 #define CP_MAX_MTU 4096
152 enum {
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
207 RxProtoTCP = 1,
208 RxProtoUDP = 2,
209 RxProtoIP = 3,
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
305 };
307 static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
311 struct cp_desc {
312 u32 opts1;
313 u32 opts2;
314 u64 addr;
315 };
317 struct ring_info {
318 struct sk_buff *skb;
319 dma_addr_t mapping;
320 u32 len;
321 };
323 struct cp_dma_stats {
324 u64 tx_ok;
325 u64 rx_ok;
326 u64 tx_err;
327 u32 rx_err;
328 u16 rx_fifo;
329 u16 frame_align;
330 u32 tx_ok_1col;
331 u32 tx_ok_mcol;
332 u64 rx_ok_phys;
333 u64 rx_ok_bcast;
334 u32 rx_ok_mcast;
335 u16 tx_abort;
336 u16 tx_underrun;
337 } __attribute__((packed));
339 struct cp_extra_stats {
340 unsigned long rx_frags;
341 };
343 struct cp_private {
344 void __iomem *regs;
345 struct net_device *dev;
346 spinlock_t lock;
347 u32 msg_enable;
349 struct pci_dev *pdev;
350 u32 rx_config;
351 u16 cpcmd;
353 struct net_device_stats net_stats;
354 struct cp_extra_stats cp_stats;
356 unsigned rx_tail ____cacheline_aligned;
357 struct cp_desc *rx_ring;
358 struct ring_info rx_skb[CP_RX_RING_SIZE];
359 unsigned rx_buf_sz;
361 unsigned tx_head ____cacheline_aligned;
362 unsigned tx_tail;
364 struct cp_desc *tx_ring;
365 struct ring_info tx_skb[CP_TX_RING_SIZE];
366 dma_addr_t ring_dma;
368 #if CP_VLAN_TAG_USED
369 struct vlan_group *vlgrp;
370 #endif
372 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374 struct mii_if_info mii_if;
375 };
377 #define cpr8(reg) readb(cp->regs + (reg))
378 #define cpr16(reg) readw(cp->regs + (reg))
379 #define cpr32(reg) readl(cp->regs + (reg))
380 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
381 #define cpw16(reg,val) writew((val), cp->regs + (reg))
382 #define cpw32(reg,val) writel((val), cp->regs + (reg))
383 #define cpw8_f(reg,val) do { \
384 writeb((val), cp->regs + (reg)); \
385 readb(cp->regs + (reg)); \
386 } while (0)
387 #define cpw16_f(reg,val) do { \
388 writew((val), cp->regs + (reg)); \
389 readw(cp->regs + (reg)); \
390 } while (0)
391 #define cpw32_f(reg,val) do { \
392 writel((val), cp->regs + (reg)); \
393 readl(cp->regs + (reg)); \
394 } while (0)
397 static void __cp_set_rx_mode (struct net_device *dev);
398 static void cp_tx (struct cp_private *cp);
399 static void cp_clean_rings (struct cp_private *cp);
400 #ifdef CONFIG_NET_POLL_CONTROLLER
401 static void cp_poll_controller(struct net_device *dev);
402 #endif
403 static int cp_get_eeprom_len(struct net_device *dev);
404 static int cp_get_eeprom(struct net_device *dev,
405 struct ethtool_eeprom *eeprom, u8 *data);
406 static int cp_set_eeprom(struct net_device *dev,
407 struct ethtool_eeprom *eeprom, u8 *data);
409 static struct pci_device_id cp_pci_tbl[] = {
410 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
412 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
414 { },
415 };
416 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
418 static struct {
419 const char str[ETH_GSTRING_LEN];
420 } ethtool_stats_keys[] = {
421 { "tx_ok" },
422 { "rx_ok" },
423 { "tx_err" },
424 { "rx_err" },
425 { "rx_fifo" },
426 { "frame_align" },
427 { "tx_ok_1col" },
428 { "tx_ok_mcol" },
429 { "rx_ok_phys" },
430 { "rx_ok_bcast" },
431 { "rx_ok_mcast" },
432 { "tx_abort" },
433 { "tx_underrun" },
434 { "rx_frags" },
435 };
438 #if CP_VLAN_TAG_USED
439 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
440 {
441 struct cp_private *cp = netdev_priv(dev);
442 unsigned long flags;
444 spin_lock_irqsave(&cp->lock, flags);
445 cp->vlgrp = grp;
446 cp->cpcmd |= RxVlanOn;
447 cpw16(CpCmd, cp->cpcmd);
448 spin_unlock_irqrestore(&cp->lock, flags);
449 }
451 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
452 {
453 struct cp_private *cp = netdev_priv(dev);
454 unsigned long flags;
456 spin_lock_irqsave(&cp->lock, flags);
457 cp->cpcmd &= ~RxVlanOn;
458 cpw16(CpCmd, cp->cpcmd);
459 if (cp->vlgrp)
460 cp->vlgrp->vlan_devices[vid] = NULL;
461 spin_unlock_irqrestore(&cp->lock, flags);
462 }
463 #endif /* CP_VLAN_TAG_USED */
465 static inline void cp_set_rxbufsize (struct cp_private *cp)
466 {
467 unsigned int mtu = cp->dev->mtu;
469 if (mtu > ETH_DATA_LEN)
470 /* MTU + ethernet header + FCS + optional VLAN tag */
471 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
472 else
473 cp->rx_buf_sz = PKT_BUF_SZ;
474 }
476 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
477 struct cp_desc *desc)
478 {
479 skb->protocol = eth_type_trans (skb, cp->dev);
481 cp->net_stats.rx_packets++;
482 cp->net_stats.rx_bytes += skb->len;
483 cp->dev->last_rx = jiffies;
485 #if CP_VLAN_TAG_USED
486 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
487 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
488 be16_to_cpu(desc->opts2 & 0xffff));
489 } else
490 #endif
491 netif_receive_skb(skb);
492 }
494 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
495 u32 status, u32 len)
496 {
497 if (netif_msg_rx_err (cp))
498 printk (KERN_DEBUG
499 "%s: rx err, slot %d status 0x%x len %d\n",
500 cp->dev->name, rx_tail, status, len);
501 cp->net_stats.rx_errors++;
502 if (status & RxErrFrame)
503 cp->net_stats.rx_frame_errors++;
504 if (status & RxErrCRC)
505 cp->net_stats.rx_crc_errors++;
506 if ((status & RxErrRunt) || (status & RxErrLong))
507 cp->net_stats.rx_length_errors++;
508 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
509 cp->net_stats.rx_length_errors++;
510 if (status & RxErrFIFO)
511 cp->net_stats.rx_fifo_errors++;
512 }
514 static inline unsigned int cp_rx_csum_ok (u32 status)
515 {
516 unsigned int protocol = (status >> 16) & 0x3;
518 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
519 return 1;
520 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
521 return 1;
522 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
523 return 1;
524 return 0;
525 }
527 static int cp_rx_poll (struct net_device *dev, int *budget)
528 {
529 struct cp_private *cp = netdev_priv(dev);
530 unsigned rx_tail = cp->rx_tail;
531 unsigned rx_work = dev->quota;
532 unsigned rx;
534 rx_status_loop:
535 rx = 0;
536 cpw16(IntrStatus, cp_rx_intr_mask);
538 while (1) {
539 u32 status, len;
540 dma_addr_t mapping;
541 struct sk_buff *skb, *new_skb;
542 struct cp_desc *desc;
543 unsigned buflen;
545 skb = cp->rx_skb[rx_tail].skb;
546 BUG_ON(!skb);
548 desc = &cp->rx_ring[rx_tail];
549 status = le32_to_cpu(desc->opts1);
550 if (status & DescOwn)
551 break;
553 len = (status & 0x1fff) - 4;
554 mapping = cp->rx_skb[rx_tail].mapping;
556 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
557 /* we don't support incoming fragmented frames.
558 * instead, we attempt to ensure that the
559 * pre-allocated RX skbs are properly sized such
560 * that RX fragments are never encountered
561 */
562 cp_rx_err_acct(cp, rx_tail, status, len);
563 cp->net_stats.rx_dropped++;
564 cp->cp_stats.rx_frags++;
565 goto rx_next;
566 }
568 if (status & (RxError | RxErrFIFO)) {
569 cp_rx_err_acct(cp, rx_tail, status, len);
570 goto rx_next;
571 }
573 if (netif_msg_rx_status(cp))
574 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
575 cp->dev->name, rx_tail, status, len);
577 buflen = cp->rx_buf_sz + RX_OFFSET;
578 new_skb = dev_alloc_skb (buflen);
579 if (!new_skb) {
580 cp->net_stats.rx_dropped++;
581 goto rx_next;
582 }
584 skb_reserve(new_skb, RX_OFFSET);
585 new_skb->dev = cp->dev;
587 pci_unmap_single(cp->pdev, mapping,
588 buflen, PCI_DMA_FROMDEVICE);
590 /* Handle checksum offloading for incoming packets. */
591 if (cp_rx_csum_ok(status))
592 skb->ip_summed = CHECKSUM_UNNECESSARY;
593 else
594 skb->ip_summed = CHECKSUM_NONE;
596 skb_put(skb, len);
598 mapping =
599 cp->rx_skb[rx_tail].mapping =
600 pci_map_single(cp->pdev, new_skb->data,
601 buflen, PCI_DMA_FROMDEVICE);
602 cp->rx_skb[rx_tail].skb = new_skb;
604 cp_rx_skb(cp, skb, desc);
605 rx++;
607 rx_next:
608 cp->rx_ring[rx_tail].opts2 = 0;
609 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
610 if (rx_tail == (CP_RX_RING_SIZE - 1))
611 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
612 cp->rx_buf_sz);
613 else
614 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
615 rx_tail = NEXT_RX(rx_tail);
617 if (!rx_work--)
618 break;
619 }
621 cp->rx_tail = rx_tail;
623 dev->quota -= rx;
624 *budget -= rx;
626 /* if we did not reach work limit, then we're done with
627 * this round of polling
628 */
629 if (rx_work) {
630 if (cpr16(IntrStatus) & cp_rx_intr_mask)
631 goto rx_status_loop;
633 local_irq_disable();
634 cpw16_f(IntrMask, cp_intr_mask);
635 __netif_rx_complete(dev);
636 local_irq_enable();
638 return 0; /* done */
639 }
641 return 1; /* not done */
642 }
644 static irqreturn_t
645 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
646 {
647 struct net_device *dev = dev_instance;
648 struct cp_private *cp;
649 u16 status;
651 if (unlikely(dev == NULL))
652 return IRQ_NONE;
653 cp = netdev_priv(dev);
655 status = cpr16(IntrStatus);
656 if (!status || (status == 0xFFFF))
657 return IRQ_NONE;
659 if (netif_msg_intr(cp))
660 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
661 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
663 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
665 spin_lock(&cp->lock);
667 /* close possible race's with dev_close */
668 if (unlikely(!netif_running(dev))) {
669 cpw16(IntrMask, 0);
670 spin_unlock(&cp->lock);
671 return IRQ_HANDLED;
672 }
674 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
675 if (netif_rx_schedule_prep(dev)) {
676 cpw16_f(IntrMask, cp_norx_intr_mask);
677 __netif_rx_schedule(dev);
678 }
680 if (status & (TxOK | TxErr | TxEmpty | SWInt))
681 cp_tx(cp);
682 if (status & LinkChg)
683 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
685 spin_unlock(&cp->lock);
687 if (status & PciErr) {
688 u16 pci_status;
690 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
691 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
692 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
693 dev->name, status, pci_status);
695 /* TODO: reset hardware */
696 }
698 return IRQ_HANDLED;
699 }
701 #ifdef CONFIG_NET_POLL_CONTROLLER
702 /*
703 * Polling receive - used by netconsole and other diagnostic tools
704 * to allow network i/o with interrupts disabled.
705 */
706 static void cp_poll_controller(struct net_device *dev)
707 {
708 disable_irq(dev->irq);
709 cp_interrupt(dev->irq, dev, NULL);
710 enable_irq(dev->irq);
711 }
712 #endif
714 static void cp_tx (struct cp_private *cp)
715 {
716 unsigned tx_head = cp->tx_head;
717 unsigned tx_tail = cp->tx_tail;
719 while (tx_tail != tx_head) {
720 struct sk_buff *skb;
721 u32 status;
723 rmb();
724 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
725 if (status & DescOwn)
726 break;
728 skb = cp->tx_skb[tx_tail].skb;
729 BUG_ON(!skb);
731 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
732 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
734 if (status & LastFrag) {
735 if (status & (TxError | TxFIFOUnder)) {
736 if (netif_msg_tx_err(cp))
737 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
738 cp->dev->name, status);
739 cp->net_stats.tx_errors++;
740 if (status & TxOWC)
741 cp->net_stats.tx_window_errors++;
742 if (status & TxMaxCol)
743 cp->net_stats.tx_aborted_errors++;
744 if (status & TxLinkFail)
745 cp->net_stats.tx_carrier_errors++;
746 if (status & TxFIFOUnder)
747 cp->net_stats.tx_fifo_errors++;
748 } else {
749 cp->net_stats.collisions +=
750 ((status >> TxColCntShift) & TxColCntMask);
751 cp->net_stats.tx_packets++;
752 cp->net_stats.tx_bytes += skb->len;
753 if (netif_msg_tx_done(cp))
754 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
755 }
756 dev_kfree_skb_irq(skb);
757 }
759 cp->tx_skb[tx_tail].skb = NULL;
761 tx_tail = NEXT_TX(tx_tail);
762 }
764 cp->tx_tail = tx_tail;
766 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
767 netif_wake_queue(cp->dev);
768 }
770 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
771 {
772 struct cp_private *cp = netdev_priv(dev);
773 unsigned entry;
774 u32 eor, flags;
775 #if CP_VLAN_TAG_USED
776 u32 vlan_tag = 0;
777 #endif
778 int mss = 0;
780 spin_lock_irq(&cp->lock);
782 /* This is a hard error, log it. */
783 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
784 netif_stop_queue(dev);
785 spin_unlock_irq(&cp->lock);
786 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
787 dev->name);
788 return 1;
789 }
791 #if CP_VLAN_TAG_USED
792 if (cp->vlgrp && vlan_tx_tag_present(skb))
793 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
794 #endif
796 entry = cp->tx_head;
797 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
798 if (dev->features & NETIF_F_TSO)
799 mss = skb_shinfo(skb)->gso_size;
801 if (skb_shinfo(skb)->nr_frags == 0) {
802 struct cp_desc *txd = &cp->tx_ring[entry];
803 u32 len;
804 dma_addr_t mapping;
806 len = skb->len;
807 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
808 CP_VLAN_TX_TAG(txd, vlan_tag);
809 txd->addr = cpu_to_le64(mapping);
810 wmb();
812 flags = eor | len | DescOwn | FirstFrag | LastFrag;
814 if (mss)
815 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
816 else if (skb->ip_summed == CHECKSUM_HW) {
817 const struct iphdr *ip = skb->nh.iph;
818 if (ip->protocol == IPPROTO_TCP)
819 flags |= IPCS | TCPCS;
820 else if (ip->protocol == IPPROTO_UDP)
821 flags |= IPCS | UDPCS;
822 else
823 WARN_ON(1); /* we need a WARN() */
824 }
826 txd->opts1 = cpu_to_le32(flags);
827 wmb();
829 cp->tx_skb[entry].skb = skb;
830 cp->tx_skb[entry].mapping = mapping;
831 cp->tx_skb[entry].len = len;
832 entry = NEXT_TX(entry);
833 } else {
834 struct cp_desc *txd;
835 u32 first_len, first_eor;
836 dma_addr_t first_mapping;
837 int frag, first_entry = entry;
838 const struct iphdr *ip = skb->nh.iph;
840 /* We must give this initial chunk to the device last.
841 * Otherwise we could race with the device.
842 */
843 first_eor = eor;
844 first_len = skb_headlen(skb);
845 first_mapping = pci_map_single(cp->pdev, skb->data,
846 first_len, PCI_DMA_TODEVICE);
847 cp->tx_skb[entry].skb = skb;
848 cp->tx_skb[entry].mapping = first_mapping;
849 cp->tx_skb[entry].len = first_len;
850 entry = NEXT_TX(entry);
852 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
853 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
854 u32 len;
855 u32 ctrl;
856 dma_addr_t mapping;
858 len = this_frag->size;
859 mapping = pci_map_single(cp->pdev,
860 ((void *) page_address(this_frag->page) +
861 this_frag->page_offset),
862 len, PCI_DMA_TODEVICE);
863 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
865 ctrl = eor | len | DescOwn;
867 if (mss)
868 ctrl |= LargeSend |
869 ((mss & MSSMask) << MSSShift);
870 else if (skb->ip_summed == CHECKSUM_HW) {
871 if (ip->protocol == IPPROTO_TCP)
872 ctrl |= IPCS | TCPCS;
873 else if (ip->protocol == IPPROTO_UDP)
874 ctrl |= IPCS | UDPCS;
875 else
876 BUG();
877 }
879 if (frag == skb_shinfo(skb)->nr_frags - 1)
880 ctrl |= LastFrag;
882 txd = &cp->tx_ring[entry];
883 CP_VLAN_TX_TAG(txd, vlan_tag);
884 txd->addr = cpu_to_le64(mapping);
885 wmb();
887 txd->opts1 = cpu_to_le32(ctrl);
888 wmb();
890 cp->tx_skb[entry].skb = skb;
891 cp->tx_skb[entry].mapping = mapping;
892 cp->tx_skb[entry].len = len;
893 entry = NEXT_TX(entry);
894 }
896 txd = &cp->tx_ring[first_entry];
897 CP_VLAN_TX_TAG(txd, vlan_tag);
898 txd->addr = cpu_to_le64(first_mapping);
899 wmb();
901 if (skb->ip_summed == CHECKSUM_HW) {
902 if (ip->protocol == IPPROTO_TCP)
903 txd->opts1 = cpu_to_le32(first_eor | first_len |
904 FirstFrag | DescOwn |
905 IPCS | TCPCS);
906 else if (ip->protocol == IPPROTO_UDP)
907 txd->opts1 = cpu_to_le32(first_eor | first_len |
908 FirstFrag | DescOwn |
909 IPCS | UDPCS);
910 else
911 BUG();
912 } else
913 txd->opts1 = cpu_to_le32(first_eor | first_len |
914 FirstFrag | DescOwn);
915 wmb();
916 }
917 cp->tx_head = entry;
918 if (netif_msg_tx_queued(cp))
919 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
920 dev->name, entry, skb->len);
921 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
922 netif_stop_queue(dev);
924 spin_unlock_irq(&cp->lock);
926 cpw8(TxPoll, NormalTxPoll);
927 dev->trans_start = jiffies;
929 return 0;
930 }
932 /* Set or clear the multicast filter for this adaptor.
933 This routine is not state sensitive and need not be SMP locked. */
935 static void __cp_set_rx_mode (struct net_device *dev)
936 {
937 struct cp_private *cp = netdev_priv(dev);
938 u32 mc_filter[2]; /* Multicast hash filter */
939 int i, rx_mode;
940 u32 tmp;
942 /* Note: do not reorder, GCC is clever about common statements. */
943 if (dev->flags & IFF_PROMISC) {
944 /* Unconditionally log net taps. */
945 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
946 dev->name);
947 rx_mode =
948 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
949 AcceptAllPhys;
950 mc_filter[1] = mc_filter[0] = 0xffffffff;
951 } else if ((dev->mc_count > multicast_filter_limit)
952 || (dev->flags & IFF_ALLMULTI)) {
953 /* Too many to filter perfectly -- accept all multicasts. */
954 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
955 mc_filter[1] = mc_filter[0] = 0xffffffff;
956 } else {
957 struct dev_mc_list *mclist;
958 rx_mode = AcceptBroadcast | AcceptMyPhys;
959 mc_filter[1] = mc_filter[0] = 0;
960 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
961 i++, mclist = mclist->next) {
962 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
964 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
965 rx_mode |= AcceptMulticast;
966 }
967 }
969 /* We can safely update without stopping the chip. */
970 tmp = cp_rx_config | rx_mode;
971 if (cp->rx_config != tmp) {
972 cpw32_f (RxConfig, tmp);
973 cp->rx_config = tmp;
974 }
975 cpw32_f (MAR0 + 0, mc_filter[0]);
976 cpw32_f (MAR0 + 4, mc_filter[1]);
977 }
979 static void cp_set_rx_mode (struct net_device *dev)
980 {
981 unsigned long flags;
982 struct cp_private *cp = netdev_priv(dev);
984 spin_lock_irqsave (&cp->lock, flags);
985 __cp_set_rx_mode(dev);
986 spin_unlock_irqrestore (&cp->lock, flags);
987 }
989 static void __cp_get_stats(struct cp_private *cp)
990 {
991 /* only lower 24 bits valid; write any value to clear */
992 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
993 cpw32 (RxMissed, 0);
994 }
996 static struct net_device_stats *cp_get_stats(struct net_device *dev)
997 {
998 struct cp_private *cp = netdev_priv(dev);
999 unsigned long flags;
1001 /* The chip only need report frame silently dropped. */
1002 spin_lock_irqsave(&cp->lock, flags);
1003 if (netif_running(dev) && netif_device_present(dev))
1004 __cp_get_stats(cp);
1005 spin_unlock_irqrestore(&cp->lock, flags);
1007 return &cp->net_stats;
1010 static void cp_stop_hw (struct cp_private *cp)
1012 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1013 cpw16_f(IntrMask, 0);
1014 cpw8(Cmd, 0);
1015 cpw16_f(CpCmd, 0);
1016 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1018 cp->rx_tail = 0;
1019 cp->tx_head = cp->tx_tail = 0;
1022 static void cp_reset_hw (struct cp_private *cp)
1024 unsigned work = 1000;
1026 cpw8(Cmd, CmdReset);
1028 while (work--) {
1029 if (!(cpr8(Cmd) & CmdReset))
1030 return;
1032 schedule_timeout_uninterruptible(10);
1035 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1038 static inline void cp_start_hw (struct cp_private *cp)
1040 cpw16(CpCmd, cp->cpcmd);
1041 cpw8(Cmd, RxOn | TxOn);
1044 static void cp_init_hw (struct cp_private *cp)
1046 struct net_device *dev = cp->dev;
1047 dma_addr_t ring_dma;
1049 cp_reset_hw(cp);
1051 cpw8_f (Cfg9346, Cfg9346_Unlock);
1053 /* Restore our idea of the MAC address. */
1054 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1055 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1057 cp_start_hw(cp);
1058 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1060 __cp_set_rx_mode(dev);
1061 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1063 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1064 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1065 cpw8(Config3, PARMEnable);
1066 cp->wol_enabled = 0;
1068 cpw8(Config5, cpr8(Config5) & PMEStatus);
1070 cpw32_f(HiTxRingAddr, 0);
1071 cpw32_f(HiTxRingAddr + 4, 0);
1073 ring_dma = cp->ring_dma;
1074 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1075 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1077 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1078 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1079 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1081 cpw16(MultiIntr, 0);
1083 cpw16_f(IntrMask, cp_intr_mask);
1085 cpw8_f(Cfg9346, Cfg9346_Lock);
1088 static int cp_refill_rx (struct cp_private *cp)
1090 unsigned i;
1092 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1093 struct sk_buff *skb;
1095 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1096 if (!skb)
1097 goto err_out;
1099 skb->dev = cp->dev;
1100 skb_reserve(skb, RX_OFFSET);
1102 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1103 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1104 cp->rx_skb[i].skb = skb;
1106 cp->rx_ring[i].opts2 = 0;
1107 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1108 if (i == (CP_RX_RING_SIZE - 1))
1109 cp->rx_ring[i].opts1 =
1110 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1111 else
1112 cp->rx_ring[i].opts1 =
1113 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1116 return 0;
1118 err_out:
1119 cp_clean_rings(cp);
1120 return -ENOMEM;
1123 static void cp_init_rings_index (struct cp_private *cp)
1125 cp->rx_tail = 0;
1126 cp->tx_head = cp->tx_tail = 0;
1129 static int cp_init_rings (struct cp_private *cp)
1131 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1132 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1134 cp_init_rings_index(cp);
1136 return cp_refill_rx (cp);
1139 static int cp_alloc_rings (struct cp_private *cp)
1141 void *mem;
1143 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1144 if (!mem)
1145 return -ENOMEM;
1147 cp->rx_ring = mem;
1148 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1150 return cp_init_rings(cp);
1153 static void cp_clean_rings (struct cp_private *cp)
1155 unsigned i;
1157 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1158 if (cp->rx_skb[i].skb) {
1159 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1160 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1161 dev_kfree_skb(cp->rx_skb[i].skb);
1165 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1166 if (cp->tx_skb[i].skb) {
1167 struct sk_buff *skb = cp->tx_skb[i].skb;
1169 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1170 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1171 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1172 dev_kfree_skb(skb);
1173 cp->net_stats.tx_dropped++;
1177 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1178 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1180 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1181 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1184 static void cp_free_rings (struct cp_private *cp)
1186 cp_clean_rings(cp);
1187 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1188 cp->rx_ring = NULL;
1189 cp->tx_ring = NULL;
1192 static int cp_open (struct net_device *dev)
1194 struct cp_private *cp = netdev_priv(dev);
1195 int rc;
1197 if (netif_msg_ifup(cp))
1198 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1200 rc = cp_alloc_rings(cp);
1201 if (rc)
1202 return rc;
1204 cp_init_hw(cp);
1206 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1207 if (rc)
1208 goto err_out_hw;
1210 netif_carrier_off(dev);
1211 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1212 netif_start_queue(dev);
1214 return 0;
1216 err_out_hw:
1217 cp_stop_hw(cp);
1218 cp_free_rings(cp);
1219 return rc;
1222 static int cp_close (struct net_device *dev)
1224 struct cp_private *cp = netdev_priv(dev);
1225 unsigned long flags;
1227 if (netif_msg_ifdown(cp))
1228 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1230 spin_lock_irqsave(&cp->lock, flags);
1232 netif_stop_queue(dev);
1233 netif_carrier_off(dev);
1235 cp_stop_hw(cp);
1237 spin_unlock_irqrestore(&cp->lock, flags);
1239 synchronize_irq(dev->irq);
1240 free_irq(dev->irq, dev);
1242 cp_free_rings(cp);
1243 return 0;
1246 #ifdef BROKEN
1247 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1249 struct cp_private *cp = netdev_priv(dev);
1250 int rc;
1251 unsigned long flags;
1253 /* check for invalid MTU, according to hardware limits */
1254 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1255 return -EINVAL;
1257 /* if network interface not up, no need for complexity */
1258 if (!netif_running(dev)) {
1259 dev->mtu = new_mtu;
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1261 return 0;
1264 spin_lock_irqsave(&cp->lock, flags);
1266 cp_stop_hw(cp); /* stop h/w and free rings */
1267 cp_clean_rings(cp);
1269 dev->mtu = new_mtu;
1270 cp_set_rxbufsize(cp); /* set new rx buf size */
1272 rc = cp_init_rings(cp); /* realloc and restart h/w */
1273 cp_start_hw(cp);
1275 spin_unlock_irqrestore(&cp->lock, flags);
1277 return rc;
1279 #endif /* BROKEN */
1281 static const char mii_2_8139_map[8] = {
1282 BasicModeCtrl,
1283 BasicModeStatus,
1284 0,
1285 0,
1286 NWayAdvert,
1287 NWayLPAR,
1288 NWayExpansion,
1290 };
1292 static int mdio_read(struct net_device *dev, int phy_id, int location)
1294 struct cp_private *cp = netdev_priv(dev);
1296 return location < 8 && mii_2_8139_map[location] ?
1297 readw(cp->regs + mii_2_8139_map[location]) : 0;
1301 static void mdio_write(struct net_device *dev, int phy_id, int location,
1302 int value)
1304 struct cp_private *cp = netdev_priv(dev);
1306 if (location == 0) {
1307 cpw8(Cfg9346, Cfg9346_Unlock);
1308 cpw16(BasicModeCtrl, value);
1309 cpw8(Cfg9346, Cfg9346_Lock);
1310 } else if (location < 8 && mii_2_8139_map[location])
1311 cpw16(mii_2_8139_map[location], value);
1314 /* Set the ethtool Wake-on-LAN settings */
1315 static int netdev_set_wol (struct cp_private *cp,
1316 const struct ethtool_wolinfo *wol)
1318 u8 options;
1320 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1321 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts) {
1323 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1324 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1327 cpw8 (Cfg9346, Cfg9346_Unlock);
1328 cpw8 (Config3, options);
1329 cpw8 (Cfg9346, Cfg9346_Lock);
1331 options = 0; /* Paranoia setting */
1332 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1333 /* If WOL is being disabled, no need for complexity */
1334 if (wol->wolopts) {
1335 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1336 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1337 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1340 cpw8 (Config5, options);
1342 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1344 return 0;
1347 /* Get the ethtool Wake-on-LAN settings */
1348 static void netdev_get_wol (struct cp_private *cp,
1349 struct ethtool_wolinfo *wol)
1351 u8 options;
1353 wol->wolopts = 0; /* Start from scratch */
1354 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1355 WAKE_MCAST | WAKE_UCAST;
1356 /* We don't need to go on if WOL is disabled */
1357 if (!cp->wol_enabled) return;
1359 options = cpr8 (Config3);
1360 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1361 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1363 options = 0; /* Paranoia setting */
1364 options = cpr8 (Config5);
1365 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1366 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1367 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1370 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1372 struct cp_private *cp = netdev_priv(dev);
1374 strcpy (info->driver, DRV_NAME);
1375 strcpy (info->version, DRV_VERSION);
1376 strcpy (info->bus_info, pci_name(cp->pdev));
1379 static int cp_get_regs_len(struct net_device *dev)
1381 return CP_REGS_SIZE;
1384 static int cp_get_stats_count (struct net_device *dev)
1386 return CP_NUM_STATS;
1389 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391 struct cp_private *cp = netdev_priv(dev);
1392 int rc;
1393 unsigned long flags;
1395 spin_lock_irqsave(&cp->lock, flags);
1396 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1397 spin_unlock_irqrestore(&cp->lock, flags);
1399 return rc;
1402 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1404 struct cp_private *cp = netdev_priv(dev);
1405 int rc;
1406 unsigned long flags;
1408 spin_lock_irqsave(&cp->lock, flags);
1409 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1410 spin_unlock_irqrestore(&cp->lock, flags);
1412 return rc;
1415 static int cp_nway_reset(struct net_device *dev)
1417 struct cp_private *cp = netdev_priv(dev);
1418 return mii_nway_restart(&cp->mii_if);
1421 static u32 cp_get_msglevel(struct net_device *dev)
1423 struct cp_private *cp = netdev_priv(dev);
1424 return cp->msg_enable;
1427 static void cp_set_msglevel(struct net_device *dev, u32 value)
1429 struct cp_private *cp = netdev_priv(dev);
1430 cp->msg_enable = value;
1433 static u32 cp_get_rx_csum(struct net_device *dev)
1435 struct cp_private *cp = netdev_priv(dev);
1436 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1439 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1441 struct cp_private *cp = netdev_priv(dev);
1442 u16 cmd = cp->cpcmd, newcmd;
1444 newcmd = cmd;
1446 if (data)
1447 newcmd |= RxChkSum;
1448 else
1449 newcmd &= ~RxChkSum;
1451 if (newcmd != cmd) {
1452 unsigned long flags;
1454 spin_lock_irqsave(&cp->lock, flags);
1455 cp->cpcmd = newcmd;
1456 cpw16_f(CpCmd, newcmd);
1457 spin_unlock_irqrestore(&cp->lock, flags);
1460 return 0;
1463 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1464 void *p)
1466 struct cp_private *cp = netdev_priv(dev);
1467 unsigned long flags;
1469 if (regs->len < CP_REGS_SIZE)
1470 return /* -EINVAL */;
1472 regs->version = CP_REGS_VER;
1474 spin_lock_irqsave(&cp->lock, flags);
1475 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1476 spin_unlock_irqrestore(&cp->lock, flags);
1479 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1481 struct cp_private *cp = netdev_priv(dev);
1482 unsigned long flags;
1484 spin_lock_irqsave (&cp->lock, flags);
1485 netdev_get_wol (cp, wol);
1486 spin_unlock_irqrestore (&cp->lock, flags);
1489 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1491 struct cp_private *cp = netdev_priv(dev);
1492 unsigned long flags;
1493 int rc;
1495 spin_lock_irqsave (&cp->lock, flags);
1496 rc = netdev_set_wol (cp, wol);
1497 spin_unlock_irqrestore (&cp->lock, flags);
1499 return rc;
1502 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1504 switch (stringset) {
1505 case ETH_SS_STATS:
1506 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1507 break;
1508 default:
1509 BUG();
1510 break;
1514 static void cp_get_ethtool_stats (struct net_device *dev,
1515 struct ethtool_stats *estats, u64 *tmp_stats)
1517 struct cp_private *cp = netdev_priv(dev);
1518 struct cp_dma_stats *nic_stats;
1519 dma_addr_t dma;
1520 int i;
1522 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1523 if (!nic_stats)
1524 return;
1526 /* begin NIC statistics dump */
1527 cpw32(StatsAddr + 4, (u64)dma >> 32);
1528 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1529 cpr32(StatsAddr);
1531 for (i = 0; i < 1000; i++) {
1532 if ((cpr32(StatsAddr) & DumpStats) == 0)
1533 break;
1534 udelay(10);
1536 cpw32(StatsAddr, 0);
1537 cpw32(StatsAddr + 4, 0);
1538 cpr32(StatsAddr);
1540 i = 0;
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1543 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1544 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1545 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1546 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1547 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1548 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1554 tmp_stats[i++] = cp->cp_stats.rx_frags;
1555 BUG_ON(i != CP_NUM_STATS);
1557 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1560 static struct ethtool_ops cp_ethtool_ops = {
1561 .get_drvinfo = cp_get_drvinfo,
1562 .get_regs_len = cp_get_regs_len,
1563 .get_stats_count = cp_get_stats_count,
1564 .get_settings = cp_get_settings,
1565 .set_settings = cp_set_settings,
1566 .nway_reset = cp_nway_reset,
1567 .get_link = ethtool_op_get_link,
1568 .get_msglevel = cp_get_msglevel,
1569 .set_msglevel = cp_set_msglevel,
1570 .get_rx_csum = cp_get_rx_csum,
1571 .set_rx_csum = cp_set_rx_csum,
1572 .get_tx_csum = ethtool_op_get_tx_csum,
1573 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1574 .get_sg = ethtool_op_get_sg,
1575 .set_sg = ethtool_op_set_sg,
1576 .get_tso = ethtool_op_get_tso,
1577 .set_tso = ethtool_op_set_tso,
1578 .get_regs = cp_get_regs,
1579 .get_wol = cp_get_wol,
1580 .set_wol = cp_set_wol,
1581 .get_strings = cp_get_strings,
1582 .get_ethtool_stats = cp_get_ethtool_stats,
1583 .get_perm_addr = ethtool_op_get_perm_addr,
1584 .get_eeprom_len = cp_get_eeprom_len,
1585 .get_eeprom = cp_get_eeprom,
1586 .set_eeprom = cp_set_eeprom,
1587 };
1589 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1591 struct cp_private *cp = netdev_priv(dev);
1592 int rc;
1593 unsigned long flags;
1595 if (!netif_running(dev))
1596 return -EINVAL;
1598 spin_lock_irqsave(&cp->lock, flags);
1599 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1600 spin_unlock_irqrestore(&cp->lock, flags);
1601 return rc;
1604 /* Serial EEPROM section. */
1606 /* EEPROM_Ctrl bits. */
1607 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1608 #define EE_CS 0x08 /* EEPROM chip select. */
1609 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1610 #define EE_WRITE_0 0x00
1611 #define EE_WRITE_1 0x02
1612 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1613 #define EE_ENB (0x80 | EE_CS)
1615 /* Delay between EEPROM clock transitions.
1616 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1617 */
1619 #define eeprom_delay() readl(ee_addr)
1621 /* The EEPROM commands include the alway-set leading bit. */
1622 #define EE_EXTEND_CMD (4)
1623 #define EE_WRITE_CMD (5)
1624 #define EE_READ_CMD (6)
1625 #define EE_ERASE_CMD (7)
1627 #define EE_EWDS_ADDR (0)
1628 #define EE_WRAL_ADDR (1)
1629 #define EE_ERAL_ADDR (2)
1630 #define EE_EWEN_ADDR (3)
1632 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1634 static void eeprom_cmd_start(void __iomem *ee_addr)
1636 writeb (EE_ENB & ~EE_CS, ee_addr);
1637 writeb (EE_ENB, ee_addr);
1638 eeprom_delay ();
1641 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1643 int i;
1645 /* Shift the command bits out. */
1646 for (i = cmd_len - 1; i >= 0; i--) {
1647 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1648 writeb (EE_ENB | dataval, ee_addr);
1649 eeprom_delay ();
1650 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1651 eeprom_delay ();
1653 writeb (EE_ENB, ee_addr);
1654 eeprom_delay ();
1657 static void eeprom_cmd_end(void __iomem *ee_addr)
1659 writeb (~EE_CS, ee_addr);
1660 eeprom_delay ();
1663 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1664 int addr_len)
1666 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1668 eeprom_cmd_start(ee_addr);
1669 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1670 eeprom_cmd_end(ee_addr);
1673 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1675 int i;
1676 u16 retval = 0;
1677 void __iomem *ee_addr = ioaddr + Cfg9346;
1678 int read_cmd = location | (EE_READ_CMD << addr_len);
1680 eeprom_cmd_start(ee_addr);
1681 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1683 for (i = 16; i > 0; i--) {
1684 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1685 eeprom_delay ();
1686 retval =
1687 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1688 0);
1689 writeb (EE_ENB, ee_addr);
1690 eeprom_delay ();
1693 eeprom_cmd_end(ee_addr);
1695 return retval;
1698 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1699 int addr_len)
1701 int i;
1702 void __iomem *ee_addr = ioaddr + Cfg9346;
1703 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1705 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1707 eeprom_cmd_start(ee_addr);
1708 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1709 eeprom_cmd(ee_addr, val, 16);
1710 eeprom_cmd_end(ee_addr);
1712 eeprom_cmd_start(ee_addr);
1713 for (i = 0; i < 20000; i++)
1714 if (readb(ee_addr) & EE_DATA_READ)
1715 break;
1716 eeprom_cmd_end(ee_addr);
1718 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1721 static int cp_get_eeprom_len(struct net_device *dev)
1723 struct cp_private *cp = netdev_priv(dev);
1724 int size;
1726 spin_lock_irq(&cp->lock);
1727 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1728 spin_unlock_irq(&cp->lock);
1730 return size;
1733 static int cp_get_eeprom(struct net_device *dev,
1734 struct ethtool_eeprom *eeprom, u8 *data)
1736 struct cp_private *cp = netdev_priv(dev);
1737 unsigned int addr_len;
1738 u16 val;
1739 u32 offset = eeprom->offset >> 1;
1740 u32 len = eeprom->len;
1741 u32 i = 0;
1743 eeprom->magic = CP_EEPROM_MAGIC;
1745 spin_lock_irq(&cp->lock);
1747 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1749 if (eeprom->offset & 1) {
1750 val = read_eeprom(cp->regs, offset, addr_len);
1751 data[i++] = (u8)(val >> 8);
1752 offset++;
1755 while (i < len - 1) {
1756 val = read_eeprom(cp->regs, offset, addr_len);
1757 data[i++] = (u8)val;
1758 data[i++] = (u8)(val >> 8);
1759 offset++;
1762 if (i < len) {
1763 val = read_eeprom(cp->regs, offset, addr_len);
1764 data[i] = (u8)val;
1767 spin_unlock_irq(&cp->lock);
1768 return 0;
1771 static int cp_set_eeprom(struct net_device *dev,
1772 struct ethtool_eeprom *eeprom, u8 *data)
1774 struct cp_private *cp = netdev_priv(dev);
1775 unsigned int addr_len;
1776 u16 val;
1777 u32 offset = eeprom->offset >> 1;
1778 u32 len = eeprom->len;
1779 u32 i = 0;
1781 if (eeprom->magic != CP_EEPROM_MAGIC)
1782 return -EINVAL;
1784 spin_lock_irq(&cp->lock);
1786 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1788 if (eeprom->offset & 1) {
1789 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1790 val |= (u16)data[i++] << 8;
1791 write_eeprom(cp->regs, offset, val, addr_len);
1792 offset++;
1795 while (i < len - 1) {
1796 val = (u16)data[i++];
1797 val |= (u16)data[i++] << 8;
1798 write_eeprom(cp->regs, offset, val, addr_len);
1799 offset++;
1802 if (i < len) {
1803 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1804 val |= (u16)data[i];
1805 write_eeprom(cp->regs, offset, val, addr_len);
1808 spin_unlock_irq(&cp->lock);
1809 return 0;
1812 /* Put the board into D3cold state and wait for WakeUp signal */
1813 static void cp_set_d3_state (struct cp_private *cp)
1815 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1816 pci_set_power_state (cp->pdev, PCI_D3hot);
1819 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1821 struct net_device *dev;
1822 struct cp_private *cp;
1823 int rc;
1824 void __iomem *regs;
1825 resource_size_t pciaddr;
1826 unsigned int addr_len, i, pci_using_dac;
1827 u8 pci_rev;
1829 #ifndef MODULE
1830 static int version_printed;
1831 if (version_printed++ == 0)
1832 printk("%s", version);
1833 #endif
1835 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1837 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1838 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1839 dev_err(&pdev->dev,
1840 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1841 pdev->vendor, pdev->device, pci_rev);
1842 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1843 return -ENODEV;
1846 dev = alloc_etherdev(sizeof(struct cp_private));
1847 if (!dev)
1848 return -ENOMEM;
1849 SET_MODULE_OWNER(dev);
1850 SET_NETDEV_DEV(dev, &pdev->dev);
1852 cp = netdev_priv(dev);
1853 cp->pdev = pdev;
1854 cp->dev = dev;
1855 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1856 spin_lock_init (&cp->lock);
1857 cp->mii_if.dev = dev;
1858 cp->mii_if.mdio_read = mdio_read;
1859 cp->mii_if.mdio_write = mdio_write;
1860 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1861 cp->mii_if.phy_id_mask = 0x1f;
1862 cp->mii_if.reg_num_mask = 0x1f;
1863 cp_set_rxbufsize(cp);
1865 rc = pci_enable_device(pdev);
1866 if (rc)
1867 goto err_out_free;
1869 rc = pci_set_mwi(pdev);
1870 if (rc)
1871 goto err_out_disable;
1873 rc = pci_request_regions(pdev, DRV_NAME);
1874 if (rc)
1875 goto err_out_mwi;
1877 pciaddr = pci_resource_start(pdev, 1);
1878 if (!pciaddr) {
1879 rc = -EIO;
1880 dev_err(&pdev->dev, "no MMIO resource\n");
1881 goto err_out_res;
1883 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1884 rc = -EIO;
1885 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1886 (unsigned long long)pci_resource_len(pdev, 1));
1887 goto err_out_res;
1890 /* Configure DMA attributes. */
1891 if ((sizeof(dma_addr_t) > 4) &&
1892 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1893 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1894 pci_using_dac = 1;
1895 } else {
1896 pci_using_dac = 0;
1898 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1899 if (rc) {
1900 dev_err(&pdev->dev,
1901 "No usable DMA configuration, aborting.\n");
1902 goto err_out_res;
1904 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1905 if (rc) {
1906 dev_err(&pdev->dev,
1907 "No usable consistent DMA configuration, "
1908 "aborting.\n");
1909 goto err_out_res;
1913 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1914 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1916 regs = ioremap(pciaddr, CP_REGS_SIZE);
1917 if (!regs) {
1918 rc = -EIO;
1919 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1920 (unsigned long long)pci_resource_len(pdev, 1),
1921 (unsigned long long)pciaddr);
1922 goto err_out_res;
1924 dev->base_addr = (unsigned long) regs;
1925 cp->regs = regs;
1927 cp_stop_hw(cp);
1929 /* read MAC address from EEPROM */
1930 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1931 for (i = 0; i < 3; i++)
1932 ((u16 *) (dev->dev_addr))[i] =
1933 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1934 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1936 dev->open = cp_open;
1937 dev->stop = cp_close;
1938 dev->set_multicast_list = cp_set_rx_mode;
1939 dev->hard_start_xmit = cp_start_xmit;
1940 dev->get_stats = cp_get_stats;
1941 dev->do_ioctl = cp_ioctl;
1942 dev->poll = cp_rx_poll;
1943 #ifdef CONFIG_NET_POLL_CONTROLLER
1944 dev->poll_controller = cp_poll_controller;
1945 #endif
1946 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1947 #ifdef BROKEN
1948 dev->change_mtu = cp_change_mtu;
1949 #endif
1950 dev->ethtool_ops = &cp_ethtool_ops;
1951 #if 0
1952 dev->tx_timeout = cp_tx_timeout;
1953 dev->watchdog_timeo = TX_TIMEOUT;
1954 #endif
1956 #if CP_VLAN_TAG_USED
1957 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1958 dev->vlan_rx_register = cp_vlan_rx_register;
1959 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1960 #endif
1962 if (pci_using_dac)
1963 dev->features |= NETIF_F_HIGHDMA;
1965 #if 0 /* disabled by default until verified */
1966 dev->features |= NETIF_F_TSO;
1967 #endif
1969 dev->irq = pdev->irq;
1971 rc = register_netdev(dev);
1972 if (rc)
1973 goto err_out_iomap;
1975 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1976 "%02x:%02x:%02x:%02x:%02x:%02x, "
1977 "IRQ %d\n",
1978 dev->name,
1979 dev->base_addr,
1980 dev->dev_addr[0], dev->dev_addr[1],
1981 dev->dev_addr[2], dev->dev_addr[3],
1982 dev->dev_addr[4], dev->dev_addr[5],
1983 dev->irq);
1985 pci_set_drvdata(pdev, dev);
1987 /* enable busmastering and memory-write-invalidate */
1988 pci_set_master(pdev);
1990 if (cp->wol_enabled)
1991 cp_set_d3_state (cp);
1993 return 0;
1995 err_out_iomap:
1996 iounmap(regs);
1997 err_out_res:
1998 pci_release_regions(pdev);
1999 err_out_mwi:
2000 pci_clear_mwi(pdev);
2001 err_out_disable:
2002 pci_disable_device(pdev);
2003 err_out_free:
2004 free_netdev(dev);
2005 return rc;
2008 static void cp_remove_one (struct pci_dev *pdev)
2010 struct net_device *dev = pci_get_drvdata(pdev);
2011 struct cp_private *cp = netdev_priv(dev);
2013 BUG_ON(!dev);
2014 unregister_netdev(dev);
2015 iounmap(cp->regs);
2016 if (cp->wol_enabled)
2017 pci_set_power_state (pdev, PCI_D0);
2018 pci_release_regions(pdev);
2019 pci_clear_mwi(pdev);
2020 pci_disable_device(pdev);
2021 pci_set_drvdata(pdev, NULL);
2022 free_netdev(dev);
2025 #ifdef CONFIG_PM
2026 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2028 struct net_device *dev;
2029 struct cp_private *cp;
2030 unsigned long flags;
2032 dev = pci_get_drvdata (pdev);
2033 cp = netdev_priv(dev);
2035 if (!dev || !netif_running (dev)) return 0;
2037 netif_device_detach (dev);
2038 netif_stop_queue (dev);
2040 spin_lock_irqsave (&cp->lock, flags);
2042 /* Disable Rx and Tx */
2043 cpw16 (IntrMask, 0);
2044 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2046 spin_unlock_irqrestore (&cp->lock, flags);
2048 pci_save_state(pdev);
2049 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2050 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2052 return 0;
2055 static int cp_resume (struct pci_dev *pdev)
2057 struct net_device *dev = pci_get_drvdata (pdev);
2058 struct cp_private *cp = netdev_priv(dev);
2059 unsigned long flags;
2061 if (!netif_running(dev))
2062 return 0;
2064 netif_device_attach (dev);
2066 pci_set_power_state(pdev, PCI_D0);
2067 pci_restore_state(pdev);
2068 pci_enable_wake(pdev, PCI_D0, 0);
2070 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2071 cp_init_rings_index (cp);
2072 cp_init_hw (cp);
2073 netif_start_queue (dev);
2075 spin_lock_irqsave (&cp->lock, flags);
2077 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2079 spin_unlock_irqrestore (&cp->lock, flags);
2081 return 0;
2083 #endif /* CONFIG_PM */
2085 static struct pci_driver cp_driver = {
2086 .name = DRV_NAME,
2087 .id_table = cp_pci_tbl,
2088 .probe = cp_init_one,
2089 .remove = cp_remove_one,
2090 #ifdef CONFIG_PM
2091 .resume = cp_resume,
2092 .suspend = cp_suspend,
2093 #endif
2094 };
2096 static int __init cp_init (void)
2098 #ifdef MODULE
2099 printk("%s", version);
2100 #endif
2101 return pci_module_init (&cp_driver);
2104 static void __exit cp_exit (void)
2106 pci_unregister_driver (&cp_driver);
2109 module_init(cp_init);
2110 module_exit(cp_exit);